Improving the Performance
of Flyback Power Supplies
By Jon Mark Hancock, Senior Applications Engineer,
Infineon Technologies NA, San Jose, Calif.
Innovative MOSFETs and flyback controllers
help designers meet challenging efficiency
and power density requirements, while also
satisfying demands for reliability and low cost.
T
he “lowly” flyback switched-mode power
supply (SMPS) is still a workhorse in the
power supply business for requirements below
100 W, but the requirements for a good design
are getting tougher all the time. Energy-savings
initiatives are now putting pressure on both mid- and fullload efficiency, and the requirements for ultralow standby
power have reached new lows (Table 1) and are decreasing
even further.
For example, just throwing a larger primary-side
MOSFET at the problem to reduce the I2  R losses due to
high peak currents in a discontinuous conduction mode
(DCM) flyback SMPS can be counterproductive. That’s
because the fixed switching loss components due to output
capacitance COSS pumping can make for real problems in
controlling standby power or ultralight load operating losses.
Yet requirements for improved power density even in lowcost applications would seem to mandate cooler running
SMPSs operating at higher switching frequencies.
Protection functionality is also critical to building
cost-effective power supplies, because any need to oversize
components to deal with overload stresses has an adverse
impact on cost. However, the alternative can be to
compromise reliability, a factor we seem to take for granted
in modern power electronics.
Rated Input Power
In this article, we’ll take a look at these challenges in
the context of a 60-W to 80-W flyback SMPS design, and
investigate how to satisfy conflicting requirements for
density, efficiency, hold-up time, reliability and cost. These
challenges can be addressed with some innovative component
technologies in MOSFETs and flyback controllers. We’ll take
an in-depth look at a few key design points for the power
stage and how component behavior affects our ability to hit
challenging performance, size and cost targets. We’ll also see
how some innovations in controller design aid in meeting
standby power targets as well as robust protection.
Performance Challenges
The outer envelope of the operating specification
requirements for the flyback SMPS will set the boundary
conditions for the design and the component challenges. The
combination of the maximum output power requirement,
plus the worst-case low-ac-line voltage and cycle-skip
hold-up time requirements will be crucial. These factors
will determine the maximum operating current for the
power MOSFET, as well as the requirements for the
flyback transformer and the rectified high-voltage dc bus
capacitor.
Pivotal to these requirements is the selected minimum dc
voltage for the flyback converter to operate without losing
regulation. Key losses include the conduction loss of the
MOSFET, which is aggravated by the high peak current in
DCM operation relative to RMS power, and the switching
crossover loss of the MOSFET, which is similarly increased
by the high peak current at turn-off.
On the other side of the operating envelope, no-load
operation at high line will incur losses in the MOSFET due
to the combination of parasitic switching losses. Those
parasitic-related losses are a function of the square of the
rectified line voltage and the COSS output capacitance of the
MOSFET, the transformer capacitance and the reflected
capacitance of the secondary-side rectifier diode. Combined
with the normal housekeeping requirements for the
No-Load Power Consumption
Phase 1
1.1.2001
Phase 2
1.2.2003
Phase 3
1.1.2005
0.3 W and < 15 W
1.0 W
0.75 W
0.3 W
15 W and < 50 W
1.0 W
0.75 W
0.50 W
50 W and < 75 W
1.0 W
0.75 W
0.75 W
Table 1. European Commission Code of Conduct Standby Power
Requirements.
www.powerelectronics.com
33
Power Electronics Technology September 2005
FLYBACK SMPS
Si_Limit_RON = rAREA � VDSS2.5
15
14 �m pitch (S5, C3)
RON/area (Ω/mm2)
7.5 �m pitch (C3, CP)
Fig. 1. The 60-W flyback demo board shown here uses through-hole
component technology and conventional heatsinks.
10
5
0
controller IC, the losses in the MOSFET make hitting standby
power targets very difficult without taking special measures.
In principle, meeting performance targets at both ends of the
spectrum requires a switching FET with low RDS(ON), as well
as very low output capacitance and gate charge.
Let’s examine a specific design example, one not too
different from what is encountered frequently in practice.
We’ll take on an older 60-W flyback design (Fig. 1)
using through-hole components, and upgrade it to an
80-W design with surface-mount components with higher
efficiency and very low standby power. Our target here
will be to completely eliminate the heatsink for the primaryside MOSFET switch by lowering the conduction and
0
200
400
Blocking Voltage (V)
600
800
Fig. 2. The area-specific RON of 14-µm and 7.5-µm superjunction FETs
falls below the silicon limit line for conventional DMOS devices.
switching losses, while delivering significant reductions in
standby power.
80-W Flyback Design
The main performance requirements for this design are
spelled out in the load and line specifications. In this case,
the output voltage is typical of adapter requirements for
notebook computers and printers.
Minimum ac input voltage: 90 Vac
Maximum ac input voltage: 265 Vac
Output voltage: 16 V
Maximum output overshoot, full load to no load: 250 mV
Maximum output power: 80 W
Target efficiency η at full load: 80%+
Hold-up time at 115-Vac drop, full load: 20 ms
No-load standby power, 90 Vac to 265 Vac: < 0.5 W
The maximum input power is a function of the output
power and converter efficiency:
Booth 1419
PIN max =
POUT max
= 100 W
η
Eq. 1
To design for low line and cycle-skip hold-up time
requirements, a minimum dc bus regulation voltage target
must be selected, and the dc bus filter capacitor requirements
must be calculated. The lower the minimum dc bus
regulation voltage, the smaller and lower the cost of the
bulk bus capacitor. However, this places higher requirements
on the MOSFET and transformer, as higher peak primary
current is required. For this design, the minimum dc bulk
capacitor voltage regulation target VDCmin = 90 Vdc. For
20-ms holdup from a nominal ac line voltage of 115 V, first
calculate the peak bus capacitor voltage at line dropout:
VDCtypPK = VACnom × 2 = 115 × 2 = 162.63 V
Eq. 2
Then the required hold-up capacitance CBULKnom is
calculated from:
Eq. 3
2 × POUT max × THOLDUP
C BULKnom =
= 217 µF
2
2
(VDCtypP
DCtypPK
K − VD
DC
C mi
min
n )× η
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FLYBACK SMPS
12
6.E-06
C3
5.E-06
25% Lower
10
C5
Gate Voltage VGS (V)
8
3.E-06
2.E-06
1.E-06
0.E+00
0
50
100
150
200
250
300
350
400
Fig. 3. A comparison of the two generations of CoolMOS devices
reveals that the C5-generation MOSFETs exhibit lower COSS energy
than C3-generation MOSFETs.
2
0
10
20
30
Gate Charge (nC)
40
50
Max RDS(ON)
(m)
Package
CO(ER)
(pF)
QG
(nC)
IRFPC60LC
400
TO-247
~125
120
SPP11N60C3
380
TO-220
45
45
IPD60N385CP
385
DPAK
36
17
Table 2. Comparing ~380-m,
, 600-V FETs manufactured in different

process technologies.
and a state-of-the-art 600-V, 7.5-µm pitch transistor
(IPD60N385CP). The latter extends an RDS(ON) class to
the TO-252 (DPAK) surface-mount package, which in
conventional technologies required a TO-247 package, while
reducing dynamic losses related to COSS (Fig. 3) and gate
charge (Fig. 4) even in comparison to existing superjunction
MOSFETs.
Let’s examine the predicted loss situation with the
IPD60N385CP. Conduction losses for worst-case operation
can be estimated using high-temperature values for
RDS(ON):
2 × PIN max
= 3.227 A
VDC min PK × DMAX
MA
Eq. 4
And the primary RMS current can be calculated from:
DMAX
MA
= 1.331 A
3
Eq. 5
This value is an aid in estimating the MOSFET and
transformer primary conduction losses.
Since the introduction of superjunction technology using
the charge compensation principle for the MOSFET drain
region[1,2], significant advances have been made in chip size
and parasitic capacitance of high-voltage MOSFETs. Fig. 2
illustrates the intrinsic conventional epitaxial drift region
limitation versus voltage (red trace), usually referred to as
the “silicon limit line.” The area-specific RON of the original
14-µm cell pitch superjunction transistor is shown for
blocking voltages of 500 V through 800 V in the yellow
plot line, and is characteristic of the CoolMOS C3 and S5
processes. The newest superjunction technology is realized
with a 7.5-µm cell pitch technology (blue plot line). This
technology achieves substantially lower area-specific RON
with a value of 2.4 /mm2 at 625 V.
Corresponding improvements have been made in
device capacitance, both the COSS output capacitance and
the gate input capacitance, which determines gate charge.
This comparison is shown in Table 2, which illustrates the
difference in characteristics for state-of-the-art low gate
charge conventional DMOS 600-V devices (IRFPC60LC),
a mainstream superjunction transistor (SPP11N60C3),
Power Electronics Technology September 2005
CoolMOS C5
CoolMOS C3
Fig. 4. Comparison of gate charge for 380-m C3 and C5.
Selecting the nearest-size standard value, the high-voltage
dc bus capacitor will be 220 µF. Next, the peak and RMS
primary side current can be estimated, which will guide the
MOSFET switch selection. The peak primary current IPRI lpk
is a function of the required input power, duty-cycle limit
of 0.5 for DCM operation, and minimum bus regulation
voltage VDCminPK:
IPRI lrms = IPRI lpk
lpk ×
4
0
VDS (V)
IPRI lpk =
6
2
Pd CONDUCTION = (IRM
RMSS ) × R DS(ON
ON ) (TJ ) = 1.03 W
Eq. 6
For the DCM flyback converter, turn-on is at zero current
and is nearly lossless. Turn-off losses are the primary concern,
and are a function of turn-off switching time, snubber
networks and the device technology. The strongly nonlinear
capacitance, which contributes to the higher COSS energy at
low voltages (Fig. 3), also acts as a nonlinear snubber during
turn-off, making the calculation of turn-off losses inexact.
For the flyback supply, they could be estimated using:
(
Pd SWITCHING =
(
E (J)
4.E-06
VDCtypPK
2
� ISWpk
× (TOF
OFF
F ) × f S = 0.71 W
Eq. 7
Here ISWpk is the peak current on the primary at turn-off,
fS is the switching frequency (110 kHz in this design), and
VDCtypPK is the dc bus voltage at low line. These calculations
suggest a worst-case MOSFET power dissipation under
2 W, which is highly amenable to surface-mount operation
36
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FLYBACK SMPS
C5
2.2 nF
C3
+
BR1
C3a
220 �F 0.22 �F
47 �F
C11
4
2
N/C
HV
FB
CS/ISENSE
VCC
SOFTST
0.47 �F
4
8
2200 �F
D3
100 nF
16 V Return
Gate
4
R9
R6
R7
750 � 1 k�
T1
PGND PQ-2620/2625
IPD60R385CP
C14
1 nF
90 Vac - 265 Vac
TB2
1
2
R2
22 k�
27 �
R11 22 �
3
1
4
2
R8b
R8a
0.47 � 0.47 �
R3
12 k�
C10
Q1
ICE3DS01G
TB1
C8
2200 �F
Ns1
5
1N4148
3
2
8
F1
T5A
GND
U1
Ns2
Output +16 V
C7
C6a C6b
+
+
330 �F +
3
5
7
1
3
NTC1
C1 0.22 �F
1
3
1 �H
6
6
2.27 mH/0.9 A
ZPD18
C13
9
L3
Aux
R10
100 �
C12 1 �F
ZD1
2
2
C2
11
D1
UF4006
L5
1
Ns3
Np1
C4
4.7 nF
R1
47 k�
43CTQ100
12
1
2.7 nF
R5
C9
10 k�
0.68 �F
IC3
TL431
IC2
SFH617A
R4
4.3 k�
PGND
Fig. 5. An 80-W, 16-V output flyback SMPS is designed using the IPD60R385CP, a 600-V MOSFET fabricated in Infineon’s 7.5-µm cell pitch
superjunction process.
the turns should be rounded down, then, considering the
estimated peak diode forward voltage VVDIODE, reflection
voltage on the primary V RMAX (100 V), and VOUT, the
secondary turns for the first cut, can be calculated:
with a small foil area (~6 cm2) on the MOSFET drain for
the heatsink.
From the peak primary current and target switching
frequency (set by the controller), the primary inductance
requirement of the flyback transformer can be calculated:
L PRI
NS =
DMAXX × VDC min
= MA
= 119 µH
IPRI lpk × f S
Eq. 10
Now, this is another point that is somewhat “iterative,”
as the secondary side current hasn’t been calculated or the
diode selected. Due to the right triangle shape of the current
waveform, the peak current is quite high, as are the I2R losses,
so minimizing the conduction loss in the rectifier diode is
a key factor in achieving good overall efficiency. The peak
semiconductor stresses become quite high as the power
level increases.
Next, the reverse voltage for the rectifier diode (VRDIODE),
and the diode’s peak and RMS currents are calculated:
Eq. 8
Assuming a maximum flux density of 0.12 T to 0.3 T
(0.2 T, typical), a core can be selected from vendors’ data
sheets, considering core area, ambient cooling conditions,
material behavior at high frequencies, winding window, etc.
Many cores might be suitable for this application, such as an
ETD30 or ER35W, but with parts on hand in the lab, I chose
a PQ2625 from Magnetics Inc. (Pittsburgh). The core set gap
must be chosen for an AL product that supports a reasonable
turns count for magnetic coupling primary-to-secondary,
and for the target inductance to achieve the required output
power while keeping the flux within reasonable limits at a
duty cycle at or below 0.5. In practice, this can be an iterative
process, evaluating off-the-shelf gap selections, calculating
the AL product, the required turns for the target inductance
and the estimated flux excursion. With a gap around 2 mm,
the PQ2625’s AL=55 x 10-9. The number of primary turns
can then be calculated as:
NP =
(
VRDIODE = VOUT + VDC max PPKK ×
)
NS
= 46.5111 V
NP
Eq. 11
Considering voltage overshoots due to parasitic
inductance, a rating of 100 V or more is needed:
NP
= 23.1
NS
1
= IDIODEpk
× DMAX = 9.24
24 A
DIODEpk ×
3
IDIODEpk = ILPRI
PRI ×
IDIODErms
L PRI
= 46.7
AL
Eq. 12
Eq. 13
While low-cost fast diodes like the MUR1520 are often
used in this application, a 100-V Schottky diode is a choice
Eq. 9
To be able to reach the required peak primary current,
Power Electronics Technology September 2005
N PRI × (VOUT + VVDIODE )
= 7.751
VRMAX
38
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FLYBACK SMPS
Tek Stop: 100 kS/s
11 Acqs
T
[
Tek Stop: 25.0 MS/s
DPO Brightness: 60%
]
1
1
2
2
68 Acqs
T
[
]
T
Drain Signal
Gate Signal
T
Ch 1
50.0 V
Ch 2
5.00 V
M50.0 �s
Ch 1
30 V
Ch 1
Fig. 6. Burst-mode waveforms are shown for drain (upper) and gate
(lower) with the time scale at 50 s/div.
50.0 V
Ch 2
5.00 V
M 2.0O �s
Ch 1
30 V
Fig. 7. Burst-mode detail is revealed when gate and drain waveforms
are measured with the time scale at 2 s/div.
to consider if reducing the output diode VF by 200 mV is
attractive or necessary for hitting efficiency targets. In this
design application, a 100-V Shottky diode was used (Fig. 5).
Before considering the controller, one other critical
element for the flyback design is the output capacitor
selection. Output capacitors are highly stressed in flyback
converters. Normally, the capacitor will be selected for three
major parameters:
Tek Stop: 50.0 MS/s
10 Acqs
T
[
]
T
1
Drain Signal
Gate Signal
T
2
50.0 V
5.00 V
M 1.00 �s
Ch 1
30 V
1. Capacitance value, related to controlling voltage
overshoot in the case of switch-off at maximum load
condition (typically 10 to 20 clock cycles at fS).
2. Low ESR, to meet output voltage ripple requirements
as a function of the actual output current ripple current
delivery.
3. Ripple current rating, to handle the internal dissipation
and heating as a result of the high ripple current at the output
of DCM flyback SMPS.
All of these criteria must be met in selecting output
capacitors. For this design, the targeted maximum allowable
voltage overshoot was set at V
VOUT=0.25 V, and to be safe, the
number of clock periods for loop overshoot control was set
to nCP=20, while the maximum output load current:
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ILOAD max =
Helping Engineer
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•
Ch 2
Fig. 8. Sample switching waveforms for the gate and drain of the
SPP07N60 MOSFET in a 60-W flyback SMPS. Time scale is 1 µs/div.
More power to you.
w w w. i c e c o m p o n e n t s . c o m • ( 8 0 0 ) 7 2 9 - 2 0 9 9
Ch 1
IOUT max
=5 A
VOUT
ISO 9001/9002
Then, the required COUT can be calculated:
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FLYBACK SMPS
Tek Stop. 50.0 MS/s
6 Acqs
T
[
]
0.845
0.840
Efficiency
0.835
0.830
0.825
Power Out vs Efficiency 90 Vac
Power Out vs Efficiency 110 Vac
Power Out vs Efficiency 220 Vac
Power Out vs Efficiency 265 Vac
0.820
T
1
0.815
0
20
30
T
2
Ch 1
50.0 V
Ch 2
5.00 V
40
50
60
70
80
Output Power (W)
M 1.0O �s
Ch 1
30 V
Fig. 10. The efficiency of the 80-W flyback SMPS is plotted versus power
output under varying line voltage conditions.
Fig. 9. Sample switching waveforms for the gate and drain of the
IPD60R385 MOSFET in an 80-W flyback SMPS. Time scale is 1 µs/div.
Keep in mind that a further spike ripple filter may be
employed after the primary output filter caps.
I
× n CP
C OUT LOAD max
= 3636 µF
∆VOUT × f S
Eq. 14
The required ESR can be estimated from the peak diode
current and desired ripple voltage, where:
VOUTripple 200 mV
R ESR =
=
= 8.6 mΩ
IDIODEpk
23 A
Flyback SMPS Controller
The ICE3DS01 controller selected for this application
is a stand-alone PWM controller for flyback applications.
This controller is part of a family developed from the
controller architecture of the third-generation integrated
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41
Power Electronics Technology September 2005
FLYBACK SMPS
PWM + Power transistor CoolSET products. [3] The
development for this controller was focused on reducing
standby power consumption through several measures.
For instance, an integrated high-voltage MOS startup cell is
used, eliminating the losses from startup resistors. The startup
cell turns off once the VCC is within the normal regulation
window from the auxiliary power winding. An active burst
mode is employed for regulation at low output power levels;
this is done with active control within the feedback loop,
and ensures maintaining an accurate output voltage while
operating the PWM switch at a very low, effective duty cycle. In
Fig. 6, while operating with regulated output voltage at
no-load, the burst pulse repetition rate drops to a little over
100 ms. Reducing the time scale to 2 µs/div in Fig. 7 reveals
details of the gate and drain switching waveforms.
For comparison, sample switching waveforms are shown
for the 60-W flyback SMPS using the SPP07N60 MOSFET
(Fig. 8) and the 80-W flyback SMPS using the IPD60R385
(Fig. 9), both running at full load (60 W and 80 W,
respectively) at 115 Vac. Due to similarities in the resonant
frequencies from transformer leakage
inductance and C O S S , other than
switching times (which are lower for
the IPD60R385CP), the waveforms are
very similar.
The efficiency of the 80-W flyback
Applications
SMPS from Fig. 5 was measured at
selected line voltages, for 20-W, 40-W,
60-W and 80-W output power. The
results are shown in Fig. 10. Efficiency
was over 80% for any of the tested
conditions, comfortably exceeding the
target requirements. Standby power was
APT75GN60B
also checked at 110 Vac and 265 Vac. In
both cases it was difficult to measure
standby power with high accuracy
because it was so low, apparently below
120 mW. This is consistent with other
application boards using the ICE3DS01,
which for 20-W to 40-W output are
usually under 100 mW.
PETech
Low VSAT 600V IGBT
For Industrial
APT200GN60J
APT100GN60B2
www.advancedpower.com
Tel: 541-382-8028
References
1. Deboy, G.; März, M.; Stengl, J.;
Strack, H.; Tihanyi, J.; Wever, H. “A New
Generation of High Voltage MOSFETs
Breaks the Limit of Silicon,” pp. 26.2.126.2.3, Proc. IEDM 98, San Francisco,
December 1998.
2. Saggio, M.; Fagone, D.; and Musumeci,
S. “MDmesh: Innovative Technology for
High Voltage Power MOSFETs,” pp. 6568, Proc. ISPSD 200, Toulouse, France,
May 2000.
3. Zoellinger, H. “CoolSET ICE3DS01
Current Mode Controller for Off-Line
Switch Mode Power Supply,” Application
Note AN-SMPS-ICE3DS01-1, Infineon
Technologies, AG.
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www.powerelectronics.com.
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