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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 3, MARCH 2004
26–42 GHz SOI CMOS Low Noise Amplifier
Frank Ellinger, Member, IEEE
Abstract—A complementary metal–oxide semiconductor
(CMOS) single-stage cascode low-noise amplifier (LNA) is presented in this paper. The microwave monolithic integrated circuit
(MMIC) is fabricated using digital 90-nm silicon-on-insulator
(SOI) technology. All impedance matching and bias elements are
implemented on the compact chip, which has a size of 0.6 mm
0.3 mm. The supply voltage and supply current are 2.4 V and
17 mA, respectively. At 35 GHz and 50 source/load impedances,
a gain of 11.9 dB, a noise figure of 3.6 dB, an output compression
point of 4 dBm, an input return loss of 6 dB, and an output return
loss of 18 dB are measured. The 3-dB frequency bandwidth
ranges from 26 to 42 GHz. All results include the pad parasitics.
To the knowledge of the author, the results are by far the best
for a silicon-based millimeter-wave LNA reported to date. The
LNA is well suited for systems operating in accordance to the
local multipoint distribution service (LMDS) standards at 28 and
38 GHz and the multipoint video distribution system (MVDS)
standard at 42 GHz.
Index Terms—CMOS, low-noise amplifier (LNA), millimeterwave frequency, MMIC, silicon-on-insulator (SOI).
I. INTRODUCTION
U
NTIL today, the fastest transistors are fabricated using
III/V-based technologies. State-of-the-art transit frequencies up to 562 GHz have been reported for indium phospide
(InP) pseudomorphic high electron mobility transistors
(pHEMTs) [1]. In the past, III/V-based technologies were the
only choice for millimeter-wave applications. Unfortunately,
due to the limited transistor yield, III/V-based circuits have
high costs and allow only low circuit complexities.
In recent years, the speed gap between III/V- and silicon-based technologies has been significantly decreased.
Silicon germanium (SiGe) heterojunction bipolar transistors
(HBTs) with of 350 GHz [2] and silicon-on-insulator (SOI)
up to 243 GHz [3] have been
CMOS technologies with
reported. For digital applications, CMOS technologies have
important advantages regarding the power consumption. This
is a major reason why CMOS plays a dominant role within the
digital market. To allow single-chip solutions, analog designers
also have to use CMOS technologies. Most CMOS technologies are optimized for digital applications, making the design
of analog circuits a demanding task. The enhancement strategy
of digital CMOS technologies focuses on the optimization of
transistors rather than of passive devices. However, passive
devices such as inductors, transmission lines, and pads are
important for analog designs. Device and metal dimensions are
Manuscript received August 12, 2003; revised November 10, 2003.
The author is with the Swiss Federal Institute of Technology (ETH) Zurich,
Electronics Laboratory, Switzerland, and IBM/ETH Center for Advanced Silicon Electronics, Zurich, Switzerland (e-mail: ellinger@ife.ee.ethz.ch).
Digital Object Identifier 10.1109/JSSC.2003.822895
scaled down to increase the transistor speed and the integration
density. Unfortunately, this degrades the performance of
passive devices [4]. Major reasons are the following.
• The coupling to the lossy substrate is increased due to
the lowering of the distance between conductor metal and
substrate.
• The parasitic resistance of lines is increased due to the
thinning and cheesing of the metals.
• Metal filling, typically up to 40%, is required for yield reasons. This increases the capacitive coupling to the lossy
substrate since the metal pieces act as highly conductive
bridges. Filling exclusion is strongly limited or not allowed at all.
• Furthermore, most digital processes feature no metal–insulator–metal (MIM) capacitors with high dielectric constant and small distance between the metal plates. Thus,
the MIM capacitors require a large area. Consequently,
they have a strong coupling to the lossy substrate resulting
in high losses.
Despite these restrictions, this paper shows that excellent millimeter-wave amplifiers with low noise and high gain can be
realized by using SOI CMOS technology. Compared to conventional bulk technology, the implementation of a thin isolation
layer between the active transistor area and the substrate allows
a higher substrate resistivity without degrading the threshold
properties of the field effect transistors (FETs). Consequently,
the parasitics of the transistors are reduced, thereby increasing
. Furthermore, passive components with higher
their and
factors and operation frequencies can be realized.
As summarized in Table I, the highest operation frequencies
for SiGe bipolar [5] and CMOS amplifiers [6], [7] reported
to date are around 24 GHz. With 11.9-dB gain and 3.6-dB
noise figure around 35 GHz, this work improves the current
state-of-the-art performances of silicon-based millimeter-wave
amplifiers. The major task of this work was the exploration of
the frequency limits of the SOI CMOS technology that was
used. Due to its large 3-dB bandwidth from 26 to 42 GHz, the
low-noise amplifier (LNA) is suited for various applications at
the Ka-band, e.g., for systems operating in accordance to the
LMDS standard at 28 and 38 GHz and the MVDS standard at
42 GHz.
II. DEVICES
The LNA was fabricated using a digital IBM SOI CMOS
technology, which features FETs with gate length of 90 nm
and a metal stack with eight metals. The substrate resistivity of
cm. For further information conthe technology is
cerning the technology, refer to [3].
0018-9200/04$20.00 © 2004 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 3, MARCH 2004
523
TABLE I
COMPARISON WITH STATE-OF-THE-ART MICROWAVE AND MILLIMETER-WAVE LNAs
A. Field Effect Transistors
For analog amplifiers, the maximum frequency of oscillation
is more important than the maximum , since
is
a benchmark for the maximum available power gain. Consequently, the n-channel FET that was used was optimized for
rather than for . Experimental FET test structures with
different gate widths and number of gate fingers were designed,
measured, and compared to optimize the geometry of a FET
with total gate width of 64 m. This gate width was chosen
since it allows simple impedance matching. Corresponding details will be discussed in Section III. The investigation showed
that for this gate width, a structure with 64 fingers is well suited
.
to reach a high
An HP 8510 XF network analyzer was used for device characterization up to 100 GHz. In Fig. 1, the measured magnitude of
, the maximum stable gain (MSG), and the
the current gain
maximum available gain (MAG) of the FET are plotted versus
frequency. The FET was biased at the maximum drain–source
of 1 V. For yield constraints of the technology, no
voltage
higher
should be applied. The threshold voltage of the tranof
sistor is approximately 0.25 V. A gate–source voltage
of
0.5 V was fed corresponding to a current density
0.25 mA m. Fig. 2 demonstrates that this current density is
a good compromise between high power gain and moderate
supply current. Thus, this bias point is well suited for the LNA.
of 147 GHz and a of 149 GHz were extracted from
A
the measurements. At 40 GHz, the MSG of the FET is 10 dB.
of 160 GHz can be reached at a current density
A peak
of 0.4 mA m. It is noted that the latest hardware of the techof up to 208 GHz [3].
nology demonstrates devices with
The measured input and output reflection coefficients of the
FET are plotted in Fig. 3. At 26.5 GHz, a minimum noise figure
of approximately 2 dB was measured for a similar FET
of around 2.6 dB can be exgeometry [3]. At 35 GHz, an
curve.
trapolated by considering the gradient of the
B. Inductive Transmission Lines
Inductive elements with high quality factor are mandatory
to reach high gain and low noise figure. At millimeter-wave
Fig. 1. Measured f
and f versus frequency at V = 0:5 V, V = 1 V
and I = 16 mA corresponding to a current density of 0.25 mA=m.
Fig. 2.
Measured f
at V
= 1 V versus current density.
frequencies, inductive lines are well suited for the realization
of inductances. Compared to coplanar transmission lines, microstrip lines are preferred since they have a higher effective inductance per length. Thus, the lines can be kept compact. This is
important to minimize the area determining the coupling to the
lossy substrate. With line length , line width , distance from
the bottom plate of the line to the ground , and the magnetic
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 3, MARCH 2004
Fig. 5. Shunted inductive transmission line. (a) Equivalent circuit.
(b) Introduction of R and C to ease calculation of Q.
TABLE II
ELEMENT VALUES OF SCALABLE INDUCTIVE TRANSMISSION LINE
Fig. 3. Measured input and output reflection coefficients of FET from 1 to
100 GHz at V = 1 V, V = 0:5 V, I = 16 mA.
Fig. 4. Simplified cross view of transmission line, C
= 0 :5 C .
Fig. 6.
L
constant , the inductance
proximated by [14]
Measured and simulated S-parameters from 1 to 60 GHz of line with
=S ,S =S .
= 0:195 nH. S
of a microstrip line can be ap-
(1)
A cross view of an inductive microstrip line as used in this
work is shown in Fig. 4. The top conductor metal is made of
copper and has a thickness of approximately 1 m and a distance
from the bottom plate to the lossy substrate of around 7 m.
In theory, it is assumed that microstrip lines have a ground
only at the bottom of the substrate. The distance from the line to
the other grounded metal plates is assumed to be infinity. However, due to layout constraints of MMIC circuits, the distance of
the line to the common ground metal of the circuit cannot be
set to infinity. In this work, is approximately 15 m. Thus, in
has to be
practice, the corresponding coplanar capacitance
considered.
were investigated and
The free design parameters and
optimized using the Ansoft 3-D high-frequency structure simulator (HFFS) [15]. For the required inductance values and the
related , the optimum is approximately 5 m. At this , optimum factors were reached for inductor values typically required for amplifiers operating around 40 GHz. Thus, this was
chosen for the lines.
Inductive lines can be applied as series or shunt elements. The
use of shunted lines is advantageous since toward the shunted
port, a significant amount of the substrate parasitics is shunted.
Thus, the corresponding losses are smaller and the related
factor is higher. In Fig. 5(a), the equivalent circuit of a shunted
is shown. The modeling of the
line with desired inductance
transmission line by means of a lumped equivalent network
allows simple derivation and optimization of the quality factor
. The relevant parasitics are the metal resistance , the oxide
, the substrate resistance
, and
. Due to
capacitance
the thin metal thickness of the line, the skin effect and the correis relatively weak. Thus,
sponding frequency dependence of
for simplicity,
is assumed to be independent of the frequency.
The element values of the equivalent circuit of the line are
, the model is scaleable with
listed in Table II. For
. The top metal was used to maximize the distance to the
lossy substrate and to minimize the corresponding substrate
losses. In Fig. 6, a comparison between measured and modeled
-parameters of a line with
m is shown from 1 to
60 GHz. Good agreement is reached. At 40 GHz, this line has
an inductance of 0.195 nH. The corresponding characteristic
wave impedance of the line is approximately 120 . Similarly
of the lines can be
to the considerations made in [16], the
calculated by
(2)
This definition is valid only for frequencies below the self-resonance frequency, where the magnetic energy dominates. To ease
the calculations, we introduce the elements
(3)
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 3, MARCH 2004
525
Fig. 9.
Measured and simulated insertion loss of signal pad.
Fig. 7. Q factor, low-frequency Q factor Q , substrate loss factor SLF, and
self-resonance loss factor RLF of line with L = 0:195 nH.
Fig. 8. Equivalent circuit of signal pad.
and
(4)
This is illustrated in Fig. 5(b). With (2)–(4), we get
Fig. 10.
Simplified equivalent circuit of the LNA.
D. RF Shunt Capacitors
(5)
SLF RLF
(6)
, the substrate loss factor
with the low-frequency factor
SLF, and the self-resonance loss factor RLF. The factor, the
, the SLF, and the RLF versus frequency of the 0.195-nH
line are depicted in Fig. 7. A high peak quality factor of 20.5
is reached at 50 GHz, making the inductive line well suited
for low-noise applications. The corresponding SLF and RLF
are 0.87 and 0.8, respectively. At the resonance frequency of
110 GHz, the RLF and the factor equal zero.
C. Signal Pads
The three top metals are used for the realization of the signal
m
m. The signal pad is
pads, which have a size of
conmodeled using the equivalent circuit shown in Fig. 8.
siders the resistive losses of the oxide. The measured and simulated insertion loss are plotted in Fig. 9. Good agreement up to
100 GHz is achieved. At 35 GHz and 50- reference impedance,
an insertion loss of only 0.2 dB was measured.
The process features MOSFET capacitors with a high
capacitance per area of approximately 11.5 fF m , making
them well suited for radio frequency (RF) shunts. Unfortunately, they have a high parasitic substrate capacitance,
resulting in a high insertion loss. Thus, they are not suited as
series dc-blocking or impedance-matching capacitors.
E. MIM Capacitor
Capacitors with high factors are required for impedance
matching and dc blocking. MIM-type capacitors offer high
factors, typically above 50 at millimeter-wave frequencies. Unfortunately, the technology used here features no MIM capacitors. However, the metal plates of the metal stack can be used
for the realization of a MIM capacitor. Due to the low dielectric material constant within the metal stack and the relative
large metal distance, the capacitance per area is relatively low.
An efficient technique to increase the capacitance density is the
use of vertical parallel plate capacitors [17].
In this work, the bottom metal of the signal pad is reused as
capacitor plate to minimize the parasitic substrate capacitances.
Together with the following metal, it is used for dc blocking.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 3, MARCH 2004
Fig. 11. Photograph of the MMIC with overall chip size of 0.6 mm
TL: RF shorted inductive transmission lines.
2 0.3 mm. The design rules of the digital CMOS technology require metal filling and cheesing.
With a metal-to-metal distance of 0.4 m and a
of 2.7, we
obtain a capacitance per area of approximately 0.1 fF m .
III. DESIGN OF LOW-NOISE AMPLIFIER
A BSIM SOI MOSFET large-signal model is used for the
simulation of the circuit. Originally, this model was optimized
for digital rather than for analog applications. Compared to a
common-source stage, cascode circuits have higher RF power
gain. This is attributed to the reduced Miller effect and the increased output resistance. Consequently, a cascode circuit is
used for the LNA. For detailed information concerning LNA
theory and design concepts of cascode amplifiers, refer to [18]
and [19].
Inductive source degeneration is frequently used to make the
input impedance of the transistor more resistive, thereby simplifying the input matching. A further advantage of this technique is that the matching for maximum gain and minimum
noise figure move closer together [20]. Unfortunately, inductive
source degeneration decreases the equivalent transconductance,
which can be approximated by
limited by the area of the signal pad. A capacitor covering
the whole signal pad has a value of 270 fF.
4) A transistor size is chosen that meets requirements 1–3 as
much as possible. Simulations show that transistors with
a total gate width of 64 m are well suited to meet the
discussed requirements. For information concerning the
bias and the impedance characteristics of this FET, refer
to Section II-A.
The simplified circuit schematic of the LNA and the final element values are illustrated in Fig. 10. The drain–source voltage
of each transistor is approximately 1 V. For stability reasons,
resistors are implemented in the bias connections. They prevent
resonances between the RF shunt capacitance and the inductance of the dc probes. The gate of the common-gate circuit is
terminated by a RF shunt capacitor and biased by a high ohmic
resistor.
A photograph of the compact MMIC with overall chip size of
0.6 mm 0.3 mm is shown in Fig. 11. Due to the design rules of
the digital CMOS technology, the lines are cheesed. According
to metal density rules, the overall chip area is filled with metal
pieces. The filling densities are in the range of 15%–40%.
IV. RESULTS OF LOW-NOISE AMPLIFIER
with the transconductance without inductive source degenera, the source inductance
and the gate source capacition
. Since it is challenging to reach sufficient gain at such
tance
high frequencies as targeted in this work, no inductive source
degeneration is used. To reach adequate matching to 50 and
maximum performance at the target frequency, the following design considerations are made.
1) The matching network is minimized by reusing the
mandatory LC bias elements, which are the series
dc-block capacitors and the shunted bias inductors. The
application of additional elements should be avoided.
factor at the
2) Inductor values having their maximum
target frequency are used. Between 30–40 GHz, inductors
with values between 0.3 and 0.4 nH have maximum .
Consequently these values are preferred.
3) To minimize the losses, the bottom plate of the pad is
used as a part of the dc-block capacitor as described in
Section II-E. The maximum value of the capacitance is
The circuit was measured on wafer. All measurements were
performed at source and load impedances of 50 and include
the losses of the pads. -parameters were measured using the HP
8510 XF network analyzer. The noise figure setup consists of an
HP 8970 B noise figure meter, an HP 8971C test set extension,
and an external mixer, allowing measurements between 26 and
40 GHz. An HP 436 A power meter was used for determination
of the compression point. The applied supply voltage and supply
current of the LNA are 2.4 V and 17 mA, respectively. At this
bias point, the circuit is unconditionally stable.
In Fig. 12, the measured and simulated gain and noise figure
versus frequency are shown. The corresponding return losses are
depicted in Fig. 13. At a frequency of 35 GHz, a gain of 11.9 dB,
a low noise figure of 3.6 dB, an input return loss of 6 dB, and an
output return loss of 18 dB were measured. The achieved noise
of the FET.
figure is only 1 dB higher than the extrapolated
The measured gain of the cascode is 1.9 dB higher than the MSG
of the single FET. An input return loss of around 10 dB would be
possible by applying inductive source degeneration. However,
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 3, MARCH 2004
Fig. 12. Measured and simulated gain and noise figure, V
17 mA.
= 2:4 V, I
527
=
Shunted inductive transmission lines have been used for gain
and noise matching. A high factor of 20.5 at 40 GHz and a
high self-resonance frequency of 110 GHz has been reached for
a typical inductance with 0.195 nH. A simple circuit topology
has been applied to minimize the number of required passive
elements. Some elements have been reused for different tasks.
This design strategy is efficient to minimize the high substrate
losses of CMOS technologies at high frequencies.
With 11.9-dB gain and 3.6-dB noise figure at a frequency
of 35 GHz, this work significantly improves the current
state-of-the-art performances of CMOS millimeter-wave
amplifiers. The achieved results are even better than the best
reported using SiGe HBT technologies. The work clearly shows
the excellent suitability of digital SOI CMOS technologies for
analog circuits at millimeter-wave frequencies. Not long ago,
this frequency range has been an exclusive domain of III/V
technologies.
ACKNOWLEDGMENT
Fig. 13.
Measured and simulated return losses, V
= 2:4 V, I
= 17 mA.
simulations predict a degradation of the gain of approximately
1.2 dB. Between the 3-dB frequency bandwidth ranging from
26 and 42 GHz, an output compression point above 4 dBm was
measured. Up to 50 GHz, the measured reverse isolation
is higher than 25 dB. This high reverse isolation is attributed to
the high substrate resistivity of the SOI technology.
Good agreement between measured and simulated -parameters was obtained. However, the accuracy of the BSIM SOI
FET model that was used is limited in terms of noise because
it was optimized for digital rather than for analog applications.
The predicted noise figure is approximately 1–1.5 dB lower than
measured. It is noted that the technology used and the models
are still in the development phase.
V. CONCLUSION
A millimeter-wave CMOS LNA operating within a 3-dB frequency bandwidth from 26 to 42 GHz has been presented. The
LNA is suited for various applications at the Ka-band, e.g., for
systems operating in accordance to the LMDS and MVDS standards. All matching and biasing elements have been integrated
on the MMIC. A 90-nm SOI technology has been used for fabrication. Although this process has been optimized for digital
rather than for analog applications, excellent results have been
reached.
The author would like to thank Dr. M. Schmatz, Zurich
Research Laboratory (ZRL), IBM Research, Zurich, Switzerland, for the organization of the chip area, his efforts during
the wafer run and the management of the IBM/ETH Center
for Advanced Silicon Electronics (CASE). For their support
concerning CASE, the author would like to acknowledge
Prof. Dr. H. Jäckel, Electronics Laboratory (IfE), ETH Zurich,
Zurich, Switzerland, and Prof. Dr. W. Bächtold, Laboratory
for Microwave Electronics and Electromagnetic Waves (IFH),
ETH Zurich, Switzerland. The author would like to thank
L. C. Rodoni, G. Sialm, and C. Kromer, all with CASE, for the
teamwork during the wafer run. The author would also like to
acknowledge Dr. C. Menolfi, Dr. M. Kossel, Dr. T. Toifl, and
Dr. T. Morf, all with ZRL, for sharing their excellent expertise
concerning the design environment, and H. Benedikter, IFH,
for his help concerning millimeter-wave measurements and for
providing measurement equipment. The helpful comments of
the reviewers were highly appreciated.
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Frank Ellinger (S’97–M’01) was born in
Friedrichshafen, Germany, in 1972. He received the
Masters degree in electrical engineering from the
University of Ulm, Ulm, Germany, in 1996, and the
M.B.A. and Ph.D. degrees in electrical engineering
from the Swiss Federal Institute of Technology
(ETH), Zürich, Switzerland, in 2001.
In 2001, he was with the Wireless Marketing Division of Infineon, Munich, Germany. Since 2001, he
has been head of the RFIC design group of the Electronics Laboratory at the ETH and Project Leader of
the IBM/ETH Competence Center for advanced silicon electronics. His main
research interests are the modeling and design of silicon and GaAs-based RF
circuits for high-speed wireless and optical communication. He is a Lecturer in
this area at the ETH. He has authored over 30 reviewed IEEE papers and several
patents.
Dr. Ellinger was Program Chair of the Workshop on Compound Semiconductor Devices and Integrated Circuits Europe (WOCSDICE) in 2003. He was
the recipient of the Young Ph.D. Award of the ETH (Bonus 29), the ETH Medal
for outstanding Ph.D. theses, and the Denzler Award of the Swiss Electrotechnical Association (SEV).