Low Voltage Differential Signaling 7:1
UG0645 User Guide
Table of Contents
Introduction ....................................................................................................................3
Hardware Implementation .............................................................................................5
Design Description......................................................................................................................................... 5
Inputs and Outputs ........................................................................................................................................ 6
Timing Diagrams............................................................................................................................................ 8
Performance Statistics ................................................................................................................................... 9
Resource Utilizations ................................................................................................................................... 10
List of Changes ............................................................................................................ 11
Product Support........................................................................................................... 12
Customer Service ........................................................................................................................................ 12
Customer Technical Support Center ........................................................................................................... 12
Technical Support ........................................................................................................................................ 12
Website ........................................................................................................................................................ 12
Contacting the Customer Technical Support Center ................................................................................... 12
ITAR Technical Support .............................................................................................................................. 13
2
UG0645: Low Voltage Differential Signaling User Guide
Introduction
Low voltage differential signaling (LVDS) is a high-speed, low power general purpose interface standard. The
standard, known as ANSI/TIA/EIA-644, was approved in March 1996. LVDS uses differential signaling with a nominal
signal swing of 350 mV differential. The low-signal swing decreases rise and fall times to achieve a theoretical
maximum transmission rate of 1.923 Gbps into a loss-less medium. The low-signal swing is also the standard not
dependent on a particular supply voltage.
LVDS uses current-mode drivers, which limit the power consumption. The differential signals are immune to ±1 V
common voltage noise. Camera Link Specifications 1-2 Channel Link National Semiconductor originally developed
the Channel Link technology as a solution for flat panel displays, using LVDS for the physical layer. The technology
was then extended into a method for general purpose data transmission. Channel Link consists of a driver and
receiver pair. The driver accepts 28 single-ended data signals and a single-ended clock. The data is 7:1 serialized,
and the four data streams and a dedicated clock are driven over five LVDS pairs. The receiver accepts all four LVDS
data streams and an LVDS clock, and then drives the 28 bits and the clock to the board.
Figure 1 shows Top-Level Block Diagram of 4-Channels LVDS 7:1.
Figure 1 · Top-Level Block Diagram of 4-Channels LVDS 7:1
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UG0645: Low Voltage Differential Signaling User Guide
Inputs and Outputs
The LVDS 7:1 interface is a source synchronous interface, which consists of multiple data bits and a clock. The
Microsemi LVDS 7:1 solution consists of five LVDS pairs, four data and one clock. The solution provides four
independent, source-synchronous channels, and on each channel a cycle of parallel clock includes seven bits of
serialized data. Four channels translate to 28 bits parallel data. It is recommended that the four independent channel
pin outs and clock are kept on the same I/O bank. However, different banks can be assigned to pin-outs provided the
clocking requirements are met.
The LVDS 7:1 TX and Rx chain implements:
4
•
LVDS 7:1 TX chain implements double data rate registers to transmit data on both the rising and falling
edges of the clock. The transmitter multiplies the parallel clock by 3.5 and uses it to transmit seven serial
bits of data in one parallel clock cycle.
•
LVDS 7:1 Rx chain implements double data rate registers to capture data on both the rising and falling edge
of the clock. Rx chain captures the incoming parallel clock and multiplies it by 3.5 in order to capture the
input serial data received on both the edges.
UG0645: Low Voltage Differential Signaling User Guide
Hardware Implementation
Design Description
Figure 2 shows implementation of 7:1 LVDS receiver and transmitter diagram with inputs and output signals of LVDS.
Figure 2 · Implementation Diagram of 7:1 LVDS Receiver and Transmitter
This section describes the implementation details of LVDS 7:1 TX and RX paths. Each LVDS 7:1 receiver module
receives LVDS data and an LVDS clock. Both data and clock enter the field programmable gate array (FPGA) device
UG0645: Low Voltage Differential Signaling User Guide
5
Inputs and Outputs
through high-speed LVDS buffers. The LVDS data is fed to the DDR_IN block while the source synchronous LVDS
clock is passed to the Fabric clock conditioning circuitry CCC. The Fabric CCC block generates serial_clk, which is
3.5 times the input received by clock RX_CLK_IN.
The output of the LVDS data buffer is passed to the DDR_IN block while, the DDR_IN module generates two streams
of data at the posedge of serial_clk. This data is then fed to the deserializer, which generates 14-bit deserilized data.
The deserializer block deserializes the incoming data and aligns it to the pre-defined word boundary. A training
pattern is sent to the deserializer, the deserializer then aligns the incoming data to the training pattern. Once the data
is aligned to the word boundary, the respective align_serializer signal is enabled and the aligned data is sent to the
RX_SYNC block.. The RX_SYNC module synchronizes the incoming 14-bit data to parallel_clk before transmitting
the 7-bit of parallel data output, as shown in Figure 2 .
The TX_CLK_IN is fed into the Fabric CCC block, which generates two output clocks parallel_clk and serial_clk. The
frequency of parallel_clk is the same as that of TX_CLK_IN while the frequency of serial_clk is 3.5 times of input
clock TX_CLK_IN. The transmitter block receives 7-bits of parallel data and a parallel clock TX_CLK_IN.
The TX SYNC module synchronizes the incoming 7-bit of parallel data with the output clocks and transmits the
synchronized data to the serializer block. The serializer block then serializes the 7-bit of parallel data to 2 bit of serial
data. These 2 bit of serial data are then passed to the DDR_OUT block, which operates at serial_clk. The serialized
data output from the DDR_OUT is then sent out of the device using high-speed LVDS buffers.
Inputs and Outputs
Table 1 and Table 2 show the input and output ports of the 7:1 LVDS block.
Table 1 · Input and Output Ports of 7:1 LVDS Receiver Interface
Signal Name
Direction
Width
Description
Reset_n
input
-
System Reset
Serial_Clk
input
-
System Serial clock
parallel_clk
input
-
Parallel clock
CAM_D3_P
input
-
Serial Input channel D rising
CAM_D3_N
input
-
Serial Input channel D falling
CAM_D2_P
input
-
Serial Input channel C rising
CAM_D2_N
input
-
Serial Input channel C falling
CAM_D1_P
input
-
Serial Input channel B rising
CAM_D1_N
input
-
Serial Input channel B falling
CAM_D0_P
input
-
Serial Input channel A rising
CAM_D0_N
input
-
Serial Input channel A falling
RDATA_A
output
7 bits
Parallel Output data Channel A
RDATA_B
output
7 bits
Parallel Output data Channel B
RDATA_C
output
7 bits
Parallel Output data Channel C
RDATA_D
output
7 bits
Parallel Output data Channel D
Align_serializer_a
output
-
Channel A Rx alignment signal to the
training pattern
Align_serializer_b
output
-
Channel B Rx alignment signal to the
training pattern
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UG0645: Low Voltage Differential Signaling User Guide
Design Description
Align_serializer_c
output
-
Channel C Rx alignment signal to the
training pattern
Align_serializer_d
output
-
Channel D Rx alignment signal to the
training pattern
Training pattern
input
-
Pattern used to align Rx to Tx.
CAM_CLKOUT_N
input
-
Clock from fabric
CAM_CLKOUT_P
input
-
Clock from fabric
Rclk_o
input
-
LVDS Receiver Clock output
Table 2 · Input and Output Ports of 7:1 LVDS Transmitter Interface
Signal Name
Direction
Width
Description
RESET
input
-
System Reset
serial_clock
input
-
System Serial clock
parallel_clk
Input
-
Parallel Clock
WDATA_A
Input
7 bits
parallel data channel A
WDATA_B
Input
7bits
Parallel data channel B
WDATA_C
Input
7 bits
Parallel data channel C
WDATA_D
Input
7 bits
Parallel data channel D
PADP_TX_0
output
-
Serial channel A rising data
PADN_TX_0
output
-
Serial channel A falling data
PADP_TX_1
output
-
Serial channel B rising data
PADN_TX_1
output
-
Serial channel B falling data
PADP_TX_2
output
-
Serial channel C rising data
PADN_TX_2
output
-
Serial channel C falling data
PADP_TX_3
output
-
Serial channel D rising data
PADN_TX_3
output
-
Serial channel D falling data
PADN_CLK_OUT
output
-
Output differential negative TX clock
PADP_CLK_OUT
output
-
Output differential positive TX clock
UG0645: Low Voltage Differential Signaling User Guide
7
Timing Diagrams
Timing Diagrams
Figure 3 and Figure 4 show the timing diagrams of 7:1 LVDS.
Figure 3 · Timing Diagram for LVDS 7:1 Receiver
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UG0645: Low Voltage Differential Signaling User Guide
Design Description
Figure 4 · Timing Diagram for LVDS 7:1 Transmitter
Performance Statistics
LVDS 7:1 design is validated on M2S150 Advanced Development Kit. The LVDS7:1 validation includes 5 LVDS pairs
(channels) including 4 data channels and 1 clock channel. It is tested for a maximum frequency of 108 MHz parallel
clock and 378 MHz of serial clock (3.5 x of parallel clock) which can transfer up to 750 Mbits/s of data per LVDS pair.
UG0645: Low Voltage Differential Signaling User Guide
9
Resource Utilizations
Resource Utilizations
®
Table 4 shows the resource utilization of the LVDS 7:1 block implemented in the SmartFusion 2 system-on-chip
(SoC) FPGA device M2S050T-FBGA896 package.
Table 3 · Resource Utilization of LVDS 7:1 Receiver
Resource
Usage
DFFs
990
4-Input LUTs
590
MACC
0
RAM1Kx18
0
RAM64x18
4
Table 4 · Resource Utilization of LVDS 7:1 Transmitter
Resource
Usage
DFFs
190
4-Input LUTs
80
MACC
0
RAM1Kx18
0
RAM64x18
0
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UG0645: Low Voltage Differential Signaling User Guide
List of Changes
The following table shows important changes made in this document for each revision.
Date and Revision
Change
Page
Revision 2
(February 2016)
Updated the SAR (76159).
NA
Revision 1
(August 2015)
Initial release.
N/A
UG0645: Low Voltage Differential Signaling User Guide
11
Product Support
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Fax, from anywhere in the world 408.643.6913
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Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers who can
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For Microsemi SoC Products Support, visit,
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UG0693: Low Voltage Differential Signaling 7:1 User Guide
12
ITAR Technical Support
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UG0645: Low Voltage Differential Signaling User Guide
13
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