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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 11, NOVEMBER 2010
Limits and Opportunities for Distributed Inductors in
High-Current, High-Frequency Applications
Christina Collins and Maeve Duffy, Senior Member, IEEE
Abstract—Issues relating to the design of distributed (parallel)
inductors for high-current, high-frequency applications, such as
voltage regulator modules (VRM’s) are investigated through component design and analysis based on standard planar ferrite cores.
Distributed solutions are shown to provide a smaller footprint and
volume over equivalent lumped inductors through improved utilization of winding and core materials. The potential for size reduction provided by increased operating frequency is shown to
be limited by the loss characteristics of available core materials
and the size of conductors needed to handle large currents. The
opportunity for improving light-load efficiency of VRM’s through
switching out of parallel inductors is introduced, and the potential
level of improvement in loss provided under light-load conditions
is illustrated.
Index Terms—High-frequency issues, planar inductor design,
voltage regulator module (VRM).
I. INTRODUCTION
NDUCTORS are central to the development of high-current,
low-voltage power supplies, such as voltage regulator modules (VRMs), where they are needed to limit ripple current levels under steady-state conditions. However, the need for highcurrent slew rates has pushed operating frequencies to levels,
where traditional design techniques do not accurately account
for all contributing effects, and consequently, the size reduction
expected at high frequency is not necessarily realized [1]. Commercially, bead inductors seem to provide the most effective
solutions, e.g., [2], [3], although there are little or no details of
core materials and winding structures available, and therefore,
it is difficult to identify limiting factors for future requirements.
Research in high-current, high-frequency inductors is focused
more on coupled inductors [4]–[6] and integration in silicon,
where the main issue is to develop manufacturing technologies
for depositing conductor and magnetic layers that are capable
of handling the high-current levels [7]–[9]. In this paper, the design of planar inductors for VRMs is investigated to determine
the limits imposed by core materials, winding technologies,
and high-frequency operation, and the potential for overcoming
I
Manuscript received October 14, 2009; revised February 17, 2010; accepted
March 12, 2010. Date of current version October 29, 2010. This work was
supported by the National University of Ireland, Galway, Ireland through a
Postgraduate Scholarship. Recommended for publication by Associate Editor
B. Ferreira.
The authors are with the Power Electronics Research Centre, Electrical and
Electronic Engineering, National University of Ireland, Galway, Ireland (e-mail:
collins.christina@gmail.com; maeve.duffy@nuigalway.ie).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2010.2047117
these limits by replacing lumped inductors with equivalent parallel inductors is demonstrated. Results are based on standard
planar cores for which information on magnetic materials and
winding technologies is readily available, and the same procedure may be applied to other inductor technologies.
Recent developments in high-frequency, high-current inductor design, include coupled inductors, air-core devices, and
silicon-integrated technologies. Coupled inductors provide a
means for enhancing the inductance per phase in a multiphase
buck circuit under steady-state conditions, while providing a
much reduced inductance under transient conditions, so that
high-current slew rates are supported [4]–[6]. The size of coupled solutions is also smaller than equivalent discrete inductors. However, circuit design is more complicated than with
uncoupled inductors, and this becomes an issue with every new
VRM specification. Air-core inductors are being investigated
for operation in the gigahertz frequency range, where inductance values are reduced to levels, where a core is no longer
necessary [10], [11]. However, semiconductors, capacitors, and
control techniques have not yet been developed to support these
frequencies for VRM current levels. The same is true of magnetics on silicon, where there are significant efforts directed
at integrating inductors alongside switches and control functions, so that parasitic impedances of interconnect paths can
be minimized [7]–[9]. Currently, technologies are available to
support lower current point-of-load applications, although work
is ongoing to increase the current carrying capacity of silicon
tracking.
The proposal to replace each phase inductor of a multiphase buck circuit with several parallel inductors in this paper addresses increasing magnetic component sizes, which are
needed to handle high-frequency effects by providing more effective usage of magnetic core and winding areas. Distribution
of magnetic components for power electronic applications has
been investigated previously, whereby component attachment
to printed circuit boards (PCBs) is facilitated by distributing
the weight of magnetic components and the overall core volume is reduced by over 50% [12]. The application of parallel
inductors in VRMs was introduced previously by Collins and
Duffy, but the limits to distribution and high-frequency operation were not investigated [13].In this paper, the extent to which
the overall size of parallel inductors in one phase of a VRM10.1
can be reduced over that of an equivalent lumped inductor is
illustrated. Designs are based on standard planar cores and PCB
windings, which are intended for integration within the VRM
board. Measurement results are presented to verify the levels of
size reduction achieved for current levels up to 30 A per phase.
The possibility of improving light-load efficiency by switching
0885-8993/$26.00 © 2010 IEEE
COLLINS AND DUFFY: LIMITS AND OPPORTUNITIES FOR DISTRIBUTED INDUCTORS
2711
out parallel inductor paths when current levels reduce is also
introduced.
Planar inductor design procedures are reviewed in Section II,
where particular issues relating to VRM applications and highfrequency operation are highlighted. It is shown that designs
are limited by loss rather than saturation, as is more usual at
100’s kHz. The performance of equivalent parallel inductors is
compared with lumped designs in Section III in terms of inductor
size, losses, and the potential for improving light-load efficiency.
Detailed analysis of designs is also presented to illustrate, which
factors are limiting performance and size reduction, particularly
in progressing toward higher switching frequencies as needed
for future applications. Results are presented for designs based
on standard cores to enable comparison with measurements, and
on partly customized cores to illustrate additional levels of improvement possible. Predictions are verified by measurements
in Section IV, followed by conclusions in Section V.
II. PLANAR INDUCTORS FOR HIGH-CURRENT,
HIGH-FREQUENCY APPLICATIONS
As mentioned, bead inductors provide the most compact solutions in commercial high-current, low-voltage applications,
where the size of a bead inductor needed to handle 30 A per
phase is as small as 6.5 × 6.9 mm2 [3]. However, details of core
materials and winding structures are not widely available, particularly in relation to their performance at high frequency, and
therefore, it is difficult to determine limiting factors for future
VRM requirements. Instead, planar inductors are considered
as an intermediate solution between discrete components and
substrate integrated devices in this paper, where planar windings are reputed for their good thermal properties and reduced
eddy-current effects. Furthermore, loss data for standard core
materials and shapes are widely available, and analytic and
finite-element analysis (FEA) techniques have been established
to account for the contribution of high-frequency effects, both
in the core and winding regions. Designs are based on VRM
inductor specifications because these impose the most challenging requirements of high-current and high-frequency inductors.
Lumped inductor designs are presented in this section for comparison with parallel designs in Section III. In order to illustrate
issues for future specifications, designs are presented for operating frequencies from 500 kHz, around which many VRM
products currently operate, to 3 MHz, which is high for ferritebased VRM inductors.
A. VRM Inductor Specifications
The industry standard solution for VRMs is a multiphase
interleaved buck converter, with the most common number
of phases used to achieve VRM10 specifications being four
[14], [15]. The basic function of the inductors is to limit ripple
current ∆I in the individual circuit phases, thereby specifying a
phase inductance L, given by
L=
D(Vin − Vo )
f ∆I
(1)
Fig. 1. VRM inductor waveforms. (a) Voltage and current and (b) currentfrequency spectrum.
where D is the duty ratio of output voltage Vo over input voltage
Vin and f is the phase switching frequency. The total output current is provided by adding the currents from each of the circuit
phases, with phase interleaving applied to reduce the current
ripple level handled by output capacitors. In this way, the interleaved buck may be seen to distribute the inductor of a simple
buck converter. However, the optimum number of phases for
providing maximum cancellation of ripple current is defined in
terms of the ratio of input:output voltage levels of the VRM [16],
and not in terms of the minimum size of inductor components
required.
Schematic voltage and current waveforms are shown for a
typical phase inductor in Fig. 1(a), where values are scaled for
VRM10.1 specifications at a nominal input voltage Vin = 12 V,
output voltage Vo = 1.3 V, and output current Io = 120 A
(30 A per phase) [17]. The corresponding frequency spectrum
for a ripple current level of ∆I = 15 A (50% ripple ratio) is
given in Fig. 1(b), from which it is calculated that harmonics
up to the third component contribute more than 5% to the rms
current. Clearly, the inductor needs to operate efficiently at frequencies up to at least three times the fundamental frequency in
this case, and inductor loss models must account for the contributions of current and voltage harmonics.
The push to high-frequency operation of VRMs is motivated
not so much by a need for reduced component size, but more
to support higher current slew rates and increasing transient
current repetition rates of high-end computing loads. In terms
of the phase inductors, the limit in current slew rate may be
seen in terms of a transient response recovery time Ttrr for the
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 11, NOVEMBER 2010
TABLE I
VRM10.1 INDUCTOR SPECIFICATIONS
while Vin and Vo are the dc input and output voltage levels of the
converter, respectively. As in conventional design, maximum
values of ∆B and J are limited by loss considerations, and
these, in turn, impose restrictions on minimum values of Ac and
Aw , so that a minimum core area product Ap , can be defined as
follows:
Ap ≥
inductor, which can be estimated as follows:
Ttrr =
LIpk
Vo
(2)
for worst case conditions of the load slewing from its maximum peak current, Ipk to 0 A with the maximum inductor
discharge voltage being limited to Vo . For example, an increase
in operating frequency by a factor of six enables a decrease
in L, and therefore, Ttrr by the same factor. In addition, highfrequency operation alleviates output capacitor requirements, so
that smaller components are needed at the load end. Given that
VRM output voltage levels are decreasing and current levels are
increasing, it is clear that high-frequency operation is critical
for enabling faster computing speeds.
With such trends of increasing frequencies and decreasing
voltage levels, the relative contributions of high-frequency effects and harmonic components will become more significant
for VRM inductors. In order to illustrate the range of issues encountered, inductors designed to meet VRM10.1 specifications
with a current ripple ratio of 0.5 are investigated at frequencies
of 500 kHz, 1 MHz, and 3 MHz, as given in Table I. Note that the
value of L decreases with increasing frequency, thereby suggesting that the inductor size can be reduced. However, it is found
that due to the combined effects of poor core loss properties
and the need for high-current conductors, the size of components designed for operation at 3 MHz is at best equal to those
designed for 500 kHz.
B. Planar Inductor Design Procedure
In effect, the area-product approach is applied for planar
magnetic design, where minimum core and window areas are
calculated so as to satisfy loss constraints, and the resulting
minimum loss design is determined for given standard core
geometries [18], [19]. Loss models are developed to include
high-frequency and nonsinusoidal waveform effects, and the
resulting issues in implementing the area-product approach are
highlighted. Designs are based on standard planar ER cores from
Ferroxcube [20], where the ER shape is chosen over EE because
it has a shorter mean turn length, and therefore, provides lower
coil resistance for the same core area.
In the case of VRM inductors, voltage and current equations
for the area-product approach can be written as follows:
N Ac ∆B
ku Aw J
,
IL =
(3)
DT
N
respectively, where N is the number of inductor turns, Ac is the
core area, Aw is the window area, ku is copper utilization level,
∆B is the flux density swing, and J is current density in the
windings. Current IL is the rms current flowing in the inductor,
Vin − Vo =
D(Vin − Vo )IL
.
f ku ∆Bm Jm
(4)
However, due to a dependence of ku and Jm on PCB layer
buildup, and of ∆Bm on planar core size, it is difficult to predefine suitable values for these parameters in the case of planar
inductors, and therefore, direct application of the area-product
approach is not so simple. Calculation of Jm and Bm is further
complicated by contributions of high-frequency effects when
compared with sinusoidal conditions. Lastly, due to a need to
apply a ferrite grade with the most suitable loss properties at a
particular frequency, it is found that the implication of (4) that
higher switching frequency results in lower Ap is not necessarily
true.
The proposed approach involves determining minimum core
and window areas separately rather than the minimum combined
area product. The first step is to determine the minimum core
window width ww m in , needed to handle the applied current
level IL , in one turn within a given PCB build
ww
m in
>
ACu m in
+ 2ccw
NPCB tCu
(5)
where NPCB is the number of PCB layers, tCu is the copper
thickness per layer, ccw is the clearance distance between the
PCB copper and core, and ACu m in is the minimum PCB copper
area needed to handle the applied current according to the IPC
standard for PCBs [21]. As a first approximation, the effect
of ac winding effects can be neglected, and ACu m in can be
calculated in terms of the dc current as Idc /Jm with Jm chosen
at a level comparable to that given for applied current levels.
As a worst case, Jm was chosen, as 30 A/mm2 in this paper,
which is the lowest current density value presented in [21] for
a temperature rise ∆T of 45 ◦ C in internal PCB conductors.
NPCB was chosen as six, with tCu as 105 µm and ws at 0.4 mm;
this PCB buildup is compatible with Intel recommendations for
a minimum of four layers with 2 oz copper for VRM10.1 boards
[17], so that the inductors are designed for integration within a
VRM board. Modeling of ac winding effects is described later
after the complete winding, core, and gap structure is defined.
For the smallest core satisfying (5), the next step is to determine minimum and maximum numbers of turns that can be
accommodated: Nm in and Nm ax , respectively. Nm ax is found
simply as the number of turns with cross-sectional area ACu m in
that can fit within the given window area/PCB build
Nm ax =
(ww − 2ccw )NPCB tCu
ww − 2ccw
=
ACu m in
ww m in − 2ccw
(6)
where ww is the window width of the given core. Calculation of
Nm in is more complicated, as it involves first determining the
maximum flux density swing ∆Bm , which can be handled by a
given core for a specified temperature rise ∆T . For planar ferrite
COLLINS AND DUFFY: LIMITS AND OPPORTUNITIES FOR DISTRIBUTED INDUCTORS
2713
cores, thermal performance is given as an empirically derived
relationship between core loss density Pv and ∆T as follows:
12∆T
Pv = √
Ve
(7)
where Ve is the effective volume of the given planar core [22],
i.e., the capability of planar cores to handle losses is dependent
on a particular core size. The relationship between loss and flux
density is then given in the form of Steinmetz parameters K,
α, and β, which are applied to predict power loss density under
sinusoidal conditions in the renowned Steinmetz equation
Pv = Kf α B β
(8)
where B is the amplitude of sinusoidal flux density in this case.
Following the development of switching-mode power supplies,
it soon became apparent that core losses incurred during square
wave/pulse excitation can be much higher than under sinusoidal
excitation for the same level of flux swing. Different models
emerged to account for the dependence of loss on the rate of
change of flux density dB/dt, rather than simply on its level, and
the most accurate model for MnZn ferrites was found to be the
improved general Steinmetz equation (iGSE) method [23], [24]
as given by
Ki
Pv =
T
with Ki =
T
0
dB α
β −α
dt,
dt |∆B|
(2π)α −1
2π
0
K
|cos θ|α |sin θ|β −α dθ
Fig. 2. (a) Maximum flux density versus core volume V e for planar cores with
D = 0.108, ∆T = 50 ◦ C, (b) Winding loss vs. load current predicted using
different models.
(9)
for piecewise linear flux density waveforms, having a flux swing
∆B and a period T = 1/f . For the case of triangular flux
waveforms applied in VRM inductors, (9) may be rewritten as
follows:
Pv = Ki f ∆B β
1
1
+
.
(DT )α −1
[(1 − D)T ]α −1
(10)
It has been shown that nonsinusoidal flux waveforms contribute to significantly increasing core loss over pure sinusoidal
waveforms and as given by (10), this contribution increases with
decreasing duty ratio. By equating (7) and (10), ∆Bm is calculated, and Nm in is then found from the voltage equation of
(3). Manufacturer’s values of K, α, and β given at the fundamental switching frequency are applied in this case. For illustration, results of ∆Bm are plotted versus the range of standard
ER core sizes in Fig. 2(a) for the three operating frequencies
considered.
If at this stage it is found that Nm in > Nm ax , this indicates
that the core area is not large enough to limit applied flux levels, and therefore, the next largest core needs to be considered.
Otherwise, for each possible value of N , the turns are divided
equally over the number of PCB layers using the maximum possible track width and the gap g, needed to produce the required
inductance value is then calculated as follows:
2MTL
N 2 µ0 Ac
g
g∼
F,
F ∼
,
=
= 1 + √ ln
L
g
Ac
L =
µ0 N 2 Ac
F
g + (lc − g)/µr
(11)
where fringing effects are included through a fringing factor F ,
as given in [18]; MTL is the mean turn length of the core and L
includes for the contribution of the reluctance of the core path
with length lc . Clearly, some iteration of the equations for g, F ,
and L is needed until the values of L and L coincide.
The resulting winding, core, and gap structures are then simulated using FEA [25] in order to verify that ac winding effects
do not cause excessive winding loss. For this purpose, an effective dc current Ieff is calculated in terms of total winding losses
as follows:
n
2
2
Ieff Rdc = Idc Rdc +
Ii2 Raci
(12)
i=1
where Rdc is dc resistance and Raci is the ac resistance at the
“ith” harmonic frequency calculated using FEA; ACu or Jeff =
Ieff /ACu is then checked to ensure that the chosen copper area
is sufficient to handle Ieff rather than Idc as previously assumed.
Components of Raci are found to be largely dependent on the
winding configuration and its proximity to a gap. For simplicity
of construction, the gap is assumed to be distributed across
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 11, NOVEMBER 2010
TABLE II
STRUCTURE OF SINGLE INDUCTOR DESIGNS (SMALLEST DESIGNS WITH
LOWEST LOSSES)
all three legs of an ER core and the 3-D nature of the core is
accounted by defining equivalent pot-core structures with equal
core length and cross-sectional area around the flux path, as
described in [26]. 1-D analytic models such as presented in [27]
and [28], are not accurate because the gap directs fringing fields
in a direction perpendicular rather than parallel to the PCB layer.
Results in Fig. 2(b) demonstrate the magnitude of ac effects
for a 155 nH, 500 kHz inductor design based on the planar ER18
core with one turn. It is seen that with all harmonics included
(Pdc + Pac tot ), eddy currents contribute to increasing winding
losses by up to 31% at full load in this case, with the impact
being more significant at lower current levels. If it is found that
the contribution of ac effects cause excessive winding losses
for the given inductor structure, the number of winding turns
needs to be reduced or if N = 1, the next largest core needs to
be chosen and a new design iteration started. If winding losses
are acceptable, the final step is to ensure that the core is not
saturated during operation
Bpk
µ0 N Ipk
=
≤ Bsat
g + lc /µr
(13)
although it will be shown that loss limitations are found to be
more restrictive than saturation in all designs considered. Finally, the overall temperature rise may be estimated by applying
half the total loss (winding plus core loss) divided by core volume in (7).
C. Analysis of VRM Inductor Designs
A comparison of designs produced using the aforementioned
procedure for the VRM specifications of Table I is provided in
Table II.
Clearly, the size of the single inductor remains the same over
all frequencies with the same core wound with a single turn
being applied in each case, i.e., the theoretical size reduction
predicted for increasing frequency is not achieved. This is explained mostly by core losses, where it is found that while the
window area of smaller cores is large enough to handle one turn,
corresponding flux levels cannot be handled, and therefore, the
next largest core needs to be chosen. As a result, the window area
is much larger than necessary. This illustrates one of the limits
of standard commercial core sizes, i.e., the ratio of core:window
area is not large enough for PCB integrated VRM inductors. As
a result, the predicted temperature rise is well below the specified value of 50 ◦ C in all cases, thereby indicating that smaller
solutions may be possible. It should be noted that the gap in
the 3 MHz design is very large, because the inductance value
needed is six times smaller than at 500 kHz. Given that the
window height is 3.2 mm and that the permeability of the core
Fig. 3. Comparison of VRM inductor (a) losses, (b) core, copper, and saturation utilization levels at 0.5, 1, and 3 MHz.
material applied is very low (80), it can be concluded that the
core is not very effective in this case, and further that 3 MHz is
close to the limit in operating frequency for ferrite-based planar
inductors for VRMs.
In order to investigate other limiting factors in the inductor
designs in more detail, a breakdown of predicted full-load losses
is presented in Fig. 3(a). Firstly, it is seen that dc losses (Pdc )
are constant for all designs because the same winding structure is used. Comparing designs with increasing frequency, it is
seen that while the operating flux density level ∆B decreases
in direct proportion to frequency according to (3), there is no
corresponding level of decrease in core loss (Pcore ), indeed core
loss increases in 3 MHz designs and this is explained by different loss characteristics of the core materials applied. This effect
can also be seen in Fig. 2(a). The fact that loss density for the
3 MHz design is closest to ∆Bm in Fig. 3(b) suggests that a
larger core area may be needed in future designs, where a lower
duty ratio will cause further increased high-frequency effects.
The increase in ac winding loss contributions (Pac ) is explained
by higher operating frequency and a larger gap as the inductance
value decreases. Clearly, these trends demonstrate the need for
FEA modeling of conductor losses in gapped inductor structures
and the difficulty in predefining Jm for implementation of the
area-product approach, as discussed earlier.
While winding loss accounts for the majority of the inductor
loss, it is confirmed that the most significant limit to reducing
the size of all components is core loss. This is shown more
clearly in Fig. 3(b), in terms of a so-called core utilization level,
COLLINS AND DUFFY: LIMITS AND OPPORTUNITIES FOR DISTRIBUTED INDUCTORS
which is defined as the operating flux density level/maximum
allowed flux density (∆B/∆Bm ) for a 50 ◦ C temperature rise,
and a copper utilization level, defined as the effective current
density/maximum current density allowed (Jeff /Jm ) in the copper tracks for the same temperature rise. In all cases, the core
utilization level is higher than that of copper. However, both
core and copper utilization levels are relatively low, which is in
accordance with the modest values of temperature rise given in
Table II. Values of Bpk /Bsat (defined as saturation utilization)
are also included to illustrate how far from saturation all designs
are, and therefore to emphasize the loss limitation. Interestingly,
the effect of saturation becomes less significant with increasing
frequency, and this is explained by larger gaps required to produce smaller inductance values at high frequency.
The proposal for replacing a lumped planar inductor design
with several equivalent parallel inductors was first prompted by
the possibility of achieving a higher utilization level of copper
areas, where several smaller parallel paths provide a more evenly
distributed impedance to high VRM current levels at high frequency. At the same time, the gap required to produce a higher
inductance value in each parallel inductor is much smaller than
in an equivalent lumped inductor, so that fringing effects should
be reduced. On investigation of this approach, it was found
that for a given temperature rise, the use of smaller cores allows the application of higher levels of magnetic flux density
∆B and of current density J in the PCB windings, thereby enabling size reduction according to (4). First, this is illustrated
in Fig. 2(a), where results of maximum levels of magnetic flux
swing allowed are compared for the three operating frequencies
investigated for different commercial core sizes, and second in
Fig. 4(a), where the plot of maximum current density allowed
versus PCB conductor area as deduced from the IPC standard
is given for a temperature rise of 45 ◦ C [21].
Clearly, the level of magnetic flux density allowed for a given
temperature rise increases with decreasing core size, where improved thermal performance of smaller cores allows more effective use of the core materials. Results in Fig. 4(b) confirm
that the improved thermal performance is provided by an increased ratio of surface area:enclosed volume for smaller cores,
as has been described previously for high-frequency magnetic
components [29]. Similarly, the increase in current handling
per unit area with decreasing conductor size is explained by
an increased ratio of conductor area:volume. Therefore, this
suggests that the combined area product of several parallel inductors should be smaller than that of a single inductor defined
to handle the same voltage and current waveforms, so long as the
ratio of surface area:volume for the inductor core and windings
increases with decreasing core size. The translation of reduced
area product into reduced inductor footprint and volume then
depends on the particular core geometry applied. The extent to
which this holds true for VRM inductors using planar ER cores
is illustrated in Section III.
III. PARALLEL INDUCTOR DESIGNS
The performance of equivalent parallel inductors is compared
to the lumped designs listed in Table II in this section. Designs
2715
Fig. 4. (a) Maximum current density versus PCB copper area ∆T = 45 ◦ C.
(b) Surface area:enclosed volume of standard planar cores (legend refers to
surface area).
based on standard commercial cores are investigated first, so
that results can be verified by measurement in Section IV; the
design procedure described in Section II is applied in this case.
Custom designs are then presented to illustrate the factors that
contribute to limiting the level of distribution of the inductors
that can be applied with advantage.
A. Standard Commercial Core Designs
Inductor specifications and details of inductor materials and
constructions are given in Table III for 1, 2, and 3 parallel inductors, which are designed to provide the same functionality,
as the inductors listed in Table II. As earlier, designs are based
on Ferroxcube’s range of planar ER cores. Due to the impractically large gap required for 3 MHz designs, only 500 kHz and
1 MHz solutions are considered. Inductance values increase
with increasing numbers of parallel inductors, as ripple current
levels are reduced in each individual component.
As found in Section II, the same core size generally applies for
a given inductor solution (single or parallel) at different frequencies, although there are differences in gap sizes and numbers of
turns to provide different inductance values. In particular, there
is no reduction in inductor size observed for increased operating frequency. However, when comparing single and parallel
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 11, NOVEMBER 2010
TABLE III
COMPARISON OF DISTRIBUTED INDUCTOR STRUCTURES
Fig. 6.
Predictions of (a) inductor losses and (b) utilization levels at full load.
having an area of Aw
IL
ku Aw Jm
.
≤
np
N
Fig. 5. Comparison of (a) area product and footprint and (b) volume and
height for single and parallel inductor designs.
inductor solutions at the same frequency, it is found that the
overall size of components decreases with increasing numbers
of parallel inductors. This is shown in terms of the overall area
product, footprint, volume, and height of the single versus parallel designs in Fig. 5, where the same results apply for both
500 kHz and 1 MHz.
In this case, the overall area product for np parallel inductors
is given by
Ap = np Ac Aw
(14)
where the same core area Ac , as given by (3) is needed to handle
the applied volt–second in each parallel inductor, and the total
rms current IL , is now divided among np core windows, each
(15)
As with conventional inductor design, the reduced area product in Fig. 5(a) can be interpreted as improved utilization of
winding and core regions, and this is shown to be true in Fig. 6
next.
With a larger inductor footprint for two parallel versus one
inductor shown in Fig. 5(b), it is clear that the improvement
in area product does not always translate into real component
size reduction. This may again be explained by the limitation
in range of standard core sizes available. Nonetheless, with
increased distribution to three parallel components, significant
improvement in inductor area is achieved. This is probably the
most significant size parameter for PCB integrated devices, as
a reduction in inductor area translates into reduced board area.
Corresponding results of inductor volume in Fig. 5(c) show the
same trend. The extent to which distribution can be applied to
provide size reduction in this way is illustrated by comparing
losses and utilization levels for the different designs.
Clearly, inductor losses increase with increasing levels of
distribution, reflecting the general increased utilization levels
of winding and core regions. Utilization levels of both copper
and core regions are approximately equal for the three parallel
designs at both frequencies, and there is not much scope to increase these further. When combined with the increased levels of
magnetic flux density and current density allowed in the smaller
cores, these trends explain the overall reduction in inductor size
achieved. Slightly lower losses are predicted for operation at
1 MHz than 500 kHz, due to differences in core materials.
COLLINS AND DUFFY: LIMITS AND OPPORTUNITIES FOR DISTRIBUTED INDUCTORS
Fig. 7.
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ER core cross section.
TABLE IV
COMPARISON OF CUSTOMIZED ER CORE DESIGNS
Fig. 8. Comparison of area product and inductor footprint for distributed
custom core designs.
In terms of identifying limiting factors to increasing levels
of distribution, it is clear that losses limit the overall performance with in general core losses imposing the first limitation,
followed by winding losses, and then, saturation. However, due
to differences in numbers of inductor turns, the trends are not
consistent, and therefore, custom one-turn inductor designs are
presented in Section III-B to confirm them.
B. Custom Core Designs
In order to facilitate easier comparison of the distributed
designs, cores used in the inductor designs of Table III were
adapted slightly so as to accommodate single turn designs. Customization in this way may be seen as addressing the low ratio of
core:window area of standard commercial cores, and as improving the balance between core and winding utilization levels. In
the case of each design with more than one turn, customization
involved increasing the core area (ri and do , as shown in Fig. 7),
so that the flux density level given by (3) is reduced to that
allowed according to (7–10) with one inductor turn. The width
of the core window ww was reduced, so that the overall core
width remained the same, and therefore, its thermal properties
could be assumed unchanged. A temperature rise of 50 ◦ C was
assumed as earlier. Details of the resulting designs are given in
Table IV.
In reviewing the design of two parallel inductors at 500 kHz,
it was found that after increasing the core area so as to handle
required core loss levels, the resulting window area was large
enough to handle 30 A current, and therefore, it was possible
to reduce the size of the single inductor solution by using an
ER14.5 core instead of ER18. Similarly, a customized ER9.5
core was found to be large enough to handle core and winding loss levels for the two parallel inductors. As ER9.5 is the
smallest standard core available, no further level of distribution
was possible through customization in this way. Inductor sizes
are compared in terms of overall area product and inductor footprint in Fig. 8, where it is seen that a smaller solution is provided
Fig. 9. Comparison of (a) full-load loss distribution and (b) utilization levels
in custom one-turn designs.
again by distribution. Corresponding results of inductor losses
and utilization levels are presented in Fig. 9.
While customization of the cores provides an overall size reduction over standard commercial cores, losses are not increased
significantly over those presented in Fig. 6 as might be expected.
DC and core loss components increase with increasing levels of
distribution, while as expected ac winding losses decrease. As
these designs were customized to allow the maximum power
loss density within the core, losses are limited firstly by core
losses, then by winding losses and finally by saturation, thereby
confirming the general trends observed in standard commercial
core designs.
These trends have been observed for two different sets of
VRM inductor designs based on planar ER cores, where the
reduced area product in both cases is explained by an increased
ratio of surface area:volume, and the extent to which reduced
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 11, NOVEMBER 2010
area product translates into reduced inductor footprint or volume depends largely on the range of core sizes available. These
in turn are limited by manufacturing and cost constraints, which
will apply for any magnetic technology. Nonetheless, it is reasonable to assume that a reduction in area product generally corresponds to reduced component size, and therefore, it would be
expected that size reduction through paralleling is achieved with
other magnetic technologies for which thermal performance improves with decreasing size.
In terms of cost, it is likely that the advantages of size reduction are achieved at the expense of increased costs when
using planar magnetic technology. This relates to the need for
attaching several cores instead of just one, and to the fact that
the cost per core does not necessarily decrease with decreasing size. Both these issues may be overcome by designing core
pieces with multiple windows, so that only one pair of core
halves needs to be produced and attached for a parallel inductor solution. Winding and soldering costs for the inductors will
be eliminated as the windings are integrated within the VRM
board, while the reduction in inductor footprint area and volume
will also act so as to alleviate cost.
C. Potential for Improved Light-Load Efficiency of VRM’s
All results of losses presented up to this point are for fullload conditions of a VRM10.1. However, full-load conditions
are not continuous or applicable for long periods of time in the
case of VRM’s, which often spend more time in sleep or other
power-saving modes than at full load. With parallel inductors,
as each inductor is rated to carry IL /n (for n parallel inductors),
there is no need for all inductors to be connected when the load
current is lower than the full-rated value. For example, once
the current in a VRM with two parallel inductors per phase
reduces to less than half of full load, it is only necessary for one
of these inductors to be connected. In this way, components of
core and ac winding loss associated with the inductor that can be
switched out are eliminated. Results of inductor loss versus load
current are presented in Fig. 10 to illustrate how overall losses
in the standard and customized inductor designs are improved
by switching out of parallel inductors according to the current
level as described.
In both cases, it is found that by switching out one of two
parallel inductors for current levels below 15 A, for example, that
both core and ac winding losses are halved; this is seen in the step
reduction in total losses at 15 A. DC winding losses are larger
than without switching, but as their contribution decreases with
the square of load current, they become much less significant.
Due to a higher contribution of dc winding losses in two parallel
inductors, total losses remain higher than the equivalent single
inductor. However, in the case of three parallel inductors, losses
after two of the inductors are switched out (for currents lower
than 10 A) are lower than for the equivalent single inductor
design. The same is true of the two parallel inductors in custom
core designs for currents lower than 15 A, where dc winding
losses are proportionately lower than for standard cores.
Clearly, improved inductor losses will impact directly on the
efficiency of the VRM, and therefore, switching out of paral-
Fig. 10. Comparison of distributed inductor losses versus load current (1 MHz
designs) (a) standard cores and (b) custom cores.
lel inductors can be applied to enhance light-load efficiency. It
should be noted that in addition to the improvement in inductor
losses, switching out of inductors results in improved losses in
other circuit components and particularly in power semiconductor switches. This is explained by reduced ac current levels produced by larger inductance values, and the possibility of eliminating switching and drive losses in semiconductor switches
connected to the inductors that are switched out. Therefore, in
addition to the level of loss reduction illustrated in Fig. 10,
switching out of parallel inductors under light-load conditions
has the potential for reducing semiconductor losses, which are
generally the most significant loss contributors in VRMs [30].
Work is ongoing to illustrate the level of improvement possible.
IV. MEASUREMENTS
Details of the test inductors are as given in Table III as much as
possible; PCB’s were designed and produced using commercial
PCB manufacturing processes and the cores were constructed
using sheets of Mylar for gap spacers. Aluminium tape was
used to hold the cores together because it was not possible to fit
the manufacturer’s clamps onto the PCB integrated windings.
FEA simulation confirmed that fringing effects introduced by
the aluminium tape are less significant than those caused by the
thicker stainless steel clamps. Measured results of resistance
and inductance are presented in Table V and photographs of
the prototype inductor PCBs are given in Fig. 11(a). The footprint occupied by the different inductor designs is marked for
illustration; the area of contact pads defined for testing is not
included, as these would not be necessary in PCB integrated
devices. Elimination of contact pads would also allow the par-
COLLINS AND DUFFY: LIMITS AND OPPORTUNITIES FOR DISTRIBUTED INDUCTORS
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TABLE V
MEASURED RESISTANCE AND INDUCTANCE OF PROTOTYPE INDUCTORS
Fig. 12. Circuit waveforms for different inductor designs. (a) Two in parallel.
(b) Three in parallel.
Fig. 11. Photograph of (a) prototype inductor PCB windings and (b) two-phase
test buck circuit.
allel inductors to be placed closer together. Values of resistance and inductance at 1 MHz were measured using an Agilent
4395 A network/spectrum/impedance analyzer, while dc resistance was deduced from voltage and current measurements on
the inductor windings when supplied from a dc power supply.
Measured inductance values are within 11% of their specified
values. Differences in predicted and measured dc resistance
values are explained by differences in the copper cross section
produced during PCB manufacture and that designed. These
differences may be addressed by incorporating compensation
for etch-back of copper in future PCB designs.
VRM measurements were performed on a two-phase buck
circuit that is capable of operating at frequencies in the range of
500 kHz–3 MHz, and at output current levels of up to 30 A per
phase. A photograph of the circuit is shown in Fig. 11(b). In this
case, it was configured for operation at 1 MHz, with Vin = 12 V,
Vo = 1 V, and prototype inductors were designed to provide a
ripple current ratio of 0.5 at 30 A full load per phase. In the
case of each inductor design, the required number of inductors
was connected in parallel and measurements of input and output
power to the circuit were taken. MOSFETs were cooled by a
fan, but the inductors were shielded from the path of the fan, as
natural convection was assumed in the thermal models applied.
Due to the relatively low level of loss contributed by inductors
in the circuit, it was difficult to measure power loss of the inductors directly. Instead, inductor temperature rise was recorded
using a thermocouple, which was positioned as closely as possible to the center leg of the cores. Measurements were performed
over a range of current levels from 0 to 30 A in each case. Waveforms of the voltage and current in one of the parallel inductors
are shown for each design in Fig. 12.
Voltage waveforms are approximately the same for each inductor design, with differences in dc and ac current levels corresponding to the number of parallel inductors. For comparison
with trends in predicted losses, results of overall circuit efficiency and temperature rise are plotted, as a function of load
current in Fig. 13.
In Fig. 13(a), it is clear that the difference in circuit efficiency caused by the different inductor realizations is minimal, with each solution providing the same load characteristic.
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 11, NOVEMBER 2010
is enabled by better thermal performance of the distributed inductor solutions and higher core:window areas. Consequently,
the size of a parallel inductor solution was shown to be smaller
than that of an equivalent lumped solution. Limits to the level
to which this method can be applied are identified for the case
of planar ferrite cores with PCB windings. Finally, the potential
for improving the light-load efficiency of VRM circuits is introduced, whereby only the minimum number of parallel inductors
required to handle the given current level are connected, with
the other parallel inductors switched out.
Work is ongoing to demonstrate the level to which lightload efficiency of VRMs can be improved by distribution of
the inductors, where the effects of switching out of inductors
on MOSFET and other circuit component losses will be investigated. Future work will investigate how the method applies
for coupled inductors and other inductor technologies (beads
and silicon integrated inductors), which are being applied in
VRMs. Other high current, variable load applications, which
may benefit will also be considered.
ACKNOWLEDGMENT
The authors would like to thank for the contributions of
Dr. D. O’Sullivan and Dr. R. Foley at University College Cork,
Ireland who designed, built, and provided support on the test
circuit. They also would like to thank Ferroxcube for providing
samples of planar cores.
REFERENCES
Fig. 13. (a) Efficiency and (b) temperature rise versus load current for different
parallel inductor designs.
This is explained by the dominance of switching related losses
in the circuit and will be investigated in more detail in future
publications. Differences in temperature rise shown in Fig. 13(b)
are more significant, particularly at higher current levels,
with the smallest three-in-parallel solution having the highest
temperature rise as might be expected. Higher temperature rise
for the two parallel inductors than for the single inductor is explained by a less optimal breakdown of core and winding losses
due to the ratio of core:window area in this case. Nonetheless,
all designs operate well within the specified temperature rise of
50 ◦ C.
V. CONCLUSION AND FUTURE DEVELOPMENTS
The application of distributed inductors as a means for reducing the size of high-current, high-frequency inductor designs as
required in VRM applications was demonstrated. Designs are
based on standard commercial planar cores with PCB windings,
which are designed for integration within VRM motherboards.
Analysis of typical VRM inductor designs shows that the scope
for their size reduction is limited by poor loss properties of core
materials at high-frequency, nonoptimal core:window areas of
standard core sizes, and high-frequency eddy-current effects in
PCB windings. The replacement of lumped inductors by several
equivalent parallel inductors was shown to address these issues
through improved utilization of core and winding areas, which
[1] M. Duffy, C. Collins, F. M. F. Rhen, P. McCloskey, and S. Roy, “High current inductor design for MHz Switching,” in Proc. IEEE Power Electron.
Spec. Conf. (PESC), 2008, Rhodes, Greece, CD-ROM, Jun., pp. 2672–
2677.
[2] HM37 High Current Low Loss Ferrite Cube Inductors Data Sheet,
BI Technologies, Fullerton, CA. (2009/10). [Online]. Available:
www.bitechnologies.com
[3] IHLM-2525CZ Low Profile, Power Inductors Data Sheet, Vishay Malvern,
PA. (2009, May 11). [Online]. Available: www.vishay.com
[4] Y. Dong, F. C. Lee, and M. Xu, “Evaluation of coupled inductor voltage
regulators,” in Proc. 23rd Annu. IEEE Appl. Power Electron. Conf. Expo.
(APEC) 2008, 24–28 Feb., pp. 831–837.
[5] Y. Yugang, Y. Dong, and F. C. Lee, “A new coupled inductors design
in 2-phase interleaving VRM,” in Proc. IEEE 6th Int. Power Electron.
Motion Control Conf. (IPEMC) 2009, 17–20 May, pp. 344–350.
[6] Y. Dong, J. Zhou, F. C. Lee, M. Xu, and S. Wang, “Twisted core coupled
inductors for microprocessor voltage regulators,” IEEE Trans. Power
Electron., vol. 23, no. 5, pp. 2536–2545, Sep. 2008.
[7] S. Prabhakaran, C. R. Sullivan, T. O’Donnell, M. Brunet, and S. Roy,
“Microfabricated coupled inductors for DC-DC converters for microprocessor power delivery,” in Proc. IEEE 35th Annu. Power Electron. Spec.
Conf. (PESC) 2004, 20–25 Jun., vol. 6, pp. 4467–4472.
[8] N. Wang, T. O’Donnell, R. Meere, F. M. F. Rhen, S. Roy, and S. C.
O’Mathuna, “Thin-film-integrated power inductor on Si and its performance in an 8-MHz buck converter,” IEEE Trans. Magn., vol. 44, no. 11,
pp. 4096–4099, Nov. 2008.
[9] M. Wang, I. Batarseh, K. D. T. Ngo, and H. Xie, “Design and fabrication of
integrated power inductor based on silicon molding technology,” in Proc.
IEEE Power Electron. Spec. Conf. (PESC) 2007, 17–21 Jun, pp. 1612–
1618.
[10] J. M. Rivas, R. S. Wahby, J. S. Shafran, and D. J. Perreault, “New architectures for radio-frequency DC–DC power conversion,” IEEE Trans.
Power Electron., vol. 21, no. 2, pp. 380–393, Mar. 2006.
[11] D. J. Perreault, J. Hu, J. M. Rivas, Y. Han, O. Leitermann, R. C. N. PilawaPodgurski, A. Sagneri, and C. R. Sullivan, “Opportunities and challenges
in very high frequency power conversion,” in Proc. 24th Annu. IEEE Appl.
Power Electron. Conf. Expo. (APEC) 2009, pp. 1–14.
COLLINS AND DUFFY: LIMITS AND OPPORTUNITIES FOR DISTRIBUTED INDUCTORS
[12] B. J. Swart, J. A. Ferreira, and J. D. Van Wyk, “Distributed magnetic
components for PCB assembly,” in Proc. 25th IEEE Power Electron.
Spec. Conf. (PESC) 1994, Jun., vol. 2, pp. 1315–1322.
[13] C. Collins and M. Duffy, “Distributed (parallel) inductor design for VRM
applications,” IEEE Trans. Magn., vol. 41, no. 10, pp. 4000–4002, Oct.
2005.
[14] ON Semiconductor ADP3198 datasheet, 8-Bit Programmable 2- to 4Phase Synchronous Buck Controller. (2008, Jan.). [Online]. Available:
http://www.onsemi.com
[15] Intersil ISL6312 datasheet, Four-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR10, VR11, and AMD Applications.
(2010, Feb. 25). [Online]. Available: http://www.intersil.com
[16] P. Xu, J. Wei, K. Yao, Y. Meng, and F. C. Lee, “Investigation of candidate topologies for 12 V VRM,” in Proc. 17th Annu. IEEE Appl. Power
Electron. Conf. Expo. (APEC) 2002, vol. 2, pp. 686–692.
[17] Intel. (2005, Mar.). Voltage Regulator Module and Enterprise Voltage
Regulator-Down (EVRD) 10.1 Design Guidelines, [Online]. Available:
http://download.intel.com/support/processors/xeon/sb/30273203.pdf
[18] C. W. McLynam, Transformer and Inductor Design Handbook, 2nd ed.
New York: Dekker, 1988.
[19] W. G. Hurley, “Optimizing core and winding design in high frequency
transformers,” in Proc. IEEE Int. Power Electron. Congr., 1996, Tech.
Proc. CIEP 1996, 14–17 Oct., pp. 2–13.
[20] Planar ER Cores and Accessories, Ferroxcube, Eindhoven, The Netherlands. (2008, Sep.) [Online]. Available: http://www.ferroxcube.com
[21] IPC, Generic Standard on Printed Board Design, IPC-2221 Standard, Feb.
1998.
[22] Design of Planar Power Transformers, Ferroxcube, Eindhoven, The
Netherlands, Application Note. (1997, May). [Online]. Available:
http://www.ferroxcube.com/appl/info/plandesi.pdf
[23] J. Li, T. Abdallah, and C. R. Sullivan, “Improved calculation of core loss
with non-sinusoidal waveforms,” in Proc. Ind. Appl. Conf. (IAS) 2001,
Oct., vol. 4, pp. 2202–2210.
[24] K. Venkatachalam, C. R. Sullivan, T. Abdallah, and H. Tacca, “Accurate prediction of ferrite core loss with non-sinusoidal waveforms using
only steinmetz parameters,” in Proc. 8th IEEE Workshop Comput. Power
Electron., Compel 2002, Jun., pp. 36–41.
[25] Ansoft, Maxell 2D, Student Version 3.1.04.
[26] R. Prieto, J. A. Oliver, and J. A Cobos, “Study of non-axisymmetric
magnetic components by means of 2D FEA solvers,” in Proc. 36th IEEE
Power Electron. Spec. Conf.(PESC) 2005, Jun., pp. 1074–1079.
2721
[27] W. G. Hurley, E. Gath, and J. G. Breslin, “Optimizing the AC resistance of
multilayer transformer windings with arbitrary current waveforms,” IEEE
Trans. Power Electron., vol. 15, no. 2, pp. 369–376, Mar. 2000.
[28] J. A. Ferreira, “Improved analytical modeling of conductive losses in magnetic components,” IEEE Trans. Power Electron., vol. 9, no. 1, pp. 127–
131, Jan. 1994.
[29] W. G. Odendaal and J. A. Ferreira, “A thermal model for high-frequency
magnetic components,” IEEE Trans. Ind. Appl., vol. 35, no. 4, pp. 924–
931, 1999.
[30] J. Sun, Y. Ren, M. Xu, and F. C. Lee, “Light load efficiency improvement
for laptop VRs,” in Proc. IEEE Appl. Power Electron. Conf. (APEC) 2007,
Feb., pp. 120–126.
Christina Collins graduated with B.E. and Ph.D. degrees from National University of Ireland, Galway,
Ireland, in 2002 and 2010, respectively.
She is currently a Design Engineer with Excelsys
Ltd., Cork, IRELAND. Her research interests include
planar magnetic design for voltage regulator modules.
Maeve Duffy graduated with B.E. and Ph.D. degrees
from National University of Ireland (NUI), Galway,
Ireland, in 1992 and 1997, respectively.
She is currently a Lecturer in the Electrical and
Electronic Engineering Department, NUI. Her research interests include magnetic component modeling and design for power electronic and biomedical
applications.