Positive Output Super-Lift Luo-converters
Dr. Fang Lin Luo, IEEE Senior Member and Mr. Lesheng Zhang
School of EEE. Nanyang Technological University
Nanyang Avenue, Singapore 639798
Abstract
The Elementary circuit is shown in figure 1
Voltage Lift Technique has been successfully employed in
design of DC/DC converters, e.g. four series Luo-Converters.
However the output voltage increases in arithmetic
progression. Luo series Elementary, Re-lift and Super- lift
converters introduces a novel approach –Super Lift technique
that implements the output voltage increasing in geometric
progression. It effectively enhances the voltage transfer gain
in power series.
Iin
D1
Io
L1
+
Vin
-
C2
+
R
V C2
-
+
Vo
-
Figure 1. Elementary circuit
Voltage Lift (VL) Technique is a popular method widely used
in electronic circuit design. It has been successfully employed
in DC/DC converter applications in recent years and opened a
way to design high voltage gain converters. Four series LuoConverters [1-9] are the examples of VL technique
implementations. However, the output voltage increases in
stage by stage just along the arithmetic progression [10]. Luo
series Re-Lift and Super lift converters introduces a novel
approach – Super-Lift (SL) technique that implements the
output voltage increasing in stage by stage along the
geometric progression. It effectively enhances the voltage
transfer gain in power series.
In order to sort these converters different from existing VL
converters, we entitle converters “Positive Output Super-lift
converters”. These are two sub-series: main series and
additional series. Each circuit of the main series has one
switch S, n inductors, 2n capacitors and (3n-1) diodes. Each
circuit of the additional series has one switch S, n inductors.
2(n+1) capacitors and (3n+1) diodes. The conduction duty
ratio is k, switching frequency is f, switching period is T=1/f,
the load is resistive load R. The input voltage and current are
Vin and Iin, output voltage and current are Vo and Io. Assume
no power losses during the conversion process, Vin x Iin=Vo x
V0
V in
Here we introduce the first three stages of Positive Output
Super-Lift Converters. For convenience to explain, we call
them Elementary circuit, Re-Lift circuit and Triple-Lift circuit
respectively. We can number them as n=1, 2 and 3.
1.1 Elementary circuit
+
V C1
-
C1
1 Introduction
Io. The voltage transfer gain is G: G =
D2
The Voltage across capacitor C1 is charged to Vin. The current
iL1 flowing through inductor L1 increases with voltage Vin
during switching-on period kT and decreases with voltage –
(Vo –2Vin) during switching-off period (1-k)T. Therefore,
kTVin = (1 − k )T (V 0 − 2Vin )
Vo =
2−k
Vin
1− k
(1)
1.2 Re-Lift circuit
The Re-Lift circuit is derived from Elementary circuit by adding
the parts (L2-D3-D4-D5-C3-C4). Its circuit diagram is shown in
figure 2.
Iin
D1
D2
D6
D4
Io
L1
C1
+
V C1
-
L2
+
C3
+
V C3
+
D5
Vin
-
D3
C2
+
V C2
-
S
C4
R
Vo
+
V C4
-
-
Figure 2. Re-Lift circuit
The voltage across capacitor C1 is charged to Vin. As
described in previous section the voltage V1 across capacitor
C2 is V1 = 2 − k Vin
1− k
The voltage across capacitor C3 is charged to V1. The current
flowing through inductor L2 increases with Voltage V1 during
switching-on period k and decreases with voltage –(Vo-2V1)
during switching-off period (1-k)T. Therefore, the output
voltage Vo across capacitor C4 is:
kTV1 = (1 − k )T (Vo − 2V1 )
Vo =
2− k
2−k 2
V1 = (
) Vin
1− k
1−k
(2)
1.3 Triple-Lift circuit
Triple-Lift circuit is derived from Re-Lift circuit by secondly
repeating the parts (L2-D3-D4-D5-C3-C4). Its circuit diagram is
shown in figure 3 below,
Iin
D1
D2
D6
D4
388V
D10
D8
The data inputs were Vin=12V, L1=L2=10mH, C1-C4=2.2uF and
R=10MO, k=0.5 and f=10kHz. To make the simulation results
as close to the actual experimental results as possible, the
setting of the MOSFET (model IXTH24N50) was modified
according to its capacitance curves of Cbd, Cgso and Cgdo. The
final setting for Rd, Cbd, Cgso and Cgdo were 0.23O, 2000p, 3.8n
and 2000p respectively. The simulation results are as shown in
figures 4-5.
Io
L1
C1
+
VC1
-
L2
+
C3
+
VC3
-
C5
D5
+
VC5
-
+
D9
R
Vin
D3
-
C2
D7
+
VC2
-
C4
+
VC4
-
Vo
S
C6
+
VC6
-
0V
Figure 3. Triple-Lift circuit
The voltage across capacitor C1 is charged to Vin. As
described before, the voltage across capacitor C2 is
2−k
V =
V , and the voltage across capacitor C4 is
1
1− k
200V
-
in
2− k 2 .
V2 = (
) Vin
1− k
The voltage across capacitor C5 is charged to V2. The current
flowing through inductor L3 increases with voltage V2 during
switching-on period and decreases with voltage –(Vo-2V2)
during switching-off (1-k) T. Therefore, the output voltage Vo
across capacitor C6 is;
97.700ms 97.750ms 97.800ms 97.850ms
V(D5:2) V(D3:2) V(M5:g) V(C3:2)
97.900ms
97.950ms
98.000ms
98.050ms
Time
Figure 4. Waveforms of Vgs, Vds and Vout that are indicated on
the Pspice simulation graph by V (M 5: g), V (D3: 2) and V (D5:
2) respectively
184mA
100mA
kTV 2 = (1 − k ) T (V o − 2V 2 )
Vo =
2−k
2−k 2
2−k 3
V2 = (
) V1 = (
) Vin
1− k
1− k
1− k
(3)
0A
1.4. Higher Order Lift circuit
Higher order Lift circuit can be designed by just multiple
repeating the parts (L2-D3-D4-D5-C3-C4). For nth order lift
circuit, the final output voltage across capacitor C2n is
Vo = (
98.05ms
98.10ms
98.15ms
98.20ms
98.25ms
Time
Figure 5. Waveforms of IL1, IL2, and IR1
2− k n
) Vin
1− k
The Voltage transfer gain is G = Vo = ( 2 − k ) n
Vin
1− k
97.90ms
97.95ms
98.00ms
I(L1) I(L2) I(R1)
(4)
The simulation results show that Vout can reach 388V that is
much higher than the theoretical one. For IL2, there is a ripple
when it drops from a high value to zero, but it does not affect
the circuit operation much.
2.2 Simulation results of Triple-Lift circuit
2 Simulation
Before building up the circuits, Pspice simulation software
package was used to these converters to verify the design and
calculation results.
2.1 Simulation results of Re-Lift circuit
The data inputs were Vin=10V, L1=L2=L3=10mH, C1-C6=2.2uF
and R=10MO, k=0.5 and f=10kHz. The final values for Rd, Cbd,
Cgso and Cgdo were 0.23O, 450p, 3.8n and 150p respectively. The
simulation results are as show in figures 6-7.
1.3KV
1.0KV
0.5KV
0V
487.35ms
V(D9:2)
487.40ms
487.45ms
V(C5:1) V(V4:+)
487.50ms
487.55ms
487.60ms
487.65ms
487.70ms
Time
Figure 6. Waveforms of Vgs, Vds and Vout that are indicated on
the PspiceSimulation graph by V (V4:+), V(D10:2)and
V(D9:2)respectively
Figure 8. Waveforms of Vgs(channel 1) and Vds(channel 2) at
Vin=12V and k=0.5
529mA
400mA
200mA
0A
483.105ms
I(L1)
483.150ms
483.200ms
I(L2) I(L3) I(R1)
483.250ms
483.300ms
483.350ms
483.400ms
483.450ms 483.500ms
Time
Figure 7. Waveforms of IL1, IL2, IL3 and IR1
Vout is 1265V shown in figure 6 that is also much higher than
the theoretical one. It will be explained later.
Figure 9. Waveforms of Vgs(channel 1) and Vds(channel 2) at
Vin=12V and k = 0.33(changing point)
3. Experiment results
A total of 5 experiments have been carried out to investigate
the behaviours of three circuits namely the Elementary circuit,
Re-lift circuit and the Triple-lift circuit. The main components
used for the experiments are shown below:
C1. 2.2uF/100V
C2, C2, C3, C4 and C5. 2.2uF/250V
C6. 2.5uF/1000V
R1. 10MO
D1-D10. IOETS12
MOSFET. IXTH24N50
3.1 Experiments results on Re-Lift Circuit
Figure 10. Waveforms of Vgs(channel 1) and Vds(channel 2) at
Vin=12V and k=0. 70(changing point)
After careful measurement, we obtained the voltage value of
Vo=108V. For Re-Lift circuit, there are two ‘changing points’
during the variation of k. One occurs at about 0.33 and the It is clear that when the value of k is outside the range of 0.33other occurs at about 0. 7. Based on the setting of Vin=12V and 0.70 (as shown in figures 9 and 10), the shape of the Vds
waveforms changes in alternate periods. The voltage between
f =100kHz, the waveforms are shown as in figure 8-figure 10.
the drain and source becomes alternatively high and low in
every two continued periods.
3.2 Experiments results on Triple-Lift Circuit
Base on the setting of Vin=10V and f=10kHz, we obtained the
voltage value of Vo=425V. The waveforms of Vgs and Vds are
shown in figure 11-12.
4. Conclusion
In conclusion, a new series of DC/DC converters – Positive
Output Super-Lift Converters have been successfully created.
It effectively increased the voltage transfer gain in the power
series. It is also observed that the experimental results were
better than the theoretical ones, especially when the circuits
were operated within the most effective frequency range. This
series of Luo-converters will also be applied in industrial
applications.
5. Acknowledgements
Last but not least, we wish to thank NTU Power Research Lab
staff for their patience and excellent support.
6. References
Figure 11. Waveforms of Vgs (channel 1) and Vds (channel 2) at
Vin=10V, f=10kHz and k=0.5
Figure 12. Waveforms of Vgs (channel 1) and Vds (channel 2) at
Vin=10V, f=10kHz and k=0.64
Comparing the experimental and simulation results, the
experimental values are generally lower than those of
simulation. It is because the components in simulation are
ideal. In the actual situation, voltage drop exists across each
component along with some power loss in the form of heat.
Both experimental and simulation values are higher than the
theoretical ones. This is attributed to errors in the MOSFET
and the variation in frequency also has some significant
effects on the results.
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