CMOS Logic Circuit Design
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Static and Dynamic CMOS Design
• Basic Considerations
• Important Technical Concepts
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Transfer (DC) Characteristic and Switching Point
Transient (AC) Characteristic as well as Rise-Time, Fall-Time and Delay Time
Fan-In and Fan-Out
• Static CMOS-Logic
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Conventional Complementary MOS Logic
Pseudo n-MOS Logic
Pass-Transistor Logic
• Dynamic CMOS-Logic
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Precharge-Evaluate (PE) Logic
NP Domino Logic
CMOS Domino Logic
Mattausch, CMOS Design, H20/4/25
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Basic Considerations
Mattausch, CMOS Design, H20/4/25
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Meaning of Static and Dynamic CMOS Logic
Logic
Output
Noise
Noise
Noise
Static Logic
VDD
(1)
Dynamic Logic
VSS
(0)
Time
Static CMOS logic actively restores the logic output values,
while dynamic CMOS logic does not.
Mattausch, CMOS Design, H20/4/25
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Advantages of Static and Dynamic CMOS Design
static design
dynamic design
- high functional reliability
- high switching speed
- easy circuit design
- small area consumption
- unlimited validity of logic outputs
- low power dissipation
The most important design goals determine, whether a
static or a dynamic design technology is chosen.
Mattausch, CMOS Design, H20/4/25
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Important Technical Concepts
- Transfer (DC) Characteristic and
Switching Point
Mattausch, CMOS Design, H20/4/25
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Transfer (DC) Characteristic
(Example Inverter)
Inverter Circuit
Inverter Transfer Characteristic
VOH = “high” output voltage
VOL = “low” output voltage
VIL = max. “low” input voltage
VIH = min. “high” input voltage
VIL -VSS =“low” noise margin
VDD - VIH = “high” noise margin
The transfer characteristic of CMOS logic is analog. The
region between points A and B (slope = 1) is logically invalid.
Mattausch, CMOS Design, H20/4/25
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Switching Point VSP
(Example Inverter)
Switching-Point Definition
Switching-Point Condition
ID, n− MOS = ID, p− MOS
βn
(V
2
SP
VSP =
− VTH, n ) =
2
βp
(VDD − V
2
SP
− VTH ,p )
2
βn
⋅ V + (VDD − VTH, p )
β p TH, n
βn
1+
βp
β p ≈ β n ; VTH , p ≈ VTH, n
VSP ≈
VDD
2
At the switching point both transistors M1 and M2 are
in the saturation region and have equal conductance.
Mattausch, CMOS Design, H20/4/25
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Transfer Characteristic and Transistor-Size
(Example Inverter)
p- and n-MOS transistor design
influences the transfer characteristic
β=
SP1
<<1
SP2
SP3
>>1
Correlation between β and
MOS-transistor parameters
µ ⋅ε ⋅ W
t ox ⋅ L
µn ≈ 3µ p
β p ≈ βn
µ = carrier mobility
ε = gate-insulator permittivity
tox = gate-insulator thickness
W = MOS transistor width
L = MOS transistor length
Wp ≈ 3Wn
The choice of MOS-transistor length L and width W is a
major design freedom in CMOS circuit design.
Mattausch, CMOS Design, H20/4/25
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Transfer Characteristic of NAND Gates
N-input NAND Gate
Switching-point N-input NAND Gate
SPN-NAND
, N-NAND
N
SPinv
<<1
,inv
VSP =
βn
⋅V + (VDD − VTH , p )
N m β p TH ,n
βn
1+
m
N βp
; m = 1~2
To keep the switching point of the N-input NAND gate
at about VDD/2, it is necessary to choose Wn~NWp/3.
Mattausch, CMOS Design, H20/4/25
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Transfer Characteristic of NOR Gates
N-input NOR Gate
Switching-point N-input NOR Gate
,inv
, N-OR
N
>>1
SPinv
SPN-OR
N m βn
VSP =
βp
⋅ VTH, n + (VDD − VTH, p )
1+
N mβ n
; m = 1~2
βp
To keep the switching point of the N-input NOR gate at
about VDD/2, it is necessary to choose Wp~3NWn.
Mattausch, CMOS Design, H20/4/25
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Important Technical Concepts
- Transient (AC) Characteristic as well as
Rise-Time, Fall-Time and Delay Time
Mattausch, CMOS Design, H20/4/25
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Rise-, Fall- and Delay-Time of Logic Circuits
Logic Gate Transient
Input and Output
Rise-, Fall- and Delay-Time
Rise-Time tr
VDD
50% (VDD/2)
Time for a transient waveform to rise from
10% to 90% of its steady state values.
Fall-Time tf
VDD
Time for a transient waveform to fall
from 90% to 10% of its steady state
values.
Delay-Time td
Time difference from the 50% transition
level of the input waveform to the 50%
transition level of the output waveform.
Rise-, fall and delay time are the main quantities for
characterizing the performance of a logic CMOS circuit.
Mattausch, CMOS Design, H20/4/25
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Simple AC Model/Equations for CMOS Logic
fall time: pull-down network
rise time: pull-up network
VDD
VDD
VSS
VSS
t f = kf
CL
;
β pd,eff ⋅ VDD
CL
1
; t dr ≈ 2 tr
β pu ,eff ⋅ VDD
t df ≈ 12 t f
tr = k r
t d,av ≈
t dr + tdf
; kf and kr depend on fabrication technology (~2-4)
2
Pull-down, pull-up network and the load capacitance CL
determine the AC-performance of the CMOS logic circuit.
Mattausch, CMOS Design, H20/4/25
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Important Technical Concepts
- Fan-In and Fan-Out
Mattausch, CMOS Design, H20/4/25
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Definition of Fan-In and Fan-Out for Logic Gates
fan-in = m
1
2
3
m-1
m
fan-out = k
1
2
3
k
The fan-in of a logic gate is the number of its inputs.
The fan-out of a logic gate is the number of its output
connections to other gates.
Mattausch, CMOS Design, H20/4/25
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Delay-Time Effect of Fan-In (m) and Fan-Out (k)
(Constant n-MOS and p-MOS transistor W/L-ratios, respectively)
NAND-Gate
NOR-Gate
tdf,NAND = m⋅ (m⋅ t fin + k⋅ t fex )
tdf,NOR = m⋅ t fin + k⋅ t fex
tdr,NAND = m⋅ trin + k⋅ trex
tdr,NOR = m⋅ (m⋅ trin + k⋅ trex )
tfin and trin are internal fall- and rise-time of a minimum sized inverter, due to its own
gate and drain capacitances, respectively.
tfex and trex are external fall- and rise-time of a minimum sized inverter, due the external
load of a minimum sized inverter with typical routing capacitance, respectively.
The fan-in has a quadratic impact on NAND-Gate fall
times as well as NOR-Gate rise times.
Mattausch, CMOS Design, H20/4/25
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Static CMOS-Logic
- Conventional Complementary MOS
(CMOS) Logic
- Pseudo n-MOS Logic
- Pass-Transistor Logic
Mattausch, CMOS Design, H20/4/25
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Conventional Static CMOS Logic
Conventional CMOS principle
A
Pull-Up
Network
B
Fu (A, B,⋅⋅⋅, N)
Example with fan-in equal 5
Pull-Up
Network
Z = A • (E + D) + (B • C) • (E + D)
Fd (A, B,⋅ ⋅⋅,N)
= Fu (A, B,⋅⋅⋅, N)
Pull-Down
Network
N
Pull-Down
Network
Z = A• (B+ C) + (D• E)
Fd (A, B,⋅ ⋅⋅,N)
Conventional CMOS logic is static because 1 and 0 are
restored by pull-up and pull-down network, respectively.
Mattausch, CMOS Design, H20/4/25
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Pseudo n-MOS Logic
Principle:
Use only the pull-down network.
Example with fan-in equal 5
Chose pull-up strength of p-MOS smaller
than pull-down strength of network.
A
VDD
Pull-Down
Network
B
VSS
Fd (A, B,⋅ ⋅⋅,N)
Z = A• (B+ C) + (D• E)
Pull-Down
Network
N
Fd (A, B,⋅ ⋅⋅,N)
VSS
Advantage: Less transistors and lower input capacitance.
Disadvantage: High power dissipation and low pull-up speed.
Mattausch, CMOS Design, H20/4/25
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Pass-Transistor Logic
V1
V2
Vk
P1
P2
FP =
P1 (V1 ) + P2 (V2 ) + ⋅⋅⋅ + Pk (Vk )
Pk
Pass-Transistor Logic Gate
Any logic function FP can be constructed by controlling a set
of pass signals Pi by another set of control signals Vi.
Mattausch, CMOS Design, H20/4/25
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2-Input Pass-Transistor Gate Example
Realization Table of 2-Input Gates
Operation
P1
P2
P3
P4
NOR(A,B)
XOR(A,B)
NAND(A,B)
AND(A,B)
OR(A,B)
0
0
0
1
1
0
1
1
0
1
0
1
1
0
1
1
0
1
0
0
Implementation with n-MOS
and p-MOS transistors
Implementation with n-MOS transistors
(Disadvantage: Noise-margin of “high” level reduced by Vth,n)
The pass-transistor logic has a good implementation density,
but may have slow switching speed.
Mattausch, CMOS Design, H20/4/25
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Dynamic CMOS-Logic
- Precharge-Evaluate (PE) Logic
- NP Domino Logic
- CMOS Domino Logic
Mattausch, CMOS Design, H20/4/25
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Precharge-Evaluate (PE) Logic
Principle:
Use only the pull-down network.
clock=0: Precharge output to 1.
clock=1: Evaluate pull-down network.
Example with fan-in equal 5
VDD
Z = A• (B+ C) + (D• E)
Fd (A, B,⋅ ⋅⋅,N)
A
B
Pull-Down
Network
N
Fd (A, B,⋅ ⋅⋅,N)
Pull-Down
Network
clock
VSS
Advantage: Low power dissipation and high speed.
Disadvantage: Low reliability and difficult design.
Mattausch, CMOS Design, H20/4/25
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NP Domino Logic
Alternating cascade of PE-logic with pull-up/pull-down networks.
VDD
VDD
Pull-Up
Network
F2
A
B
N
Pull-Down
Network
F1
clock
Pull-Down
Network
F3
clock
clock
VSS
VDD
VSS
VSS
Low power and high speed, but difficult to design.
Mattausch, CMOS Design, H20/4/25
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CMOS Domino Logic Gate
VDD
Buffer and
“high” level restoring
elements
Fd (A, B,⋅ ⋅⋅,N)
A
B
N
Pull-Down
Network
Fd (A, B,⋅ ⋅⋅,N)
clock
VSS
CMOS domino logic achieves a good balance of switching
speed, area/power consumption and design reliability.
Mattausch, CMOS Design, H20/4/25
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CMOS Domino Logic Circuit
VDD
A
B
N
VDD
VDD
Pull-Down
Network
Pull-Down
Network
Pull-Down
Network
Fd1
Fd 3
Fd 2
clock
clock
clock
VSS
VSS
VSS
A CMOS domino logic circuit uses only pull-down networks.
Mattausch, CMOS Design, H20/4/25
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