Introduction to
CMOS VLSI
Design
Lecture 18:
Design for Low Power
David Harris
Harvey Mudd College
Spring 2004
Outline
q
q
q
q
Power and Energy
Dynamic Power
Static Power
Low Power Design
18: Design for Low Power
CMOS VLSI Design
Slide 2
Power and Energy
q Power is drawn from a voltage source attached to
the VDD pin(s) of a chip.
q Instantaneous Power: P(t ) = iDD (t )VDD
q Energy:
q Average Power:
18: Design for Low Power
T
T
0
0
E = ∫ P ( t )dt = ∫ iDD (t )VDD dt
T
Pavg
E 1
= = ∫ iDD (t )VDD dt
T T 0
CMOS VLSI Design
Slide 3
Dynamic Power
q Dynamic power is required to charge and discharge
load capacitances when transistors switch.
q
q
q
q
One cycle involves a rising and falling output.
On rising output, charge Q = CVDD is required
On falling output, charge is dumped to GND
VDD
This repeats Tfsw times
iDD(t)
over an interval of T
fsw
18: Design for Low Power
CMOS VLSI Design
C
Slide 4
Dynamic Power Cont.
Pdynamic =
VDD
iDD(t)
fsw
18: Design for Low Power
CMOS VLSI Design
C
Slide 5
Activity Factor
q Suppose the system clock frequency = f
q Let fsw = αf, where α = activity factor
– If the signal is a clock, α = 1
– If the signal switches once per cycle, α = ½
– Dynamic gates:
• Switch either 0 or 2 times per cycle, α = ½
– Static gates:
• Depends on design, but typically α = 0.1
q Dynamic power:
Pdynamic = α CVDD 2 f
18: Design for Low Power
CMOS VLSI Design
Slide 7
Short Circuit Current
q When transistors switch, both nMOS and pMOS
networks may be momentarily ON at once
q Leads to a blip of “short circuit” current.
q < 10% of dynamic power if rise/fall times are
comparable for input and output
18: Design for Low Power
CMOS VLSI Design
Slide 8
Example
q 200 Mtransistor chip
– 20M logic transistors
• Average width: 12 λ
– 180M memory transistors
• Average width: 4 λ
– 1.2 V 100 nm process
– Cg = 2 fF/µm
18: Design for Low Power
CMOS VLSI Design
Slide 9
Dynamic Example
q Static CMOS logic gates: activity factor = 0.1
q Memory arrays: activity factor = 0.05 (many banks!)
q Estimate dynamic power consumption per MHz.
Neglect wire capacitance and short-circuit current.
18: Design for Low Power
CMOS VLSI Design
Slide 10
Static Power
q Static power is consumed even when chip is
quiescent.
– Ratioed circuits burn power in fight between ON
transistors
– Leakage draws power from nominally OFF
devices
Vgs −Vt
I ds = I ds 0 e
nvT
−Vds


vT
1 − e 


Vt = Vt 0 − ηVds + γ
18: Design for Low Power
(
φs + Vsb − φs
CMOS VLSI Design
)
Slide 12
Ratio Example
q The chip contains a 32 word x 48 bit ROM
– Uses pseudo-nMOS decoder and bitline pullups
– On average, one wordline and 24 bitlines are high
q Find static power drawn by the ROM
– β = 75 µA/V2
– Vtp = -0.4V
18: Design for Low Power
CMOS VLSI Design
Slide 13
Leakage Example
q The process has two threshold voltages and two
oxide thicknesses.
q Subthreshold leakage:
– 20 nA/µm for low Vt
– 0.02 nA/µm for high Vt
q Gate leakage:
– 3 nA/µm for thin oxide
– 0.002 nA/µm for thick oxide
q Memories use low-leakage transistors everywhere
q Gates use low-leakage transistors on 80% of logic
18: Design for Low Power
CMOS VLSI Design
Slide 15
Leakage Example Cont.
q Estimate static power:
18: Design for Low Power
CMOS VLSI Design
Slide 16
Low Power Design
q Reduce dynamic power
– α:
– C:
– VDD:
– f:
q Reduce static power
18: Design for Low Power
CMOS VLSI Design
Slide 19