Intl. Journal of Microcircuits and Electronic Packaging
Quantifying the Impact of a Non-Ideal Return
Path
Andrew Byers and Melinda Piket-May
University of Colorado at Boulder
Campus Box 425
Boulder, Colorado 80309
Phone: 303-492-7891
Fax: 303-492-5323
e-mails: byersa@maori.colorado.edu, mjp@maori.colorado.edu
Stephen H. Hall
Intel Corporation
JF2-54
2111 NE 25th Ave.
Hillsboro, Oregon 97124
Phone: 503-264-8695
Fax: 503-264-6053
e-mail: stephen.h.hall@intel.com
Abstract
Non-ideal return path issues can pose several significant problems for high-speed digital system designers. Occurring in many different
forms, non-ideal return paths can cause detrimental effects such as ground bounce, increased signal delays, signal disruption, and electromagnetic incompatibility. In an ideal system, the return current travels through the reference plane directly beneath the transmission line
carrying a signal. A non-ideal return path occurs when there is a discontinuity in the reference plane that causes the return current to diverge
away from the ideal path. Experiment and simulation were used to quantify the timing and signal quality impacts of a transmission line
passing over a slot in the ground plane. This ground slot structure represents the simplest example of a non-ideal return path, and is well
suited to evaluate the impact that a poor return path will have on the performance of a digital system. Although the specifics of this particular
return path problem will differ from more complicated situations, many of the signal quality and timing trends can be generalized to return
path problems of a more complex nature. Subsequently, this study will help identify the performance degradation trends that can be expected
in a digital system design when the engineer is not able to provide a perfect path for the return currents. Additionally, the use of bypass
capacitors to shorten the return current path length and thereby reduce the non-ideal effects on signal integrity is presented in this paper.
Key words:
1. Introduction
Signal Integrity, Timing Budget, Coupling, Return Current Path,
Finite Difference Time Domain, Time Domain Reflectometry,
Ground Gap, and Decoupling Capacitors.
Non-ideal return paths manifest themselves in several different
ways in high speed interconnect systems. A few common examples
are signal lines passing over split power planes used to facilitate
dual voltages, a line changing reference planes, a meshed or slotted
ground plane, and package/connector power and ground return pins.
Essentially, any situation where the return current is forced to diverge from its ideal path directly beneath the signal trace can be
considered a non-ideal return path. Regardless of the form, these
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Quantifying the Impact of a Non-Ideal Return Path
non-ideal situations have detrimental effects on signal integrity
and timing reliability. Any reflected or transmitted disturbance
caused by a non-ideal current return path can distort the waveforms, and if severe enough, can cause system failures due to
excessive ringing or overshoot on the bus. Furthermore, nonideal return paths tend to cause timing pushouts. A timing pushout
is an increase in the flight time of a signal compared to an ideal
interconnect. Often seen as a ledge in the rising/falling edge or a
diminished rise time at the receiver, these pushouts consume valuable interconnect timing budgets allocated to a designer.
This paper highlights three major problems associated with a
ground slot non-ideal return path: A large inductive disruption seen
at the driver, a timing pushout at the receiver, and an unusually high
coupling coefficient between lines that traverse the same gap. The
non-ideal effects measured were dependent on the return current
divergence path and gap width. Any type of non-ideal return path
will introduce additional timing uncertainties into the system and
degrade timing budgets and signal integrity. Therefore, the ability to
identify and model the specific mechanisms that contribute to the
performance degradations is essential to a good design methodology. Simulation techniques using Finite Difference Time Domain
(FDTD) algorithms, as well as traditional circuit simulators were
developed and compared to measurements. The sensitivity of the
signal disruption and timing pushout due to physical parameters such
as gap width and length is described in this work. This paper quantifies the signal degradation caused by a specific return path discontinuity, explores different modeling techniques and gives insight into
the performance impact trends that can be expected for other return
path problems.
2. Background
3. Measurement and Simulation
Techniques
To quantify the impact of this return path problem, a test board
was built that consists of two parallel microstrip lines traversing a
slot in the ground plane. The layout of this test board is shown in
Figure 1. Lines traversing gaps with two different widths, 25 mils
and 100 mils, were measured. The two ground plane sections are
connected with 5 mil traces at the edges of the gap to provide a DC
connection. The microstrip lines are 6 mils wide on FR-4 dielectric,
and the line impedance is 65 ohms. All other relevant dimensions
are indicated in the Figure. It is important to note that although this
slot is placed in a ground plane for this study, slots or gaps in any
plane referenced by a transmission line will affect the return current
present on that plane. There are instances when a microstrip line is
referenced to a power plane, and the imperfections in the return path
have the same effects on a signal as seen in a corresponding groundreferenced line.
Ground planes shorted together
0.7”
Microstrip
1.4”
Bypass
capacitor
cap
landing
pads
pads
g
a
p
5.2”
0.7”
Ground planes shorted together
Microstrip
Figure 1. Ground gap test board layout used for TDR/TDT
measurements.
Time Domain Reflectometry and Time Domain Transmission
techniques (TDR/TDT) were used to measure the effects of the gap
There has been some work done in the development of equivaon flight time and signal quality. A TDR measures the Time Dolent circuits for the reference plane gap structure. A transmission
main waveform at the driver, while a TDT is measured at the reline model for the diverging return current is designed by increasing
ceiver. A TDR/TDT system uses a digital oscilloscope for measurethe length of the signal line after taking into account the microstripment and a step-pulse function generator for a source. The stepto-slotline transition1. Another model of equivalent SPICE circuit is
pulse is placed on one port of the transmission line under test using
also presented and compared to experimental results, along with fulla coaxial feed attached to a matched contact probe. The TDR syswave time domain simulations2. This model uses separate nets for
tem used in this study consisted of a Tektronix 11801B Digital Samthe lines passing over the gap and for the slotline created by the gap
pling Oscilloscope meter using a sampling head extender (cable)
itself, linking the nets through controlled current and voltage sources.
and a SD-24 TDR sampling head. Cascade Michtotech 250 micron
A more complete full-wave analysis of a line over a ground plane
GSG microprobes were used to achieve clean signal transition from
slot is also derived, and expressions for the reflection and transmisthe coaxial cable to the microstrip on the test board.
sion factors from the slot are developed along with an equivalent YSimulations were done with conventional circuit-simulator tools
parameter pi-network model3.
and a FDTD full-wave three-dimensional solver. The circuit simuThis paper provides a more extensive review of the measurable
lators used were QUAD by Viewlogic and HSPICE. Both of these
signal characteristics due to the ground gap and highlights the trends
tools use lumped and distributed models based on standard electroand sensitivities seen in both measured and simulated structures.
magnetic transmission line and lumped element equations. Although
Simple modeling techniques are suggested, and FDTD simulations
the ability to model complex geometries is sacrificed for the relaare used to augment the measurements in order to develop more
tively fast simulations, tools such as these are used to simulate large
achievable robust design guidelines.
interconnect systems with a good degree of accuracy.
The FDTD method4 directly solves Maxwell’s curl equations in
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Intl. Journal of Microcircuits and Electronic Packaging
the Time Domain. These are given in differential form as follows,
4. Disruptions Due to the Ground Slot
(1)
A. Inductive Spike on Signal Line
(2)
In the case of the ground gap depicted in Figure 1, the most immediate effect on a digital signal carried on a transmission line traversing the gap is a significant inductive spike, as seen in the measured TDR pulse in Figure 3. This disruption is caused by the increase in the current loop, which corresponds to an increased inductance from the following basic relation,
where E and H are the electric and magnetic fields, respectively, and
e and µ are the permittivity and the permeability of the material.
Since FDTD solves the basic physics of the problem, arbitrary geometries and materials can be modeled, and boundary conditions
are automatically enforced at material interfaces. In the numerical
implementation of equations (1) and (2), central differences are used
in place of the temporal and spatial derivatives, giving second order
accuracy. This yields a three dimensional grid of electric and magnetic field points, with the magnetic fields displaced by ½ of the
lattice spacing, as shown in Figure 2. The field quantities are solved
in a “leap-frog” fashion with a half time-step between the solution
of the electric and magnetic fields. The electric field is found from
the magnetic field using equation (1), and the magnetic field is found
from the resulting electric field using equation (2). The FDTD simulations performed for this project were used to augment the existing
measured data in order to uncover sensitivity trends in the data, or
how a measured electrical parameter is affected by a change in a
physical model parameter.
(3)
where L is the inductance, v is the flux defined by the magnetic field
and the area between the line and the ground plane, and I is the
current. As the gap forces the return current to diverge, the flux loop
defined by the signal line current and the ground plane current increases, thus increasing the inductance. Figure 3 shows measured
results for two different gap widths. The impedance levels shown
on this plot correspond to transitions that the TDR signal sees. The
50 ohm level is the coaxial feed line, the 65 ohm level is the microstrip
before the gap, and the 97 ohm and 115 ohms levels are the peak
impedances seen at the driver due to the gap reflections. A larger
gap width translates to a larger inductance loop, thus explaining the
higher inductive spike seen in the TDR data.
-0.11
-0.13
Z= 115
100 mil gap
voltage (V)
-0.15
-0.17
Z= 97
-0.19
-0.21
Z= 65
-0.23
25mil gap
Z= 50
-0.25
0
Figure 2. A single FDTD grid cell showing the location of
the electric and magnetic field points.
2.5E-10 5E-10 7.5E-10 1E-09 1.3E-09 1.5E-09 1.8E-09
Time (s)
Figure 3. Measured TDR inductive spike for two different
gap widths: 100 mils and 25 mils.
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Quantifying the Impact of a Non-Ideal Return Path
The inductive spike in the digital signal can pose a serious
problem since it will degrade the signal integrity at the driver
and receiver, filter the edge rate and increase inter-symbol interference. If the degradation of signal integrity is severe enough, it
is possible to cause a false trigger at the receiver or to push out
the timings enough to violate the setup or hold times. Furthermore, increased overshoot at the buffers can exacerbate oxide
stress and subsequently affect reliability.
FDTD simulations were performed on scaled-down versions
of the test board in order to avoid numerical instabilities associated with memory-intensive models due to high grid density. Also,
by running many simulations of smaller versions of the problem,
the basic performance trends and the significance of the physical
variables could be identified and verified against the measured
data trends. A typical simulation of a ground-gap model run on a
SGI Origin 200 Server took about 2 hours of CPU time and 30
Mbytes of memory. FDTD TDR simulation results for test boards
with different gap widths are shown in Figure 4. Four different
gap widths were simulated: 100mils, 50 mils, 20 mils, and 10
mils. The important trend to notice is the proportionality between the gap width and the spike magnitude. A comparison of
the spike magnitudes for the measured data and FDTD is favorable. In the 20 mil and 25 mil cases, both exhibited inductive
spike magnitudes of nearly 20% of the input step voltage. In both
the measured and simulated 100 mil cases, the relative spike
magnitudes were closer to 30% of the input step voltage.
inductor in a traditional circuit simulator would sufficiently account for the inductive spike caused by the ground plane discontinuity. The values for the inductors used in these simulations
were chosen using a first order approximation equation given by
Johnson and Graham5, as follows,
(4)
Gap
Inductance
pre-gap line
post-gap line
Figure 5. Equivalent ground gap model.
0.1
0
10nH
-0.1
voltage
1.2
1.15
1.1 100mil gap
TDR Voltage
1.05
-0.2
5nH
-0.3
nominal
1
-0.4
0.95
0.9
-0.5
0.85
0
0.8
0.75
0.7
1E-10
1.5E-10
2E-10
2.5E-10
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
time (ns)
10mil gap
3E-10
3.5E-10
Time(seconds)
Figure 4. FDTD simulations of TDR data for ground gap
encounter: inductive disruption on the signal line.
The inductive spike seen in the measured and FDTD data indicates that the phenomenon should be able to be modeled with a series inductor inserted into a transmission line5, depicted in Figure 5.
Figure 6 shows the results of QUAD circuit simulations performed
with 5nH and 10nH series inductors, along with the nominal (no
inductor) simulation. The spike magnitude scales with the inductance, as expected. In this respect, using an appropriately sized
Figure 6. QUAD simulations of series inductor inserted into
microstrip line; modeling ground gap.
In this equation, a microstrip line passing over a symmetric gap
to both sides is assumed, where D is the return current diversion
distance, w is gap width, and Lgap is the series inductance caused by
return current diverging around the gap. However, two very significant secondary effects of the ground gap, namely timing pushout
and unusually high line to line coupling, are more difficult to model
using this simple lumped element model.
B. Receiver Edge Rate Degradation
The next consequence of passing a digital signal line over a
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Intl. Journal of Microcircuits and Electronic Packaging
0.00E+00
25 mil gap
voltage (mV)
-5.00E-02
100 mil gap
-1.00E-01
-1.50E-01
-2.00E-01
first ledge area
-2.50E-01
-3.00E-01
0
2E-10
(s)
4E-10
6E-10
8E-10
time (sec)
Figure 7. Measured receiver edge rate degradation due to
ground gap encounter; 100 mil and 25 mil gap cases.
The causes of this timing pushout are not as intuitive as the reasons behind the inductive spike. The measured TDT data in Figure
7 show that a wider gap results in a more severe timing pushout. Not
only is the edge rate degraded, but there is also a ledge-type shape
occurring about halfway between the low and high voltage levels of
the pulse. Due to its severity, the ledge seen in the data threatens the
timing budget even more than the degraded edge rate. As the signal
reached the ground plane gap, a portion of the ground current “jumps”
the gap through the inherent capacitance, while the rest of the ground
current diverges around the gap. This splitting of the ground current
explains the existence and location of the ledge in the TDT waveform. The idea of a capacitance across the gap also explains why the
start of the ledge occurs earlier in the rising edge of the waveform
for a wider gap. A wider gap indicates a smaller capacitance, which
in turn would support a smaller amount of ground current passing
directly across the gap and more ground current diverging around
the gap, thus causing a more significant ledge. Identifying this
problem is an important step since it helps the designer mini-
mize the effect during the initial design and provides insight into
how to develop sufficient modeling strategies.
This curious ledge effect at the receiver is an example of a
phenomenon that a simple simulation with an inductor in the
middle of a transmission line cannot model. However, a fullwave solver with relatively free geometrical modeling ability, such
as FDTD, will be able to predict such an effect. Results from a
TDT simulation are shown in Figure 8 for the two different gap
widths, along with the nominal case of a microstrip over a continuous ground plane. Although the FDTD simulation shows a
definite ledge effect that depends on the gap width, the exact
shape of the timing pushout is not quite the same as is seen in the
measured data in Figure 7. The FDTD ledges are more prominent than their measured counterparts, stemming from the fact
that the FDTD solver makes a lossless approximation and the
model is a scaled-down version of the test board. However, the
sensitivity of the ledge location and timing impact on the gap
physical parameters is consistent between the FDTD simulations
and the measurements. Note that for the 100 mil gap, the ledge
starts at an earlier point on the rising edge of the waveform than
it does for the 25 mil gap. This supports the idea of a capacitance
existing across the gap, through which a portion of the ground
current passes. A set of FDTD simulations shows that the point during the rising edge (defined as a percentage of the final voltage level)
where the ledge begins depends on the gap width, as plotted in Figure 9. Another relationship is verified in Figure 10 between the timing pushout caused by the ledge and the return current diversion
path length around the gap. The independent axis of this Figure is
length the gap extends away from the microstrip, while the dependent axis is the receiver rise time, with a 50ps rise time on the input
signal providing the ideal case. Understanding the relationships between the physical characteristics of the gap and their impacts on
the waveforms is a good step towards developing appropriate modeling strategies. Currently, there are no lumped-element and transmission line models that show this important ledge effect at the receiver.
1.2
no gap
1
25 mil gap
0.8
Voltage (V)
gap, or slot, in the ground plane is a significant degradation of
the edge rate at the receiver. Figure 7 is a TDT measurement
showing this degradation in the edge rate, a timing pushout, for
the two gap widths. The actual amount of the timing pushout
will depend on the particular threshold voltage level of the receiver. CMOS systems typically have a threshold region that can
vary between 35% and 65% of Vcc. The actual threshold voltage
varies due to process variation and system noise. In this case, a
receiver switching at 65% of Vcc would see a much larger pushout
than one switching at 35%. The timing impact ranges from approximately 50ps at the 35% level to 150ps at the 65% level,
which is costly in any modern high-speed design. To gauge the
significance, it should be noted that modern high-speed digital
designs have typical setup and hold interconnect skew budgets
between 100 and 300ps.
0.6
0.4
100 mil gap
0.2
0
1E-10
1.5E-10
2E-10
2.5E-10
time (seconds)
3E-10
Figure 8. FDTD simulation depicting ledge effect in
receiver waveforms.
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Quantifying the Impact of a Non-Ideal Return Path
energy sourced on the driving line is coupled onto the passive
line in a mutual inductive manner, as seen in the measured results in Figure 11. This coupling has harmful repercussions since
independent signals on separate lines will be adversely affected.
The amount of coupled energy depends on the magnitude of the
inductive spike, which in turn depends on the gap width.
Receiver Ledge Dependence on Gap Width
80
ledge start (% final voltage)
75
70
65
60
55
-1.00E-01
50
driver line inductive disruption
-1.50E-01
45
0
10
20
30
40
50
60
70
gap width (mils)
voltage (V)
40
-2.00E-01
-2.50E-01
Figure 9. FDTD simulation: TDT ledge start, defined as
the starting point of the ledge normalized to the final
receiver voltage, verses the ground gap width.
-3.00E-01
passive line coupled
-3.50E-01
0
2E-10
4E-10
6E-10
8E-10
1E-09 1.2E-09 1.4E-09
time (s)
Receiver Risetime Dependence on Gap Length
Figure 11. Measured disruption on the signal line due to
ground gap and the subsequent coupling on both ends of the
passive line.
140
10%-90% risetime (ps)
120
100
80
60
40
20
0
0
200
400
600
800
1000
gap length (mils)
Figure 10. FDTD simulation: TDT timing pushout versus gap
length. The timing pushout is a combination of degraded edge
rate and a distinct ledge, while the gap length defines return
curent diversion distance.
C. Ground Slot Coupling
FDTD simulations produced results similar to the measured data.
These results are plotted along with the simulation bypass capacitor
results in Figure 13. The main difference between the FDTD simulations and the measurements was that FDTD predicted a higher
coupling factor. This may be due again to the lossless approximation and to the fact that the microstrip lines were physically closer in
the scaled-down model of the test board. Although the simulations
did not exactly match the measurements, both the FDTD simulations and the measurements indicated that the coupling coefficient
is dependent on the gap width.
Circuit simulators such as QUAD and HSPICE also are able to
model the general coupling mechanism by using a mutual inductance between two series inductors placed in separate transmission
lines. This simple representation models the effect of the gap on the
driver line with the inductor and the actual coupling mechanism
along the gap with the mutual inductance. Although this rough approximation of the problem works for first-pass designs, several of
the finer nuances of the gap are ignored, such as the receiver rise
time degradation and the coupling delay from one line to the other.
Another side effect of routing over a gap is an abnormally high
coupling factor to other transmission lines traversing the same
gap. The coupling mechanism is the gap itself, with the coupled
energy traveling in the slotline mode to the victim microstrip
line. At a distance of 1.4 inches away, nearly 15% of the pulse
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Intl. Journal of Microcircuits and Electronic Packaging
5. Use of Bypass Capacitors to
Mitigate Effects
There are two basic approaches for mitigating the effects of
the reference plane gap on signal integrity. The first is to simply
avoid routing lines over a gap. In the past, the gap presence was
not an issue, as the effects were hard to see with the slower rise
times on digital pulses and the timing pushouts were small compared to the required setup and hold times. Currently, that is not
the case, and digital designers must find alternative methods to
separate power or ground planes without creating return path
discontinuities.
The second approach is the use of bypass, or decoupling capacitors6. The return current will naturally follow the path of least inductance. Therefore, by providing bypass capacitors to shorten the path
length, the long divergence around the gap and increased inductance is avoided. Figure 12 shows measured results of placing two
bypass capacitors across the gap, one on each side of the sourced
line. Standard surface-mount capacitors were soldered across the
gap on the cap landings, as indicated in Figure 1. Surface-mount
caps are used here mainly since they present the least amount of
lead inductance to the ground current. Note that not only is the coupling to the neighboring line avoided, but also the magnitude of the
inductive spike is limited as the ground current loop is shortened.
Placing a decoupling capacitor between the two lines, the inductive
spike is reduced in magnitude by about half and the coupling is
virtually eliminated. Decoupling capacitors also reduce the timing
pushout by shortening the return current diversion distance, which
in turn decreases the delay seen by the portion of the current that is
forced around the gap.
The use of lumped bypass capacitors is available to the FDTD
model through a SPICE-FDTD interface, where the H fields in
the FDTD grid are transferred to current in the SPICE program
during runtime7, 8. This interface allows for SPICE capacitors to
be placed across the gap in the FDTD model. A simulation result
exhibiting the correct operation of the bypass capacitors is shown
in Figure 13. A 0.1:F SPICE capacitor placed between the lines
reduces the size of the inductive spike by about 50%, while also
reducing the amount of coupling by nearly 75%.
1
0.8
0.6
no bypass cap
driver line
0.4
bypass cap
no bypass cap
0.2
passive line
0
bypass cap
-0.2
-0.4
1E-10
1.5E-10
2E-10
2.5E-10
Time (seconds)
Figure 13. The use of lumped SPICE bypass caps in the FDTD
grid to mitigate the inductive disruption and coupling caused
by the ground plane gap.
0.05
no caps
6. Conclusions
passive line
0
two caps
The multiple problems posed by non-ideal return paths limit the
speed and reliability of high-speed digital designs. Three distinct
effects of a typical ground slot non-ideal return path were identified
-0.1
in both measurements and simulations. The reflected spike at the
driver and the start of the timing pushout ledge at the receiver are
-0.15
no caps
both strongly dependent on the gap width. The spike at the driver
and the duration of the timing pushout are sensitive to the gap length,
-0.2
or the return current diversion distance. Coupling to quiet lines dedriver line
pends on a combination of gap width and length, and good decoupling
two caps
-0.25
capacitor placement generally alleviates all of the above problems.
0.00E+ 1.00E- 2.00E- 3.00E- 4.00E- 5.00E- 6.00E- 7.00E- 8.00E- 9.00E- 1.00E00
10
10
10
10
10
10
10
10
10
09
Finite Difference Time Domain simulations were shown to produce
time (sec)
the same performance trends as measured TDR data, thereby equipping the designer with another tool with which to identify and remove signal integrity roadblocks. Future work includes extending
Figure 12. Measured TDR: Use of decoupling caps to mitigate
the understanding of this simple return path case to more compligap effects on signal and victim lines.
cated situations, as well as developing more accurate lumped-element models of the ground gap disruption.
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voltage (V)
-0.05
(s)
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Quantifying the Impact of a Non-Ideal Return Path
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About the authors
applications in high speed analog and digital design, EMC/EMI,
solar cell design, and wireless communication. She serves on the
Administrative Committee of IEEE Antennas and Propagation
Society. Professor Piket-May is also very active in engineering
education. Her focus is on moving towards an interactive environment where the student is in charge of the learning. She
works on undergraduate engineering design issues and incorporating research into the classroom in an interactive and meaningful way. She received a 1996 URSI Young Scientist Award
and was named a Sloan New Faculty Fellow in 1997. Professor
Piket-May was awarded an NSF CAREER award in 1997 for her
research and teaching activities. She is currently mentoring an
NSF PSFMETE Post-Doc Fellow in Engineering Education.
More information is available at http://maori.colorado.edu
Stephen H. Hall is a Senior Design
Engineer at Intel Corporation. He is currently working in the Intel Architecture
Laboratory designing high speed systems,
enabling technologies, developing simulation methodologies and performing research in the area of high speed signaling.
He has 6 years of experience in the area
of high speed digital design. Before
coming to Intel, he worked in the Special Purpose Processor Development
Group at the Mayo Foundation developing extremely high speed
optical and electrical systems.
Andrew Byers is pursuing a combined B.S./M.S. Degree in Electrical Engineering at the University of Colorado
at Boulder, focusing in computational
electromagnetic simulations and measurements. He has worked an internship
at Brookhaven National Laboratory in
New York designing digital radiation
monitor units. Two internships at Intel
have led to his current research, which
involves high-speed digital interconnect
measurements and modeling.
Melinda Piket-May (S’89 , M’92) received her BSEE Degree from the University of Illinois - Champaign in 1988
and her MSEE and Ph.D. Degrees in Electrical Engineering from Northwestern
University in 1990 and 1993, respectively.
Her work experience includes internships
at Fermi National Accelerator Lab, Naval
Research Lab, and Cray Research. She
joined the ECE Department at the University of Colorado – Boulder in 1993
where she is currently an Assistant Professor. Professor PiketMay has an active research program in computational
electromagnetics. Her work includes development of general
methods to extract information from the numerical simulation,
as well as work on higher order FDTD schemes to reduce phase
error in FDTD simulations. Her research is industrial based with
The International Journal of Microcircuits and Electronic Packaging, Volume 22, Number 3, Third Quarter 1999 (ISSN 1063-1674)
© International Microelectronics And Packaging Society
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