EE290 A: Advanced Topics in CAD
Component Based Design
of Electronic Systems
Professors Kurt Keutzer and Richard Newton
Department of Electrical Engineering and Computer
Sciences
University of California at Berkeley
Spring 1999
Kurt Keutzer & Richard Newton
1
Outline
• Raw trends
• Implication of trends - SOC/component based
design
• Challenges in component based design
• Homework 1
Kurt Keutzer & Richard Newton
2
Semiconductor Capital Investment
70
60
Asia
Europe
Japan
USA
Investment ($B)
50
40
30
20
10
0
84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 0
Projected
Year of Investment
Kurt Keutzer & Richard Newton
Source: Dataquest
3
Moore’s Law
Transistors
Microprocessors
PPC603
Pentium
10M
80486
1M
68020
68000
100K
Pentium Pro
PPC601
80386
68040
MIPS R4000
8086
10K
4004
8080
1K
100
10x/6
10x/6 years
years
10
1
1975
Kurt Keutzer & Richard Newton
1980
1985
1990
1995
4
NTRS: Microprocessor: total transistors/chip
1408M
704M
352M
176M
88M
44M
22M
11M
1
1997
1999
2001
2003
2006
2009
2012
5
Kurt Keutzer & Richard Newton
NRTS: ASIC/Microprocessor logic transistors
512M
256M
128M
64M
32M
16M
8M
4M
1
1997
1999
Total microprocessor tr.
Kurt Keutzer & Richard Newton
2001
2003
2006
Microprocessor logic tr.cm2
2009
2012
ASIC logic tr. cm2
6
NRTS: Chip Frequency (Ghz)
Clock Speed GHz.
10.0
9.0
7.0
5.0
3.0
1.0
0
1997
1999
2003
2001
2006
2009
2012
On-chip, global clock, high performance
On-chip, local clock, high-performance
7
Kurt Keutzer & Richard Newton
Evolution of the EDA Industry
Results
What’s next?
19 9 9
(Design Productivity)
19 9 2
Synthesis - Cadence, Synopsys
19 85
a
0
b
1
d
q
s
Schematic Entry - Daisy, Mentor, Valid
clk
19 78
Transistor entry - Calma, Computervision
McKinsey S-Curve
Effort
Kurt Keutzer & Richard Newton
(EDA tools effort)
8
To Design, Implement, Verify 10M transistors
Staff Months
62.5
Implementations here are
often not good enough
125
Beh
625
RTL
a
0
b
1
s
d
q
Because implementations
here are inferior/ unpredictable
6250
Power
clk
62,500
Delay
Area
9
Kurt Keutzer & Richard Newton
Why?:The Deep Sub-Micron Double-Whammy
Stolen back by Prof. Kurt Keutzer, UC Berkeley
Kurt Keutzer & Richard Newton
10
Crisis: Productivity Gap
100,000
1,000
10,000
x
x x
100
2007
10
2009
2005
2003
2001
1999
1997
21%/Yr. compound
Productivity growth rate
1995
1
1985
10
1,000
x
x
1991
x
1989
x
1993
100
Productivity
Trans./Staff - Mo.
1,000,000
10,000
1983
2.5µ
10,000,000
58%/Yr. compound
Complexity growth rate
100,000
1981
.35µ
100,000,000
Logic Tr./Chip
Tr./S.M.
1987
Logic Transistors per Chip
(K)
10,000,000
.10µ 1,000,000
Source:
SEMATECH
11
Kurt Keutzer & Richard Newton
Within a 50K - 100K Module
HDL
75 - 100% delay in gates
3.5µ - 1.0µ
1980 - 1990
.18µ - 0.1µ
1998 - 2005
This flow
should work
OK for blocks
of 50-100K
gates and
should
continue to
work OK in the
future
RTL
Synthesis
netlist
logic
optimization
Library
netlist
physical
design
• typically: size down then up
layout
Kurt Keutzer & Richard Newton
Proper sizing within flow is
absolutely required
• try: size up- then down
12
Outline
• Raw trends
• Implication of trends - SOC/component based
design
• Challenges in component based design
• Homework 1
13
Kurt Keutzer & Richard Newton
Design Paradigm: Re-useable IP
Achieve required design productivity
by assembling re-useable
blocks of intellectual property (IP)
Reused blocks
µP
DSP
3rd Party
Designers
Customer
Designs
Encryption
Semiconductor Industry
Silicon
capability
enables
integration of
entire systems
on a single die
Kurt Keutzer & Richard Newton
14
Also: Trend towards programmable Solutions
A/D
ASIC
Circuitry
D/A
P=>S Core
Today
S=>P
µP
System on a chip
Program
ROM
DMA
ASIC
µP
ASIC
ASSP
ASSP
memory
memory
µP
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
memory
FPGA-based system
memory
µP
Software running on a
(Multi-)Microprocessor
Kurt Keutzer & Richard Newton
15
Key Forces Driving Component-based Design
Exponentially increasing complexity device
complexity/capability
Productivity / Time-to-market requirements more
stringent
Synthesis from very high-level descriptions does not
provide adequate quality-of-results
Trends toward programmable solutions
Kurt Keutzer & Richard Newton
16
Next Step in the Evolution of the EDA Industry
Results
Componentbased design
19 9 9
(Design Productivity)
19 9 2
Synthesis - Cadence, Synopsys
19 85
a
0
b
1
d
q
s
Schematic Entry - Daisy, Mentor, Valid
clk
19 78
Transistor entry - Calma, Computervision
McKinsey S-Curve
Effort
Kurt Keutzer & Richard Newton
(EDA tools effort)
17
Growing list of IP Blocks
Video: MPEG, DVD, HDTV
Audio: MP3, voice recognition
Processors: CPUs, DSPs, Java
Networking: ATM, Ethernet,
ISDN, FibreChannel, SONET
Power PC core: 3.1mm2 in 0.35µ
ARM Core: 3.8 mm2 in 0.35µ
MPEG2 Decoder: ~65k gates
PCI Bus: ~8k gates
Bus: PCI, USB, IEEE 1394
Ethernet MAC: ~7k gates (soft)
Memory: SRAM, ROM, CAM
RSA Encryption: ~7k gates
Wireless: CDMA, TDMA
Communication: modems, transceivers
Coding: speech, Viterbi, Reed-Solomon
Display drivers/controllers: TFT
Other: sensors, encryption/decryption, GPS
Kurt Keutzer & Richard Newton
18
Example: Configurable Microprocessor
ALU
Pipe
I/O
Cache Timer
Register File
MMU
Tailored, RTL
uP core
Describe the
processor
attributes from
a browser-like
interface
Using the
tensilica
processor
generator,
create...
Customized
Compiler,
Assembler,
Linker,
Debugger,
Simulator
Use a
standard cell
library to
target to the
silicon
process
Kurt Keutzer & Richard Newton
19
Easily select Instruction Set attributes
Kurt Keutzer & Richard Newton
20
Set Memory and Cache attributes
Kurt Keutzer & Richard Newton
21
Outline
• Raw trends
• Implication of trends - SOC/component based
design
• Challenges in component based design
• Homework 1
Kurt Keutzer & Richard Newton
22
Challenges in Component-based Design
What is a component - what is the right quanta/granularity of capability?
Design
• How are components described?
• How are they modeled?
Implementation
• How do we trade-off between HW and SW implementations?
• In HW how do we trade off between soft, firm, and hard macros?
Verification
• How do we verify individual components?
• How do we verify component interfaces?
• How do we verify a family of parameterizable instances?
23
Kurt Keutzer & Richard Newton
What is a Component?
Component
CN
• A component is defined as any fully encapsulated behavior.
l
It is analogous to an object in object-oriented programming in
that it may have an associated state, behavior, and identity.
• We use the term component, rather than object, to stress the fact
that the implementation medium— logic, memory, software,
reconfigurable logic, or some combination— is not a factor in the
specification of the component itself.
Kurt Keutzer & Richard Newton
24
What is a Component?
Component
interface
CN
• Access to components is provided via an interface and
the interface is the only way to interact with the
component.
25
Kurt Keutzer & Richard Newton
What is a Component?
system
interface
Component
CN
environment
• A system is defined as one or more, possibly interacting,
components and their associated environment.
• The environment specifies all of the external constraints and all
possible inputs the collection of components might be asked to
respond to and so closes the system.
Kurt Keutzer & Richard Newton
26
Challenges in Component-based Design
What is a component - what is the right quanta/granularity of capability?
Design
• How are components described?
• How are they modeled?
Implementation
• How do we trade-off between HW and SW implementations?
• In HW how do we trade off between soft, firm, and hard macros?
Verification
• How do we verify individual components?
• How do we verify component interfaces?
• How do we verify a family of parameterizable instances?
Kurt Keutzer & Richard Newton
27
The Seven Views of Computer Systems
View One:
Structural Levels of a Computer System
View Two:
Levy’s Levels of Interpreters
View Three:
Packaging Levels of Integration
View Four:
A Marketplace View of Computer Classes
View Five:
An Applications/Functional View of Computer
Classes
View Six:
The Practice of Design
View Seven:
The BLAAUW Characterization of Computer
Design
Kurt Keutzer & Richard Newton
28
View One: Hierarchy of Computer Levels
Adapted from
Bell and Newell [1971]
29
Kurt Keutzer & Richard Newton
View Two: A Hierarchy of Interpreters
[Levy, 1974]
Kurt Keutzer & Richard Newton
30
Design: How are Components Described
and How are They Modeled?
Today, most “software” components are described using either assembly
language or a C model
l
l
Compiled and executed using C development environment for a target
processor ISA
Semantics defined operationally by the compiler/assembler and
“language extensions” via packages and system calls
Kurt Keutzer & Richard Newton
31
Design: How are Components Described
and How are They Modeled?
Today, most “hardware” components are described using a “C model”
l
Compiled and executed using C development environment
l
Usually an “untimed” model
l
Central issues: handling concurrency, special data types, language
subsets, language extensions via packages
In certain application-specific areas, other approaches are more common
(e.g. SPW, Cosap, Matlab)
l
Usually embodies a particular model of sequence/time and specifies a
particular path to implementation
l
New “general-purpose” approaches under development and research
l
CoWare, Felix, Polis, Ptolemy-2, JavaTime, …
Central Issue: Relationship of Description/Specification to final
implementation
Kurt Keutzer & Richard Newton
32
Design: How are Components Described
and How are They Modeled?
At lower levels of abstraction:
l Register Transfer Level (RTL): VHDL, Verilog
l Gate Level: Vendor gate library (NAND, flip-flop, etc.)schematic
l Physical: Mask layout (rectangles on layers)
Ways of delivering SOC IP:
l Hard: Detailed and fully-characterized layout in a specific
process
l Soft: RTL Level in Verilog or VHDL; “implementation
independent”
l Firm: Soft + a collection of constraints and requirements
for the implementation
Kurt Keutzer & Richard Newton
33
What is an Architecture?
m Amdahl, Blaauw, and Brooks, 1964, defined three interfaces:
Computer Architecture: "The attributes of a computer as seen by a
machine language programmer."
Implementation: "Actual hardware structure, logic design, and
datapath organization."
Realization: "Encompasses the logic technologies, packaging, and
interconnection.”
m Hennessy and Patterson
Instruction-Set Architecture: programmer-visible instruction set.
Serves as a boundary between the hardware and the software.
Organization: High-level aspects of a computer’s design, including
the memory system, bus architecture, and internal CPU design
Hardware: Used to refer to the specifics of a machine. Including
detailed logic design and packaging technology
Architecture: covers all three aspects.
Kurt Keutzer & Richard Newton
34
What is an Architecture?
m A description of the behavior of a system that is independent of its
implementation.
Ô Isomorphic to its "interface specification" (Siewiorek, Bell,
Newell, 1971)
For example:
Ô Instruction set definition of a computer
Ô Z-domain description of a filter
Ô Handshaking protocol for a bus
m May guide implementation (contain 'hints' or 'pragmas')
e.g. a particular specification may lead naturally to a serial or
parallel implementation.
35
Kurt Keutzer & Richard Newton
What is an Instruction-Set Architecture?
Example: Instruction set
Inst_A
Inst_B
Inst_C
...
Inst_C may not
follow Inst_A
Inst_A
Inst_B
Inst_C
...
Inst_C may not
follow Inst_A because
Inst_A uses a scratchpad
register that Inst_C will
over-write.
Architecture
Not architecture
Kurt Keutzer & Richard Newton
36
Specification vs. Description
Specification: Saying what I want; describes behavior in terms of
results.
e.g. ∀ A { A[i,j] ← 0}
Description: Saying how to do it; describes behavior in terms of
procedure or process.
e.g. for(i=0; i<N; i++)
for(j=0; j<M; j++)
A[i][j] = 0;
We do not have specification languages for general-purpose
digital design. For some special-purpose applications (e.g.
DSP) we do.
37
Kurt Keutzer & Richard Newton
Languages versus Models
D
Esterel
⊕
D
⊕
⊗
D
⊕
⊕
D
⊕
⊕
⊕ ⊗ ⊕ ⊕ ⊗ ⊕ ⊕
⊕
⊕
D
⊕ ⊕
⊗ ⊗
⊕ ⊕
⊕
⊗
⊕
D
⊕
D
⊕ ⊕ ⊗ ⊕ ⊕ ⊗
⊕
⊕
Synchronous
Reactive
FPGA-Based
“C, C++”
Language
VHDL
Matlab
Model of
Discrete
“FSMs”
Event
Computation
“Von Implementation
Neumann” Hard-Wired
Processor
ASIC
Media
UML
C for
RTOS
RTOS
Languages versus Models
D
Esterel
⊕
⊕
⊗
D
D
⊕
⊕
D
⊕
⊕
⊕ ⊗ ⊕ ⊕ ⊗ ⊕ ⊕
⊕
⊕
D
⊕ ⊕
⊗ ⊗
⊕ ⊕
⊕
⊗
⊕
D
⊕
D
⊕ ⊕ ⊗ ⊕ ⊕ ⊗
⊕
⊕
“C, C++”
VHDL
Discrete
Event
Synchronous
Reactive
Matlab
“FSMs”
C for
RTOS
“Von Neumann” Hard-Wired
Processor
ASIC
FPGA-Based
UML
RTOS
Languages versus Models
D
Esterel
⊕
D
⊕
⊗
D
⊕
⊕
D
⊕
⊕
⊕ ⊗ ⊕ ⊕ ⊗ ⊕ ⊕
⊕
⊕
D
⊕ ⊕
⊗ ⊗
⊕ ⊕
⊕
⊗
⊕
D
⊕
D
⊕ ⊕ ⊗ ⊕ ⊕ ⊗
⊕
⊕
“C, C++”
VHDL
Matlab
UML
(really just syntax)
Synchronous
Reactive
FPGA-Based
MLSM
SLSM
“Von Neumann” Hard-Wired
Processor
ASIC
RTOS
VHDL: The “nroff/latex” of Design
VHDL-Based
Synthesis
System
41
Encoding Information in Time & Space
In Most HDLs, "wires" are declared but
the passage of time is embedded in
the control structures.
We are caught up (once again!) with
imperative, sequential thinking and a
Von Neumann model.
We need a way of capturing both
temporal and spatial encoding in a
single, unified mathematical model.
Use a type mechanism: "τ-types"
Kurt Keutzer & Richard Newton
42
Challenges in Component-based Design
What is a component - what is the right quanta/granularity of capability?
Design
• How are components described?
• How are they modeled?
Implementation
• How do we trade-off between HW and SW implementations?
• In HW how do we trade off between soft, firm, and hard macros?
Verification
• How do we verify individual components?
• How do we verify component interfaces?
• How do we verify a family of parameterizable instances?
43
Kurt Keutzer & Richard Newton
Architecture for SOC
Application
Application API
SOC Block Integration Layer
Coarse-Grain API (thread level)
Hardware Interface (electrical)
Kurt Keutzer & Richard Newton
Multi-User
Interface
Vector Stage
Vector Stage
Vector Stage
Vector Stage
General-Purpose
Processor
with BIOS
and OS
Vector Stage
Fine-Grain API
Vector Processor
Interface
44
A Vision: Design System 2010
Specification
Threader
Thread
PDA Budget
Constraints: Real time,
PDA, Precision
Communication Complexity
(1)Threads mapped
to processing units
Thread Optimization
& Implementation
CU
Processing Unit
Microarchitectural
Optimization
FU FU FU FU
FU
MemoryFU
Datapath
MIL-IP
COTS Silicon
Logic
(2) Functional units and
coprocessors allocated
to processing unit
(3) Functional unit
implemented as
hardware/”software”
45
Kurt Keutzer & Richard Newton
System-On-A-Chip: 1998
Embedded µP Core
Kurt Keutzer & Richard Newton
90K CBA gates
46
Transition to Extensive Use of Regular Structures
Intel 4004 (‘71)
Intel 8080
Intel 8286
Intel 8085
Intel 8486
Kurt Keutzer & Richard Newton
47
Move Towards Regularity and Programmability
Intel 4004 (‘71)
Intel 8080
Intel 8286
Regular logic
Kurt Keutzer & Richard Newton
Intel 8085
Intel 8486
Programmable structure
Other (random logic, etc.)
48
Particular Function (e.g. MPEG)
Evaluations/W
or
ess
c
o
pr
GP
X
or
ess
c
o
pr
P
G
IC
AS
Real-time
requirement
Non real-time
Time
49
Kurt Keutzer & Richard Newton
Example of System Behavior
Mem
13
Rate
Buffer
12
Cable
Sensor
Synch
Control
4
Satellite Dish
Front
End 1
User/Sys
Control
3
Transport
Decode 2
Rate
Buffer
5
Rate
Buffer
9
Video
Decode 6
Audio
Decode/
Output 10
Mem
11
remote
Frame
Buffer
7
Video
Output 8
monitor
speakers
From Alberto Sangiovanni-Vincentelli
Kurt Keutzer & Richard Newton
50
IP-Based Design of Behavior
System Integration
Communication Protocol
User Interface
Written in C
Mem
13
Test-bench
User/Sys
Control
3
Rate
Buffer
12
Sensor
Synch
Control
4
Satellite Dish
Front
End 1
Transport
Decode 2
Rate
Buffer
5
remote
Frame
Buffer
7
Video
Decode 6
Rate
Buffer
9
Audio
Decode/
Output 10
Cable
monitor
Mem
11
Base-band Processing
(Matlab,SPW)
Transport Decode
Written in C
Video
Output 8
speakers
Decoding Algorithms
(Matlab possibly coming from a library)
From Alberto Sangiovanni-Vincentelli
51
Kurt Keutzer & Richard Newton
IP-Based Design of Implementation
Which Bus? PI?
AMBA?
Dedicated Bus for
DSP?
DSP
Processor
External
I/O
MPEG
Peripheral
Audio
Decode
Do I need a dedicated Audio Decoder?
Can decode be done on Micro-controller?
Processor Bus
Can I Buy
an MPEG2
Processor?
Which One?
Which DSP
Processor? C50?
Can DSP be done on
Micro-controller?
DSP RAM
Which
Micro-controller?
ARM? HC11?
Control
Processor
System
RAM
How fast will my
User Interface
Software run? How
Much can I fit on my
Micro-controller?
From Alberto Sangiovanni-Vincentelli
Kurt Keutzer & Richard Newton
52
Separate Behavior from Architecture
Implementation Architecture
System Behavior
l
Functional Specification
of System.
Hardware and Software
l
Optimized Computer
No notion of hardware or
software!
Mem
13
Rate
Buffer
12
User/Sys
Control
3
Transport
Decode 2
Rate
Buffer
5
Rate
Buffer
9
Video
Decode 6
MPEG
Frame
Buffer
7
DSP
Processor
External
I/O
Sensor
Synch
Control
4
Front
End 1
l
Video
Output 8
Peripheral
Processor Bus
l
Audio
Decode
Audio
Decode/
Output 10
DSP RAM
Control
Processor
System
RAM
Mem
11
From Alberto Sangiovanni-Vincentelli
53
Kurt Keutzer & Richard Newton
Map Between Behavior and Architecture
Transport Decode Implemented
as Software Task Running
on Micro-controller
Rate
Buffer
12
Sensor
Communication
External
Over Bus
I/O
Synch
Control
4
Front
End 1
Transport
Decode 2
Rate
Buffer
5
Rate
Buffer
9
Video
Decode 6
Audio
Decode/
Output 10
MPEG
Frame
Buffer
7
Video
Output 8
Peripheral
Audio
Decode
DSP
Processor
Processor Bus
Mem
13
User/Sys
Control
3
DSP RAM
Control
Processor
System
RAM
Mem
11
Audio Decode Behavior
Implemented on
Dedicated Hardware
From Alberto Sangiovanni-Vincentelli
Kurt Keutzer & Richard Newton
54
Basic Principles
Design Methodology general enough to capture most of application domains
Existing methods should be modeled to allow transition
Powerful policies to allow fast development of complex systems with correctness
guarantees
Policies supported by verification and synthesis tools both at the abstract and at
the physical level
Constraint-based Approach to generate appropriate guiding principles for
Subsequent Implementation steps
Validation of ideas can only come by applying it to “real” designs
From Alberto Sangiovanni-Vincentelli
55
Kurt Keutzer & Richard Newton
System Level Design
Design Methodology:
l
Top Down Aspect:
l
l
l
l
l
Formalization: precise unambiguous semantics
Abstraction: capture the desired system details
Decomposition: partitioning the system behavior into simpler
behaviors
Successive Refinements: refine the abstraction level down to the
implementation by filling in details and passing constraints
Bottom Up Aspect:
l
l
IP Re-use (even at the algorithmic and functional level)
Components of architecture from pre-existing library
From Alberto Sangiovanni-Vincentelli
Kurt Keutzer & Richard Newton
56
System Design
Architecture
Synthesis
Function
Verification
Mapping
HW
SW
From Alberto Sangiovanni-Vincentelli
57
Kurt Keutzer & Richard Newton
Estimation and Modeling
SW
library
Processor
Model
Hardware Path
Behavioral
Function
HW
library
Mapping
Model
Library
Code
Generation
Software Path
Model
Library
Network of
Modules
ARM8
Combines Behavioral Parameters and Architectural Models
From Alberto Sangiovanni-Vincentelli
Kurt Keutzer & Richard Newton
58
Communication Refinement
Separate Function of blocks from inter-block
Communication
IP Block
Protocol Up
Converter
Protocol Down
Converter
Substitute lower-level detail for communications
behavior
IP Block With
Generic Data
Transfer
IP Block
IP Block With
Generic Data
Transfer
From Alberto Sangiovanni-Vincentelli
59
Kurt Keutzer & Richard Newton
Communication Refinement
Standard interfaces constitute the backbone of an IP market: abstract form the concerns of
hardware implementation (multi-target VC), abstract from the concerns of a particular bus
(bus-independent VC)
system transaction, «ANY» data structure (e.g. video line)
hardware or software
«ANY BUS» operation (data, address...)
VSI-Alliance OCB Group.
Virtual Component Interface (VCI)
Physical Bus (e.g.
PIBus)
fixed bus-width,
detailed protocol
Communication Interface (e.g.
bounded FIFO)
Bus Wrapper
From Alberto Sangiovanni-Vincentelli
Kurt Keutzer & Richard Newton
60
IP Integration
Mechanical
Deployment
Inertial
Sensors
Imager
Mechanical
Pointing
D/A
(3 x 100 Hz)
A/D
(9 x 1Khz)
A/D
(20 x MHz+)
D/A
(3 x 100 Hz)
Integrated Sensor System
Signal
Conditioning
Image
Formation
Data Buffers
Data Buffers
Position
Processing
Wireless Control
Hello,
Hello,IItalk
talk
Myrinet
Myrinet
and
andPCI
PCI
ATR
4 mByte/sec
System Processors
Hi,
Hi,IItalk
talk
PCI
PCIand
and
Hippi
Hippi
Image Display
User Controls
nXn HPC
RAMBUS
DSP
PCI
My System
RAM
Normalizer
IP Library
CODEC
DSP
uCntrl
SRAM
A/D
nXn HPC
Normalizer
IR Imager
SINCGARS
GPS/IMU
MPEG-4
Crossbar
Crossbar
uCntrl
A/D
Logic
OK, Lets
talk PCI
GSM/PCS
CODEC
IR Imager
SINCGARS
Kurt Keutzer & Richard Newton
61
Challenges in Component-based Design
What is a component - what is the right quanta/granularity of capability?
Design
• How are components described?
• How are they modeled?
Implementation
• How do we trade-off between HW and SW implementations?
• In HW how do we trade off between soft, firm, and hard macros?
Verification
• How do we verify individual components?
• How do we verify component interfaces?
• How do we verify a family of parameterizable instances?
Kurt Keutzer & Richard Newton
62
System-on-a-Chip IP Creation and
Analysis Flow
Architectural Design
Digital Control
Memory
Datapath
RTL
Functional
Description
Memory Behavior
Model
Logic
Synthesis
Logic Design
& Simulation
Decoder/
Periphery Design
Logic
Verification
Performance
Optimization
Core Cell
Sense Amp
Analog
Analog Functional
Model
Analog Circuit
Design & Sim.
Datapath
Compiler
Custom
Layout
Std Cell
P&R
Chip Assembly
Block P&R
DRC/LVS/Extraction
Parasitic Reduction
Final Power &
Reliability Check
Full Chip
Timing Verification
Full Chip
Func Simulation
63
Kurt Keutzer & Richard Newton
System-on-a-Chip Design Flow
Architectural Design
Digital Control
Memory
Datapath
RTL
Functional
Description
Logic
Synthesis
Logic Design
& Simulation
Logic
Verification
Performance
Optimization
Datapath
Compiler
Global
Timing/Power
Memory Behavior
Model
Analog
Analog Functional
Model
Decoder/
Periphery Design
Block
Timing/Power
Core Cell
Sense Amp
Analog Circuit
Design & Sim.
Custom
Layout
Physical
Floorplan
Std Cell
P&R
Chip Assembly
Block P&R
DRC/LVS/Extraction
Parasitic Reduction
Final Power &
Reliability Check
Kurt Keutzer & Richard Newton
Full Chip
Timing Verification
Static Timing
Models
Functional
Models
Full Chip
Func Simulation
64
System-on-a-Chip Integration Flow
Planning
Physical
Manufacturing
Reliability
System Design
Power
Noise
System
Hardware/Software
Partitioning
Timing
Test
System
Physical
Floorplan
System Verification
System Abstraction
Functional
Power Models
Timing Models
Bus Functional Models
Models
Software
65
Kurt Keutzer & Richard Newton
SoC Model Views
Full Function Cycle
Timing Model
Full-Function with Timing
Software Design
Bus Functional
Physical Design
re
ctu
hite
Arc
Power Design
Set
Manufacturing Design
Testbench/Tests
Instr
uctio
n
Automatic
Model
Creation
Integration
Timing Design
Core Design
Core Views
Functional Design
Core Creation
Test Model
Post-Design
Remodeling
Kurt Keutzer & Richard Newton
Floorplan/Phy Model
Electrical Rule Model
Place & Route
and
Chip Finishing
66
Berkeley Wireless Research Center (BWRC)
Conventional cellular
phone solution
• Research into technology
and design methodologies
for CMOS single chip radios
• Exploring future applications
of wireless technology, 4th
generation and beyond
Kurt Keutzer & Richard Newton
67
BWRC Long-Term Research Drivers
Universal Radios for 4th Generation
l
Two generations beyond present digital cellular
l
Low energy, high-performance programmable computing platform
l
Systems and circuits focus to resolve rules of engagement at the air
interface and to allow for peaceful co-existence
Picoradios
l
Ultra-low power, low cost, embedded CMOS radio’s ( < 1 mW)
l
EDA systems for rapid, optimized implementation
Ultra-High Bandwidth Millimeter Radios
l
Scaled CMOS solutions for 20 - 60 GHz operation
l
Architectures and Device modeling
Kurt Keutzer & Richard Newton
68
Homework 1: JPEG as a Component
You are to evaluate/estimate one of a number of possible
implementations of the JPEG specification (description?)
provided on the course web page.
You will estimate, as accurately as you can and with as much
justification as you can:
l
Frames/second
l
Frames/mW
l
Production cost of your solution
You may work in groups of one or two
Your results should be submitted online by Friday, 1/29, 5pm
We will compare results and assumptions in Week 3
69
Kurt Keutzer & Richard Newton
Scenario 2 Implications: Power as the Driver
We believe power always has been the driver!
1000
MIPS/mW
100
10
Four orders
of magnitude
1
0.1
0.01
0.001
Pentium
0.35µm
StrongARM
0.35µm
TI DSP
0.25µm
Dedicated
1µm
Source: R. Brodersen, Berkeley
70
Challenges in Component-based Design
What is a component - what is the right quanta/granularity of capability?
Design
• How are components described?
• How are they modeled?
Implementation
• How do we trade-off between HW and SW implementations?
• In HW how do we trade off between soft, firm, and hard macros?
Verification
• How do we verify individual components?
• How do we verify component interfaces?
• How do we verify a family of parameterizable instances?
Kurt Keutzer & Richard Newton
71