Lecture 13
Digital Circuits (III)
CMOS CIRCUITS
Outline
• CMOS Inverter: Propagation Delay
• CMOS Inverter: Power Dissipation
• CMOS: Static Logic Gates
Reading Assignment:
Howe and Sodini; Chapter 5, Sections 5.4 & 5.5
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1. Complementary MOS (CMOS) Inverter
Circuit schematic:
VDD
VIN
VOUT
CL
Basic Operation:
•
VIN = 0 ⇒ VOUT = VDD
– VGSn = 0 ( < VTn )
⇒
– VSGp = VDD ( > - VTp ) ⇒
•
NMOS OFF
PMOS ON
VIN = VDD ⇒ VOUT = 0
– VGSn = VDD ( > VTn ) ⇒
– VSGp = 0 ( < - VTp ) ⇒
NMOS ON
PMOS OFF
No power consumption while idle in any logic state!
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2. CMOS inverter: Propagation delay
Inverter propagation delay: time delay between input
and output signals; figure of merit of logic speed.
Typical propagation delays: < 100 ps.
Complex logic system has 10-50 propagation delays
per clock cycle.
Estimation of tp: use square-wave at input
VIN
VDD
tCYCLE
0
t
tPHL
VOUT
tPLH
VDD
50%
tCYCLE
0
t
Average propagation delay:
tp =
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(t PHL + t PLH )
2
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CMOS inverter:
Propagation delay high-to-low
VDD
VOUT:
HI LO
VIN:
LO HI
CL
VDD
VIN=0
VDD
VDD
VOUT=VDD
VIN=VDD
VOUT=VDD
CL
t=0-
VOUT=0
VIN=VDD
CL
CL
t=0+
t->infty
During early phases of discharge, NMOS is saturated
and PMOS is cut-off.
Time to discharge half of charge stored in CL:.
1
−
charge on C L @t = 0
t pHL ≈ 2
NMOS discharge current
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CMOS inverter:
Propagation delay high-to-low (contd.)
Charge in CL at t=0-:
(
QL t = 0
−
)= C
L VDD
Discharge Current (NMOS in saturation):
I Dn =
Then:
t PHL ≈
Wn
2
µ nCox (VDD − VTn )
2Ln
CL VDD
Wn
2
µn Cox (VDD − VTn )
Ln
Graphical Interpretation
ID
VOUT
t = 0+
VIN = VOH
t = tPHL
VOH
t = 0−
VIN = 0V
VOH
2
0
0
VOH
2
VOH
VOUT
0
0
(a)
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t
tPHL
(b)
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CMOS inverter:
Propagation delay low-to-high
VDD
VOUT:
LO HI
VIN:
HI LO
CL
VDD
VDD
VDD
VOUT=0
VIN=VDD
VIN=0
VOUT=0
CL
t=0-
VOUT=VDD
VIN=0
CL
CL
t=0+
t->infty
During early phases of discharge, PMOS is saturated
and NMOS is cut-off.
Time to charge to half of final charge on CL:.
1
charge on C L @t = ∞
t PLH ≈ 2
PMOS charge current
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CMOS inverter:
Propagation delay high-to-low (contd.)
Charge in CL at t=∞ :
Q L (t = ∞) = CL VDD
Charge Current (PMOS in saturation):
Wp
− IDp =
µ pCox VDD + VTp
2Lp
(
)
2
Then:
t PLH ≈
CL VDD
(
Wp
µp Cox VDD + VTp
Lp
)
2
Key dependencies of propagation delay:
•
VDD ↑ ⇒ tp ↓
– Reason: VDD ↑ ⇒ Q(CL ) ↑, but ID goes as square↑
– Trade-off: VDD ↑ ⇒ more power consumed.
•
L ↓ ⇒ tp ↓
– Reason: L ↓ ⇒ ID ↑
– Trade-off: manufacturing cost!
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Components of load capacitance CL:
•
•
•
Following logic gates: must add capacitance of
each gate of every transistor the output is connected
to.
Interconnect wires that connects output to input of
following logic gates
Own drain-to-body capacitances
CL = CG + Cwire + CDBn + CDBp
VDD
W
L p2
VDD
VDD
2
W
L n2
W
L p1
VIN
+
CL
VOUT
VIN
1
VDD
W
L n1
W
L p3
−
3
W
L n3
(a)
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(b)
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Gate Capacitance of Next Stage
• Estimation of the input capacitance:
• n- and p-channel transistors in the next stage
switch from triode through saturation to cutoff
during a high-low or low-high transition
• Requires nonlinear charge storage elements to
accurately model
• Hand Calculation use a rough estimate for an inverter
Cin = Cox (WL) p + C ox (WL)n
CG for example circuit
C G = C ox (WL) p2 + Cox (WL)n2 +
Cox (WL) p3 + Cox (WL)n3
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Interconnect Capacitance
;;
• “Wires” consist of metal lines connecting the output of
the inverter to the input of the next stage
;;
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;
;
metal interconnect
(width Wm, length Lm)
polysilicon
gate
p+
0.6 µm deposited oxide
0.5 µm thermal oxide
p
(grounded)
gate oxide
• The p+ layer (i.e., heavily doped with acceptors) under
the thick thermal oxide (500 nm = 0.5 mm) and deposited
oxide (600 nm = 0.6 mm) depletes only slightly when
positive voltages appear on the metal line, so the
capacitance is approximately the oxide capacitance:
Cwire = Cthickox (Wm*Lm)
where the oxide thickness = 500 nm + 600 nm = 1.1 µm.
For large digital systems, the parasitic wiring capacitance
can dominate the load capacitance
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Parasitic Capacitance-Drain/Bulk
Depletion
gate oxide
n+ polysilicon gate
source
interconnect
drain
interconnect
bulk
interconnect
;
;;;;
;;;;
;;
;;;;
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;;;
;;;;
;;;;
deposited
oxide
;;
;;
;;
;;
;
;;
;
;
L
field
oxide
n+ drain diffusion
Ldiff
n+ source diffusion
p+
[ p-type ]
(a )
;;;;;;;;
;
;
;;;
; ; ;;;;;;;;;;;;;;
;;;;; ;;;;;;;;;;;;
;;;;; ; ; ; ; ; ;
;;;;; ; ; ; ; ;
;
;
;
;
;
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;
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;
;
;
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;
;;;;;;;;;;;;
;
;
;
;
;
;
active area (thin
oxide area)
gate contact
gate
interconnect
polysilicon gate
contact
n+ polysilicon gate
A
metal
interconnect
source contacts
W
bulk
contact
source
interconnect
drain
interconnect
L
drain
contacts
edge of
active area
(b)
L
W
Ldiff
(c)
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Calculation of Parasitic Drain/Bulk Junction
Depletion Capacitance
• Depletion qJ(vD) is non-linear --> take the worst case and use the zero-
bias capacitance Cjo as a linear charge-storage element during the transient.
• “Bottom” of depletion regions of the inverter’s drain diffusions
contribute a depletion capacitance:
CJBOT = CJn(WnLdiffn) + CJp(WpLdiffp)
Where: CJn and CJp are the zero-bias bottom capacitance (fF/µm2) for the
n-channel and p-channel MOSFET drain-bulk junction, respectively.
Typical numbers: CJn and CJp are about 0.2 fF/µm2
• “Sidewall” of depletion regions of the inverter’s drain diffusions make an
additional contribution:
CJSW = (Wn + 2Ldiffn)CJSWn + (Wp + 2Ldiffp)CJSWp
Where: CJSWn and CJSWp are the zero-bias sidewall capacitance (F/µm) for
the n-channel and p-channel MOSFET drain-bulk junction, respectively.
Typical numbers: CJSWn and CJSWp are about 0.5 fF/µm
The sum of CJBOT and CJSW is the total depletion capacitance, CDB
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Power Dissipation
• Energy from power supply needed to charge up the capacitor:
Echarg e = ∫ VDD i(t)dt = VDD Q = VDD 2 C L
• Energy stored in capacitor:
Estore = 1/ 2C LVDD 2
• Energy lost in p-channel MOSFET during charging:
Ediss = Echarge − Estore = 1/ 2CL VDD 2
•During discharge the n-channel MOSFET dissipates an
identical amount of energy.
•If the charge/discharge cycle is repeated f times/second,
where f is the clock frequency, the dynamic power
dissipation is:
P = 2E diss * f = C L VDD 2 f
In practice many gates do not change state every clock
cycle which lowers the power dissipation.
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CMOS Static Logic Gates
VDD
M4
A
M3
B
+
M2 VOUT
_
M1 B
A
(a)
VDD
M3
A
M4
A
B
+
B
M2
VOUT
_
M1
(b)
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CMOS NAND Gate
I-V Characteristics of n-channel devices
VDD
VM
M4
M3
ID
VM
VM
VGS1 = VM
M2
+
M1 VDS1
VGS2 = VM − VDS1
ID1 = ID2
;;;
;;;
;;
;;
−
VDS
(a)
;;
;;
source
(b)
VM
VM
gate
gate
M1
M2
n+
L1
L2
(a)
;;
;;
drain
VM
;;
source
VM
gate
;;
gate
M1
M2
L1
L2
drain
(b)
• Effective length of two n-channel devices is 2Ln
• Kneff = kn1/2 = kn2/2 Recall kn = W/LµnCox
•Effective width of two p-channel devices is 2Wp BUT
worst case only one device is on
• Kpeff = kp3 = kp4
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Calculation of static and transient
performance for NAND Gate
• kpeff
= kneff is desirable for equal
propagation delays and symmetrical transfer
characteristics
• Recall µn = 2µp
• Therefore (W/L)n = (W/L)p
for 2-input NAND gate
•In general for an M-input NAND Gate
⎛ W⎞
M ⎛ W⎞
⎜ ⎟ = ⎜ ⎟
⎝ L ⎠n 2 ⎝ L ⎠ p
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What did we learn today?
Summary of Key Concepts
Key features of CMOS inverter:
•
•
No current between power supply and ground while
inverter is idle in any logic state
“rail-to-rail” logic
– Logic levels are 0 and VDD.
•
High |Av| around the logic threshold
– ⇒ Good noise margins.
CMOS inverter logic threshold and noise margins
engineered through Wn/Ln and Wp/Lp.
Key dependencies of propagation delay:
•
•
VDD ↑ ⇒ tp ↓
L ↓ ⇒ tp ↓
Power dissipation CV2f
Sizing static gates
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