PST-10-A-1 PCB Guidelines
AN0029 rev. 2
Introduction
The PST-10-A-1 requires proper selection of the external components in order to meet
optimum performance. This document describes the selection of external components and layout
of the PCB for optimum performance.
Figure 1 shows the schematic of the PST-10-A-1 evaluation PCB. The performance of
the chip relies on using the proper external components. Figure 2 shows the layout of the
PST-10-A-1 evaluation PCB.
DC-Blocking Capacitor
A DC blocking capacitor is required at the RF input. The DC blocking capacitor, C1, will
limit the frequency of operation. You need to use a capacitor that will provide low insertion loss
and good VSWR over the intended frequency range. For broadband performance, we
recommend the ATC 530B broadband capacitor. This is a 10000 nF capacitor that provides a low
insertion loss from low frequency to 40 GHz.
De-coupling Capacitors
The internal thermistors that sense the RF power, need a solid RF ground at pin 2. This is
accomplished by placing a low capacitance value immediately near the chip and a larger value in
parallel. On the PST-10-A-1 evaluation PCB, there is a 68 pF 0402 capacitor near the chip. A
similar capacitor arrangement is needed on pin 6. These capacitors provide de-coupling of the
bias line. C3 and C5 are not used.
Output LP Filter
The Power Output and the Temp Comp Output are DC voltages. However, they will each
have a small RF ripple. This ripple can be removed by using an RC low pass filter. The RC
combinations of R2/C6 and R3/C7 on the evaluation PCB provide a 42 kHz low pass filter. This
RC filter can be adjusted based on your needs. However, a larger RC time constant will slow
down the response of the output voltage to a change in RF input power.
PCB Layout
As with any RF component, a properly designed PCB is required for optimum
performance. The PCB trace into the RF_In pin of the PST-10-A-1 should be a good 50 ohm
microstrip (or CPW) line. There needs to be a handful of ground vias close to each ground pin of
the device (pins 1 and 3). Also, each de-coupling capacitor should have a via very close to the
ground pad of the capacitor.
3/30/2011
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The information contained herein is considered company confidential and shall not be disclosed to any outside party in part or in
whole without permission from a qualified executive of Florida RF Labs Inc. and EMC Technology Inc.
PST-10-A-1 PCB Guidelines
AN0029 rev. 2
Figure 1. PST-10-A-1, Schematic of Evaluation PCB
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3/30/2011
The information contained herein is considered company confidential and shall not be disclosed to any outside party in part or in
whole without permission from a qualified executive of Florida RF Labs Inc. and EMC Technology Inc.
PST-10-A-1 PCB Guidelines
AN0029 rev. 2
Figure 2. PST-10-A-1, Evaluation PCB Layout
3 of 3
3/30/2011
The information contained herein is considered company confidential and shall not be disclosed to any outside party in part or in
whole without permission from a qualified executive of Florida RF Labs Inc. and EMC Technology Inc.