3. Basic building blocks
Analog Design for CMOS VLSI Systems
Franco Maloberti
Inverter with active load
It is the simplest gain stage. The dc gain is given by the
slope of the transfer characteristics.
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
1
Small signal analysis
C1 = Cgs1 + Cgs1,ov
C2 = Cgd1 + Cgd1,ov
+
C3 = Cdb1 + Cdb2 + Cgd 2 + Cgd 2,ov + CL
Vout
−gm1
Av =
=
Vin
gds1 + gds2
At low frequency:
with
W
gm = 2µCox
ID
L
€
gds = λID
€Analog Design for CMOS VLSI Systems
Franco Maloberti
€
€
Av = −
W 
2µCox  
 L 1
(λ
n
+ λp
)
ID
3. Basic building blocks
2
The dc gain increases as the square root of the bias
current is decreases. This holds until the devices enter the
subthreshold region
In subthreshold the dc gain becomes independent of the
biasing current:
ID
1
gm =
Av = −
kT
kT
n
λn + λp n
q
q
(
Analog Design for CMOS VLSI Systems
Franco Maloberti
€
)
3. Basic building blocks
3
€
At high frequency:
 Miller's theorem is applied to C2
 The output total capacitance is C2 + C3
 The output resistance is 1 / (gds1 + gds2)
 The transfer function has one pole
(
€
)
λn + λp ID
gds1 + gds2
ωp =
=
C2 + C3
C2 + C3
 The unity gain frequency increases as the square root of
the bias current.
W
2µ1Cox
1
1
g
1
€
L I
m1
fT =
ω p Av (0) =
=
D
2π
2π C2 + C3 2π C2 + C3
 Due to the Miller's theorem the input capacitance
becomes: Cin = C1 + C2(1 – Av), if |Av| >> 1 it can be a
significant load for the stage driving it.
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
4
Example
Simulate an inverter with active load (VDD = 5 V) as the
following figure with BSIM3 Models. Find the dc gain and
unity gain frequency.
The achieved gain is about 47 dB, the unity gain frequency is around
500 MHz, and the phase margin is 87 degrees.
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
5
Cascode
The cascode gain stage is used to attenuate the Miller
effect on node 1.
VB > Vsat,1 + VGS2 = Vsat,1 + VTh,n + Vsat,2 =
I1
I1
= VTh,n +
+
W 
W 
2µnCox  
2µnCox  
 L 1
 L 2
The bias voltage VB keeps
M1 in the saturation region.
€
VB < Vout,min −Vsat,2 + VGS2 = Vout,min + VTh,n
Analog Design for CMOS VLSI Systems
Franco Maloberti
€
3. Basic building blocks
6
Small signal analysis
C1 = Cgs1 + Cgs1,ov
C2 = Cgd1 + Cgd1,ov
C3 = Cgd 2 + Cgd 2,ov + Cgd 3 + Cgd 3,ov + Cdb2 + Cdb 3 + CL
C4 = Cgs2 + Cgs2,ov + Cdb1 + Csb2
For low frequency, neglecting gds1 and gds2:
gm1vin = −gm2v1 = −gds3vout
Vout
gm1
Av =
=−
Vin
gds3
V1
gm1
A1 =
=−
Vin
gm2
The Miller effect is significantly reduced if gm1 ≈ gm2.
Analog Design for CMOS VLSI Systems
Franco Maloberti
€
€
3. Basic building blocks
7
At high frequency:
The circuit has two nodes: the output and node 1.
 The capacitance at the output is C3
 The output impedance is 1 / gds3 (neglecting the
impedance at the drain of M2)
 The capacitance at the node 1 is (C2 + C4)
 The impedance at the node 1 is 1 / gm2
 The pole associated to the output node is:
1
1
1 gds3
fp,out =
=
2π τ out 2π C3
 The pole associated to the node 1 is:
2
1 1
1
gm2
/ζ
fp,1 =
=
2π τ1 2π gm1(C2 + C4 ) + gm2C2
€
where ζ = 1 + rds3 / rds2
Analog Design for CMOS VLSI Systems
Franco Maloberti
€
3. Basic building blocks
8
€
since gm >> gds, fp,out is dominant.
 The gain-bandwidth product is:
1 gm1
fT = fp,dom Av =
2π C3
 If a good phase margin is needed, it must be:
gm1
gm2 / ζ
<
C3 (C€2 + C4 ) + C2 gm1 / gm2
This condition can be fulfilled
by increasing CL.
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
9
Impedance at the drain of M2
ix
i x + gm2vs2
vx =
+
gds1
gds2
ix
vs2 =
gds1
 g 
vx
rd 2 =
= rds1 + rds2 1+ m2  ≅ rds1gm2 rds2
ix
€  gds1 
€
Analog Design for CMOS VLSI Systems
Franco Maloberti
€
3. Basic building blocks
10
Impedance at the node 1,r1:
v x = rds3i x + rds2 (i x − gm2v x )
€
1  rds3  ζ
rs2 =
1+
=
gm2  rds2  gm2
Analog Design for CMOS VLSI Systems
Franco Maloberti
€
3. Basic building blocks
11
Cascode with cascode load
Transconductance gain stages.
The gain is increased by increasing gm or rout.
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
12
In the improved version the transconductance of M1 is
increased by the factor:
IM 4 + IM5
IM 4
VB1 and VB2 must keep M1
and M4 out the triode region
€
VB1 > Vsat,1 + VGS2
VB2 < VDD – Vsat,4 – VGS3
The figure plots the folded
structure useful if we need to
rise the voltage of the source
of M1.
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
13
Small signal analysis
The output impedance is (conventional version):
rout
r
(
=
g r
ds1 m2 ds2
)( r
g r
ds 4 m3 ds3
)
rds1gm2 rds2 + rds 4gm3 rds3
(for the improved and folded version rds1 must be replaced
with rds1 // rds5)
The dc€gain is:
rds1gm2 rds2 rds 4gm3 rds3
2
1
Av = −gm1
≅ gm rds
rds1gm2 rds2 + rds 4gm3 rds3 2
(
)(
)
(
)
The circuit has three nodes:
 output node
€ source of M2
 source of M3
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
14
€
The transfer function will have three poles. The dominant
one is the output pole
fp,out
1
1
=
2π routCout
1
1
f2 =
2π r2C2
1
1
f3 =
2π r3C3
Cout, C2, C3 capacitances incident on nodes 1, 2, 3.
At low frequency:
rds1gm2 rds2 rds 4gm3 rds3
€ rout =
€
rds1gm2 rds2 + rds 4gm3 rds3
1  rds 4gm3 rds3 
r2 =
1+
 // rds1
gm2 
rds2

€
1  rds1gm2 rds2 
r3 =
1+
 // rds 4
gm3 
rds3 
€
rout >> r2 , r3
(
Analog Design for CMOS VLSI Systems
Franco Maloberti
€
€
)(
)
3. Basic building blocks
15
At high frequency:
1
r2 ≅
gm2
1
r3 ≅
gm3
Output swing:
The output swing is limited by the conditions for which one
€ brought out of saturation
of€the transistors of the stage is
Vout,max = VB2 + VGS3 −Vsat3
Vout,min = VB1 + VGS2 −Vsat2
VB1 and V
€B2 must keep M1, M4, and M5 out of the triode
region.
€
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
16
Example
Simulate the folded cascode amplifier, shown in the following figure,
with VDD = 3.5 V. Use the BSIM3V2 models to find the gain and the
phase from input to output and from input to node 2.
We observe that the gain and the phase plots of the output show a 20
dB roll-off with a good phase margin (60 degrees). The low frequency
gain is 77 dB and the unity gain frequency is around 80 MHz. The
behavior of the gain from the input to node 2 is interesting: above the
dominant pole, it holds 14 dB, just 2 dB more than the expected value
gm1/gm2. At low freq. goes to 34 dB.
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
17
Differential stage
M1, M2 in saturation with (W/L)1 = (W/L)2
2
µCox W 
µCox W 
I1 =
I2 =
  VGS1 −VTh
  VGS2 −VTh
2  L 1
2  L 2
(
)
(
)
2
assume:
VGS1 = VGS0 +
vin
2€
VGS2 = VGS0 −
Analog Design for CMOS VLSI Systems
Franco Maloberti
€
vin
2
3. Basic building blocks
18
€
€
The output variable is the differential current:
µCox  W 
ΔI = I1 − I2 =
  vin (VGS0 −VTh )
2  L 1
since the bias current can be expressed as:
µCox  W 
ISS = I1 + I2 =
  VGS0 −VTh
€
2  L 1
(
)
2
W 
it results: ΔI = vin µCox   ISS for small signals: Δi = vin gm
 L 1
with€a common mode signal:
€
gmvCM
vin
id
iCM =
≅
CMRR =
≅ 2gm ri
€
1+ 2gm r1 2r1
iCM
Analog Design for CMOS VLSI Systems
Franco Maloberti
€
3. Basic building blocks
19
Example
W 
Verify the equation ΔI = vin µCox   ISS
 L 1
Consider an n-channel differential pair with (W/L)=100 and ISS=100 µA.
€
The transconductance transfer function is fairly linear over a wide
range of the input signal. It starts to saturate only when the input signal
approaches the overdrive voltage of the differential pair (75 mV).
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
20
Source follower
Used as buffer or as dc-level shifter
at low frequency:
(g
hence:
vout
gm1
Av =
=
vin
gm1 + gds1 + gds2 + gmb1
€
ds1
Analog Design for CMOS VLSI Systems
Franco Maloberti
)
+ gds2 vout + gmb1vout − gm1v gs1 = 0
3. Basic building blocks
21
If gm1 >> gds1 + gds2 + gmb1 then Av ≈ 1
C1
at high frequency:
Av (s) ≅
C1 + Cout
where:
Cout = CL + Cgd2 + Cgd2ov + Cdb2 + Csb1
C1 = Cgs1 + Cgs1ov
€
The output impedance
is obtained by applying a test
source vx at the output node.
ix = (gds1 + gds2 + gmb1 + gm1) vx
hence:
1
1
rout =
≅
gm1 + gds1 + gds2 + gmb1 gm1
The output is not symmetrical. For n-channel input device
Vout-max = VDD – VGS1
Vout-min = Vsat2
€
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
22
Example
Simulate the large signal behavior and derive the dc small signal
voltage gain. IB = 0.1 mA and VDD = 3.3 V.
The output voltage, practically, follows the input shifted by VGS.
However due to the body effect, the value of VGS is not constant; it rises
from 713 mV to 1.13 V. Therefore the input-output characteristic is not
1 but 0.81. The figure shows also the dc gain: its value ranges from
0.74 to 0.86 quite well match as theoretical results.
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
23
Level shifter
Essential for NMOS circuits, useful for CMOS circuits
 High-impedance level shift
 Low-impedance, or "battery", level shift
High input impedances:
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
24
ΔV = VGS =
2L
I + VTh = Vov + VTh
kW
 Body effect neglected
 Threshold voltage variation effect
€ ≈ ± 150 mV)
(∆V
Th
 Input and output swing limitation
Level shift threshold-independent:

2
ΔV =
k 
L
L 
  I1 − I2 −   I2 
 W 1
W 2 
(
)
(assuming M1 in saturation and neglecting λ)
usually ∆V < VTh
€
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
25
Low Impedance:
It behaves like a voltage source
a)
b)
ΔV = VDS
2L
=
I + VTh
kW
ΔV = VGS1 + VGS2
€
€
 2L 
 2L 
= VTh1 + VTh2 + 
 I1 + 
 I2
 kW 1
 kW 2
a) rout = 1 / gm
b) affected by twice
voltage threshold
variation
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
26
€
€
Improved output stages
Source follower with local feedback:
(
)
i x = gm1 + gds2 v x + gm4v2
v2 = gm1rds3v x
Analog Design for CMOS VLSI Systems
Franco Maloberti
€
Rout
1
=
gm1 1+ gm4 rds3 + gds2
(
)
3. Basic building blocks
27
Class AB push-pull:
V12 = VGS3 + VGS4
W 
W 
  = k 
 L 1
 L 3

2L3
2L4
= VTh,n + VTh,p + I5 
+
µpW4Cox
 µnW3Cox
W 
W 
  = k 
 L 2
 L 4




With RL = 0
VGS1 ≈ VGS3, VGS2 ≈ VGS4, I1 = I2 = kI5
€
The output conductance is
gm = gm1 + gm2
With resistive load, the drop voltage across the output
resistance determines:
VGS1 > VGS3, VGS2 < VGS4, I2 = I1 – Iout
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
28
For a given load I2 → 0; the output conductance becomes
gout = gm1
In general an output stage has the following equivalent
circuit:
(
2
Rout = Rout0 1+ α1Iout + α 2Iout
+K
)
It determines harmonic distortion.
€
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
29
Class AB push-pull with gain stage:
Vg1 ≅ Vg2
if it is verified the condition:
1
1
+
<< rds6
gm4 gm5
Analog Design for CMOS VLSI Systems
Franco Maloberti
3. Basic building blocks
30