EECS 105 Spring 2004, Lecture 33
Lecture 33:
Prof J. S. Smith
Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Context
We are continuing to review some of
the building blocks for multi-stage
amplifiers, including current sources
and cascode connected devices, and
we will also look at the general
objectives of multi-state amplifier
configurations.
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University of California, Berkeley
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EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Reading
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Chapter 9, multi-stage amplifiers
Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Lecture Outline
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Department of EECS
Current Mirrors
An Example Using Cascodes
Multistage Amps
Example 1: Cascode Amp Design
Example 2: Two Stage CS Amp
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EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Current Sinks and Sources
Sink: output current goes
Source: output current comes
to ground
from voltage supply
Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Current Mirrors
We only need one reference current to set up all the current
sources and sinks needed for a multistage amplifier.
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University of California, Berkeley
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EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Multistage Amplifiers
Necessary to meet typical specifications for any of the 4 types
We have 2 flavors (NMOS, PMOS) of CS, CG, and CD and
the npn versions of CE, CB, and CC (for a BiCMOS
process)
What are the constraints?
1. Input/output resistance matching
2. DC coupling (no passive elements to block the signal)
Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Summary of Cascaded Amplifiers
General goals:
1. Boost the gain parameter (except for buffers)
2. Optimize the input and output resistances
Rin
Voltage:
Current:
Transconductance:
Transresistance:
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∞
0
∞
0
Rout
0
∞
∞
0
University of California, Berkeley
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EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Start: Two-Stage Voltage Amplifier
• Use two-port models to explore whether the combination
“works”
CE2
CE1
CE1,2
Results of new 2-port: Rin = Rin1, Rout = Rout2
Av = −Gm1 ( Rin 2 || Rout1 ) × ( −Gm 2 Rout 2 )
Av = Gm1Gm 2 ( Rin 2 || Rout1 )( Rout 2 )
Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Add a Third Stage: CC
Goal: reduce the output resistance
(important spec. for a voltage amp)
CE2
CE1
CC3
Output resistance:
Rout =
Department of EECS
R
r || r
1
1
+ S =
+ o 2 oc 2
g m3 β
gm3
β
University of California, Berkeley
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EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Using CMOS Stages
CS2
CS1
CD3
Input resistance: ∞
Voltage gain (2-port parameter):
Av = − g m1 ( ro1 || roc1 ) × g m 2 ( − ro 2 || roc 2 )
Output resistance:
Rout =
1
g m + g mb
Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Multistage Current Buffers
Are two cascaded common-base stages better than
one?
CB1
CB2
Input resistance: Rin = Rin1
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University of California, Berkeley
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EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Two-Port Models
Rout = Rout 2 ≅ r02 (1 + g m 2 rπ 2 || RS 2 ) || roc 2
Output impedance of stage #1 (large)
Rout ≅ r02 ( g m 2 rπ 2 ) || roc 2 = ( β o ro 2 ) || roc 2
Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Common-Gate
2nd
Stage
Rout = Rout 2 ≅ r02 (1 + g m 2 RS 2 ) || roc 2
Rout = Rout 2 ≅ r02 (1 + g m 2 ro1 || roc1 ) || roc 2
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University of California, Berkeley
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EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Second Design Issue: DC Coupling
Constraint: large inductors and capacitors are not
available
Output of one stage is directly connected to the
input of the next stage Æ must consider DC
levels … why?
3.2V
Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Alternative CG-CC Cascade
Use a PMOS CD Stage: DC level shifts upward
3.2V
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University of California, Berkeley
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EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
CG Cascade: DC Biasing
Two stages can have different supply currents
Extreme case:
IBIAS2 = 0 A
Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
CG Cascade: Sharing a Supply
First stage has no current
supply of its own Æ its output
resistance is modified
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University of California, Berkeley
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EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
The Cascode Configuration
Common source / common gate
cascade is one version of a cascode
(all have shared supplies)
DC bias:
Two-port model: first stage
has no current supply of its own
Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Cascode Two-Port Model
CS1*
CG2
Output resistance of first stage = Rout ,CS * = R down ,CS = ro1
Rout roc 2 || (1 + g m ro1 )ro 2
Gm = g m1
Rin = ∞
Why is the cascode such an important configuration?
Department of EECS
University of California, Berkeley
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EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Miller Capacitance of Input Stage
Find the Miller capacitance for Cgd1
Input resistance to
common-gate
second stage is low Æ
gain across
Cgd1 is small.
Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
CG Cascade: DC Biasing
Two stages can have different supply currents
Extreme case:
IBIAS2 = 0 A
Department of EECS
University of California, Berkeley
11
EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
CG Cascade: Sharing a Supply
First stage has no current
supply of its own Æ its output
resistance is modified
Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
The Cascode Configuration
Common source / common gate
cascade is one version of a cascode
(all have shared supplies)
DC bias:
Two-port model: first stage
has no current supply of its own
Department of EECS
University of California, Berkeley
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EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Cascode Two-Port Model
CS1*
CG2
Output resistance of first stage = Rout ,CS * = R down ,CS = ro1
Rout roc 2 || (1 + g m ro1 )ro 2
Gm = g m1
Rin = ∞
Why is the cascode such an important configuration?
Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Miller Capacitance of Input Stage
Find the Miller capacitance for Cgd1
Input resistance to
common-gate
second stage is low Æ
gain across
Cgd1 is small.
Department of EECS
University of California, Berkeley
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EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Two-Port Model with Capacitors
Miller capacitance: C M = (1 − AvC gd 1 )C gd 1
AvCgd 1 = − g m1 (
g
1
|| ro1 ) ≈ − m1 = −1
gm2
gm2
CM = 2C gd 1
Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Generating Multiple DC Voltages
Stack-up diode-connected
MOSFETs or BJTs and
run a reference current
through them Æ pick off
voltages from gates or
bases as references
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University of California, Berkeley
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EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Multistage Amplifier Design Examples
Start with basic two-stage transconductance
amplifier:
Why do this combination?
Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Current Supply Design
Output resistance
goal requires large
roc Æ
use cascode current
source
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University of California, Berkeley
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EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Totem Pole Voltage Supply
DC voltages must be set for the cascode current
supply transistors M3 and M4, as well as the gate of
M 2.
Why include M2B?
Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 33
Prof. J. S. Smith
Complete Amplifier Schematic
Goals: gm1 = 1 mS,
Rout =10 MΩ
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University of California, Berkeley
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