EECS 105 Spring 2004, Lecture 34
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
Reading
Lecture 34:
Designing amplifiers, biasing,
frequency response
Prof J. S. Smith
Department of EECS
z
Chapter 9, multi-stage amplifiers. The frequency
analysis is in the first section of chapter 10, but we
won’t go farther into chapter 10 for a while.
z
The Lectures on Wednesday and Friday will be
given by Joe and Jason, respectively. They will be
doing several example problems.
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Department of EECS
University of California, Berkeley
Prof. J. S. Smith
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
EECS 105 Spring 2004, Lecture 34
Context
Lecture Outline
We will figure out more of the design
parameters for the amplifier we
looked at in the last lecture, and then
we will do a review of the
approximate frequency analysis of
circuits which have a single
dominant pole.
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z
z
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Example 1: Cascode Amp Design
Example 2; CS NMOS->CS PMOS
Review of frequency analysis (with a
dominant pole)
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EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
Current Supply Design
Amplifier Schematic
High impedance current source means all of the
small signal current goes to the load resistance,
giving more SS voltage gain
Note that the backgate
connection for M2 is not
specified: ignore gmb
Output resistance
goal requires large
roc for high gainÆ
so we used a cascode
current source
Department of EECS
University of California, Berkeley
Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
Complete Amplifier Schematic
Bias voltages
derived from
transistors under
similar operating
conditions to
the transistors
they supply
Goals: gm1 = 1 mS,
Rout =10 MΩ
Cascode current source
For high roc
Totem Pole Voltage Supply
DC voltages must be set for the cascode current
supply transistors M3 and M4, as well as the gate of
M 2.
CG output
M2B supplies the
Bias quiescent voltage
For the CG stage
CS input, with
low voltage
gain
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EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
EECS 105 Spring 2004, Lecture 34
Miller Capacitance of Input Stage
Prof. J. S. Smith
Schematic
Find the Miller capacitance for Cgd1
Goals: gm1 = 1 mS,
Rout =10 MΩ
C gd
Input resistance to common-gate
second stage is low Æ gain across
Cgd1 is small.
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Department of EECS
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
EECS 105 Spring 2004, Lecture 34
Two-Port Model with Capacitors
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Prof. J. S. Smith
Device Sizes
M1: select (W/L)1 = 200/2 to meet specified
gm1 = 1 mS
Æ find VBIAS = 1.2 V
Miller capacitance: C M = (1 − AvC gd 1 )C gd 1
AvCdg 1 ≅ −
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g m1
gm2
University of California, Berkeley
Cascode current supply devices: select
VSG = 1.5 V
(W/L)4= (W/L)4B= (W/L)3= (W/L)3B = 64/2
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EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
Device Sizes
Find output resistance Rout
λn = (1/20) V-1, λn = (1/50) V-1 at L = 2 µm Æ
ron = (100 µA / 20 V-1)-1 = 200 kΩ, rop = 500 kΩ
Match M2 with diode-connected device M2B.
Output (Voltage) Swing
2I D 2
2(100 µA)
=
= 500 µS
VGS 2 − VTn 1.4V − 1V
2( − I D 3 )
2(100 µA)
=
=
= 400 µS
VSG 3 + VTp 1.5V − 1V
gm2 =
Assuming perfect matching and zero input voltage,
what is VOUT?
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
Two-Port Model
M2: select (W/L)2 = 50/2 to meet specified
Rout =10 MΩ
Æ find VGS2 = 1.4 V
Department of EECS
EECS 105 Spring 2004, Lecture 34
g m3
Rout = roc || ro 2 (1 + g m 2 RS 2 ) = ro 3 (1 + g m 3 RS 3 ) || ro 2 (1 + g m 2 ro1 )
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Prof. J. S. Smith
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
Voltage Transfer Curve
Maximum VOUT
Open-circuit voltage gain: Av = vout / vin = - gm1Rout
Minimum VOUT
= −103 ×10 7 =
vOUT
4
dvout
dvin
Q
≈ −10,000
3
2
1
0
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2
3
4
vIN
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EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
EECS 105 Spring 2004, Lecture 34
Multistage Amplifier Design Example
Prof. J. S. Smith
CS→CS
Amplifier
Direct DC connection: use NMOS then PMOS
Start with basic two-stage transconductance
amplifier:
Why do this combination?
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Department of EECS
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
Current Supply Design
Quiescent level shifts
Assume that the reference is a
“sink” set by a resistor
NMOS
PMOS
⇑
(typical)
⇓
(typical)
CG
⇑
⇓
CD
⇓
⇑
(known shift) (known shift)
CS
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Must mirror the reference
current and generate a sink for
iSUP 2
Source follower
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EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
DC Bias: Find Operating Points
Use Basic Current Supplies
Find VBIAS such that VOUT = 0 V
Device parameters:
µ nCox = 50 µA/V2
µ p Cox = 25 µA/V2
VTn = 1 V
VTp = -1 V
λn = 0.05 V-1
λp = 0.05 V-1
Device dimensions (for “lecture” design):
(W/L)n = 50/2
(W/L)p = 80/2
Department of EECS
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Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
Complete Amplifier Topology
Finding RREF
V+
Require IREF = - ID3 = 50 µA
M3
VSG 3 = −VTp +
RREF
VSG 3 = −(−1)V +
V
-
I REF = 50µA =
50 µA =
What’s missing? The device dimensions,
the bias voltage and reference resistor
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− 2I D3
µ p Cox (W / L)3
− 2 × 50 µA
4
= 1+
= 1.32V
25µA(80 / 2)
40
[V
+
] [ ]
− VSG 3 − V −
Rref
[2.5 − 1.32] − [− 2.5] ⇒ R
Rref
ref
= 74kΩ
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EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
EECS 105 Spring 2004, Lecture 34
DC Operating Point
Prof. J. S. Smith
Two-Port Model
IREF =
50 µA
Find Gm = iout / vin
VBIAS = VGS 1 = Vtn +
2 I D1
µ n Cox (W / L)
= 1+
100µA
9
≈ V
50( µA / V − 2 )(50 / 2) 7
Department of EECS
University of California, Berkeley
Department of EECS
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
EECS 105 Spring 2004, Lecture 34
Small-Signal Device Parameters
University of California, Berkeley
Prof. J. S. Smith
Output Voltage Swing
Transistors M1 and M2
gm1 = 350 µS
ro1 = 400 kΩ
gm2 = 315 µS
ro2 = 400 kΩ
Current supplies iSUP1 and iSUP2
roc1 = ro4 =400 kΩ
roc2 = ro6 =400 kΩ
Transistors M2 and M6 will limit the output swing
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EECS 105 Spring 2004, Lecture 34
Limits to Output Voltage
Prof. J. S. Smith
Prof. J. S. Smith
Output Current Limits
M6 will leave saturation when vOUT drops to:
vOUT , MIN = V − + VDS 6, sat = −2.5 +
EECS 105 Spring 2004, Lecture 34
2I D6
µ nCox (W / L )6
• Positive output current (negative vOUT)
iOUT , MAX = iD 6 − (0 ) = 50 µA = −vOUT , MIN / RL
vOUT ,MIN = −(50 µA)(25kΩ) = −1.25V
(less negative than limit set by saturation of M6)
vOUT,MIN = -2.5 + 0.28 = - 2.22 V
M2 will leave saturation when vOUT rises to:
+
vOUT , MAX = V − VSD 2, sat
2( − I D 2 )
= 2 .5 −
µ p Cox (W / L )2
vOUT,MAX = 2.5 - 0.32 = 2.18 V
• Negative output current (positive vOUT)
No limit on current from M2, so voltage swing sets
current limit
iOUT , MIN = −vOUT , MAX / RL =
What about M4?
− (2.18V / 25kΩ) = −87.2 µA
Department of EECS
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Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
Output Current Swing
Transfer Curves (for RL = 25 kΩ)
Loaded voltage gain = vout/vin = (gm1Rout1)(gm2Rout||RL) = 490
Load resistor: pick RL = 25 kΩ
Output current: iOUT = −vOUT / RL
Loaded transconductance = iout/vin
= (-gm1Rout1)(gm2)(Rout/(Rout + RL) = -19.5 mS
iOUT = iD 6 − (− iD 2 )
iOUT
Limits: asymmetrical
vOUT
M2: can increase - iD2
-2
-1
M6: can’t increase iD6
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vOUT
iOUT [µA]
2
100
1
50
-1
1
-50
-2
-100
1
0
2 vIN
-2
-1
0
2 vIN
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EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
Review: Frequency Resp of Multistage Amplifiers
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
Approximating the Transfer Function
Multiply out denominator:
• We have a systematic technique to study amplifier
performance (derive transfer function, study
poles/zeros/Bode pltos).
• In most cases, the systematic approach is too
cumbersome.
• We have a good qualitative understanding of
circuit performance (e.g., CS suffers from Miller
effect, CD andd CG are wideband stages …)
• Open Circuit Time Constants: Analytical
technique is capable of estimating only the
dominant (lowest) pole …for a restricted class of
amplifiers.
H ( jω ) =
≈
Ho
(1 + jω / ω1 )(1 + jω / ω2 )...(1 + jω / ωn )
Ho
⎛ 1
1
1 ⎞
1 + jω ⎜⎜ +
+ ... + ⎟⎟
ωn ⎠
⎝ ω1 ω2
Since ω1 << ω2, ω3, …, ωn Æ
b1 =
1
+
1
ω1 ω 2
+ ... +
1
ωn
≈
1
ω1
Department of EECS
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Department of EECS
University of California, Berkeley
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
EECS 105 Spring 2004, Lecture 34
Prof. J. S. Smith
The Special Case
How to Find b1?
The transfer function can have no zeroes and must
have a dominant pole ω1 << ω2, ω3, …, ωn
H ( jω ) =
Ho
1 + jωb1 + ( jω ) 2 b2 + ( jω ) 3 b3 + ...
(
)
Factor denominator:
H ( jω ) =
Ho
(1 + jω / ω1 )(1 + jω / ω 2 )...(1 + jω / ω n )
See P. R. Gray and R. G. Meyer, Analysis and Design of
Analog Integrated Circuits (EE 140) for derivation
Result: b1 is the sum of open-circuit time constants
τi which can be found by considering each
capacitor Ci in the amplifier separately and
finding the Thévenin resistance RTi of the
network from the capacitor’s point of
viewÆ
τi = RTi Ci
b1 = ∑i =1 RTi Ci ⎯
⎯→ ω1 ≈
1
n
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∑
n
i =1
RTi Ci
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EECS 105 Spring 2004, Lecture 34
Finding the Thévenin Resistance
Prof. J. S. Smith
1. Open-circuit all capacitors (i.e.; remove them)
2. For capacitor Ci, find the resistance RTi across its
terminals with all independent sources removed
(voltages shorted, currents opened) … might need
to apply a test voltage and find the current in some
cases.
Insight for design: the bandwidth of the amplifier will
be limited by the capacitor that contributes the largest
τi = RTi Ci Æ not necessarily the largest Ci
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