ATE-A1
Testing Without Relays - Using Inductors to
Compensate for Parasitic Capacitance
TEST AND MEASUREMENT PRODUCTS
Introduction (Why Get Rid of Relays?)
The capacitance of the PPMU also interferes with the ideal
performance of the transmission line and, therefore, the
accuracy of the AC measurements made over the
transmission line. Since the PPMU is in the circuit when
high-speed signals are passing between the DCL and the
DUT (see Figure 1), the PPMU must have minimal impact
on these signals. This means that the lead length to the
PPMU must be short and the parasitic capacitance of the
Force/Sense pins must be small.
Due to their size, cost and relatively slow (millisecond)
operating speeds, minimizing the number of mechanical
relays is a significant goal of any ATE design. This paper
covers one approach to optimizing the AC performance
when the relays separating the DC measurement section
(Per Pin Parametric Measurement Unit; PPMU) and the
AC test section (Driver, Comparator, Load; DCL) are
removed.
A PPMU such as the E4707B, designed to have minimal
output capacitance when disabled, still has enough
capacitance to both degrade the rise/fall times of fast
signals from the driver, as well as cause a transient in the
signal reflected from the DUT (see Figure 2). If the pin
driver is used to terminate a signal from the DUT into the
driver’s 50Ω output resistance, the parasitic capacitance
will not cause a transient in the signal from the DUT, but
will still slow the rise and falls times.
What Happens when PPMU and DCL are Connected
to the DUT at the Same Time?
When the PPMU and the DCL are simultaneously
connected to a test device (DUT), the leakage of the DCL
inputs appears in parallel with the DUT leakages. This
can be calibrated out if the DCL leakage is small enough.
Semtech DCL leakages are typically less than 5nA over
most of their voltage range, therefore having minimal
impact on the PPMU current measurements above this
current.
SENSE
Per-Pin DC
Measurement Unit
FORCE
50
Driver
50Ω
–
+
DUT Pin
Transmission Line
Window Comparator
+
–
Signals from Pin Driver are
reflected by DUT and are
terminated at Pin Driver
AC Pin Electronics
Figure 1. Simultaneous Conection of PPMU and DCL to DUT
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ATE-A1
Testing Without Relays - Using Inductors to
Compensate for Parasitic Capacitance
TEST AND MEASUREMENT PRODUCTS
1.50
1.00
0.50
0.00
500ps R/F input signal
-0.50
11pf load capacitance
-1.00
-1.50
0
1
2
3
4
5
6
7
8
9
Time (nS)
Figure 2. Effect of 11pF PPMU Parasitic Capacitance on a 500ps Rise/Fall Time Signal
Reducing the Effect of the PPMU Capacitance
An ideal transmission line acts as a continuous series L-parallel C circuit whose impedance is:
Z=
L
C
So a lumped capacitance can, in principle, be compensated for by adding a lumped inductance in series. For a 50Ω
transmission line, a series inductance of 2.5nH/pF could theoretically be used to compensate for a parallel capacitance
as shown in Figure 3.
SENSE
Per-Pin DC
Measurement Unit
FORCE
50
Driver
Inductor
–
+
50Ω
DUT Pin
Transmission Line
Window Comparator
+
–
AC Pin Electronics
Figure 3. Compensating for PPMU Capacitance with a Single Inductor
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ATE-A1
Testing Without Relays - Using Inductors to
Compensate for Parasitic Capacitance
TEST AND MEASUREMENT PRODUCTS
In practice, placing an inductor in series does in fact reduce the transient due to the parallel capacitance, but at the
expense of further reducing the rise/fall times of the transmitted signals. Figure 4 shows the effect of varying amounts
of inductor compensation on a 500ps rise time signal with 11pF lumped capacitance. The amounts of these effects
are quantified in Table 1. As can be seen, enough inductance to significantly reduce the amount of transient significantly
reduces the rise/fall time of the signal.
1.50
1.00
0.50
0.0nh
0.00
3.3nh
6.8nh
-0.50
12 nh
-1.00
18nh
-1.50
0
2
4
6
8
10
Time (nS)
Figure 4. Rise/Fall Time and Glitch from a 500ps Input Signal, 11pF Lumped Capacitance
and Varying Series Inductance
Series
Inductance
(nH)
Measured
10%-90%
Rise Time (ps)
Percent
Overshoot
Percent
Undershoot
0
806
3.8
22.1
3.3
840
5.4
21.7
6.8
750
5.5
20.4
12
832
6.8
16.0
18
961
8.4
13.0
27
936
16.5
10.6
Table 1. Waveform Rise/Fall Times and Overshoot/Undershoot with Varying Inductive Compensation
Using two inductors instead of one to compensate for the lumped capacitance, as shown in Figure 5, gives substantial
improvement in rise/fall times for a given amount of over/undershoot at the cost of adding an extra inductor. Table 2
quantifies this effect.
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ATE-A1
Testing Without Relays - Using Inductors to
Compensate for Parasitic Capacitance
TEST AND MEASUREMENT PRODUCTS
SENSE
Per-Pin DC
Measurement Unit
FORCE
50
Driver
Inductor
Inductor
50Ω
–
+
DUT Pin
Transmission Line
Window Comparator
+
–
AC Pin Electronics
Figure 5. Compensating for PPMU Capacitance with Two Inductors
Configuration
Measured
10%-90%
Rise Time (ps)
Percent
Overshoot
Percent
Undershoot
3.3nH–11pF–3.3nH
843
5.1
20.1
4.7nH–11pF–4.7nH
811
4.5
17.7
6.8nH–11pF–6.8nH
765
5.5
16.3
10nH–11pF–10nH
754
6.9
13.4
13nH–11pF–12nH
789
7.8
10.8
15nH–11pF–15nH
891
8.7
6.5
Table 2. Rise/Fall Times and Over/Undershoot for L-C-L Configuration
Up to this point, the PPMU Force and Sense lines have been connected to the transmission line at one single point.
Since a transmission line is a continuous L-C-L-C, a better approximation of this can be achieved by connecting the
Force and Sense lines separately. This requires additional board space since two lines must now be routed, but if the
PPMU is located close enough to the transmission line to minimize the signal reflection, the line routing should not be
a problem. One approach is to use a single inductor between the two capacitances as shown in Figure 6. In this
configuration, the two nodes do not have the same capacitance. The force node has typically 8pF and the sense
node has 3pF. As can be seen from the data in Table 3, this C-L-C approach gives performance similar to the L-C-L
approach above.
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ATE-A1
Testing Without Relays - Using Inductors to
Compensate for Parasitic Capacitance
TEST AND MEASUREMENT PRODUCTS
SENSE
Per-Pin DC
Measurement Unit
FORCE
50
Driver
Inductor
50Ω
–
+
DUT Pin
Transmission Line
Window Comparator
+
–
AC Pin Electronics
Figure 6. Compensating for PPMU Capacitance with a Single Inductor between Force and Sense Lines
Configuration
Measured
10%-90%
Rise Time (ps)
Percent
Overshoot
Percent
Undershoot
3pF-3.3nH-8pF
720
3.6
24.3
3pF-6.8nH-8pF
664
3.2
21.0
3pF-10nH-8pF
656
3.5
19.3
3pF-15nH-8pF
694
4.6
16.1
3pF-22nH-8pF
770
8.2
13.0
3pF-27nH-8pF
841
11.6
10.4
Table 3. Rise/Fall Times and Transient Overshoot/Undershoot from Using
a Single Inductor Between Separated Force and Sense Lines
However, once the Force and Sense lines are separated, it makes sense to use separate inductors for each line as
shown in Figure 7. This goes an additional step to approximating the continuous L-C structure of a transmission line.
As shown in Table 4, this topology yields significantly reduced rise/fall times and undershoot/overshoot than the
previous approaches. Note that the optimum performance occurs much closer to the theoretical 2.5nH/pF
compensation, indicating that this circuit is much closer to an ideal transmission line than the previous examples.
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ATE-A1
Testing Without Relays - Using Inductors to
Compensate for Parasitic Capacitance
TEST AND MEASUREMENT PRODUCTS
SENSE
Per-Pin DC
Measurement Unit
FORCE
50
Driver
Inductor
Inductor
50Ω
–
+
DUT Pin
Transmission Line
Window Comparator
+
–
AC Pin Electronics
Figure 7. Compensating for PPMU Capacitance with a Two Inductors with Separate Force and Sense Lines
Configuration
Measured
10%-90%
Rise Time (ps)
Percent
Overshoot
Percent
Undershoot
3pF–5.6nH–8pF-10nh
662
7.1
14.2
3pF–6.8nH–8pF-10nh
668
8.0
13.9
3pF–10nH–8pF-10nh
658
6.7
11.1
3pF–12nH–8pF-10nh
665
7.1
9.8
3pF–15nH–8pF-10nh
686
6.8
8.2
3pF–18nH–8pF-10nh
703
8.4
5.9
Table 4. Rise/Fall Times and Overshoot/Undershoot Charateristics of the Figure 7 Circuit
At this point it is tempting to further improve the waveform by inserting an additional inductor after the Sense connection
to make an L-C-L-C-L configuration, but makes virtually no improvement (See Table 5). This is primarily because the
3pF capacitance of the Sense pin has much less effect at 500ns rise/fall times than the 8pF Force capacitance.
Configuration
Measured
10%-90%
Rise Time (ps)
Percent
Overshoot
Percent
Undershoot
3.3nH-3pF-15nH-8pF-10nH
695
7.8
6.9
3.9nH-3pF-15nH-8pF-10nH
688
8.6
6.8
3.9nH-3pF-12nH-8pF-10nH
687
7.5
8.4
Table 5. Waveform Performance of Three-Inductor Compensation Scheme
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Testing Without Relays - Using Inductors to
Compensate for Parasitic Capacitance
TEST AND MEASUREMENT PRODUCTS
As the rise/fall times of the input signal change, the amount of waveform distortion caused by these circuits changes
as well. The effect of the 3pF-15nH-8pF-10nH circuit with varying rise/fall time signals is shown graphically in Figure
8 and quantified in Table 6.
1.5
1.0
150 ps
250 ps
354 ps
500 ps
707 ps
1000ps
2000 ps
0.5
0.0
-0.5
-1.0
-1.5
0
2
4
6
time (ns)
8
10
Figure 8. Waveforms for 3pF-15nH-8pF-10nH Circuit (Figure 7) with Varying Rise/Fall Time Inputs
Rise/Fall Times (ps)
Input
Signal
Output
Signal
Percent
Overshoot
Percent
Undershoot
150
524
9.3
10.4
250
555
7.8
9.7
354
604
8.3
9.2
500
685
6.5
8.3
707
810
5.6
6.8
1000
1080
4.7
2.0
Table 6. Performance of 3pF-15nH-8pF-10nH Circuit (Figure 7) with Varying Rise/Fall Time Inputs
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Testing Without Relays - Using Inductors to
Compensate for Parasitic Capacitance
TEST AND MEASUREMENT PRODUCTS
Further Refinements
Since small increases in the amount of parasitic
capacitance clearly make a significant difference in the
circuit’s AC performance, it is important to do as much as
possible to reduce stray capacitance. Besides reducing
the trace lengths to the PPMU, it is also useful to minimize
the effect of a given trace length. This can be done by
minimizing the trace width and by removing as much of
the ground and power planes as possible beneath the
trace. This must be done with care to ensure that noise
and crosstalk are not introduced. Since a continuous
ground plane is needed for good microstripline or stripline
transmission line performance, the ground plane must not
be removed in the vicinity of these signal paths.
Since the sense circuit has very little current flow
(nanoamps), the capacitance of this circuit can be
decoupled from the transmission line using a series resistor
as shown in Figure 9. (This resistor should be as close to
the transmission line as possible to get the maximum
effect). If the resistor is large relative to the transmission
line impedance, the amount of distortion will be
proportionately small. For instance, if the transmission
line impedance is 50Ω and the series resistor is 5KΩ, the
amount of distortion due to the sense line capacitance is
limited to 50/5000 = 1%. In most systems this is small
enough to be ignored. One must take care, however, that
the R-C time constant due to the series resistor and the
total sense line capacitance is small enough not to cause
settling time or stability problems in the PPMU circuit.
SENSE
Per-Pin DC
Measurement Unit
FORCE
50
5K
Driver
Inductor
Inductor
–
+
50Ω
DUT Pin
Transmission Line
Window Comparator
+
–
AC Pin Electronics
Figure 9. Using a Series Resistor to Mask the Capacitance of the PPMU Sense Node
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ATE-A1
Testing Without Relays - Using Inductors to
Compensate for Parasitic Capacitance
TEST AND MEASUREMENT PRODUCTS
Inductor in Series with PPMU
An alternate configuration where the inductor is placed in
series with the PPMU Force/Sense lines, as shown in Figure
10, is often proposed. Rather than imitating a transmission
line circuit, this inductor is intended to mask the effect of
the PPMU capacitance, much like the resistor in series
with the PPMU sense line described in the previous section.
rise/fall times will have less distortion, but placing the
inductors in series with the transmission line will still give
better performance. Reducing the parasitic capacitance
to the 8pF of the E4707 Force line alone only improves
this marginally.
The problem is that, in order for a resistor in series with
the PPMU lines to mask the PPMU capacitance, two criteria
must be met. First, the impedance of the inductor must
be much higher than the impedance transmission line at
all the frequencies at which the DCL and DUT may be
operating. Since these frequencies can easily range from
100’s of MHz down to KHz, this requirement alone is hard
to meet. Next, the resonant frequency of the inductor
and the PPMU capacitance must be much lower than the
Unfortunately, in most cases this approach does not have
the desired effect. The Inductor and PPMU capacitance
create a resonant circuit which actually slows the rise/fall
times down even more than the capacitance alone while
not significantly reducing the magnitude of the capacitive
undershoot. Waveform examples with varying inductances
in the circuit in Figure 10 are shown in Figure 11. These
show the response to a 500ps rise/fall time signal. Slower
SENSE
Per-Pin DC
Measurement Unit
FORCE
50
Inductor
Driver
50Ω
–
+
DUT Pin
Transmission Line
Window Comparator
+
–
AC Pin Electronics
Figure 10. Inductor Placed in Series with PPMU Dorce and Aense Lines
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Testing Without Relays - Using Inductors to
Compensate for Parasitic Capacitance
TEST AND MEASUREMENT PRODUCTS
lowest frequency of operation. This also requires a larger
than practical inductance.
Compounding this, the inductor impedance must also be
low enough not to interfere with the accuracy, settling times
and stability of the PPMU. Since modern PPMU’s can
have ~1V/µs slew rates and 0.1% settling times of less
than 100µs, there can be considerable overlap between
the minimum DCL frequency and the maximum PPMU
frequency. Thus, meeting this requirement, along with
the previous ones, is difficult if not impossible for most
systems
Load cap= 11pf (E4707 force + sense)
1.50
.
1.00
0.50
0.0nh
0.00
3.3nh
6.8nh
-0.50
8.2nh
12nh
-1.00
-1.50
0
2
4
6
8
10
Time (nS)
Figure 11. Waveforms with Varying Inductances Placed in Series with the PPMU Force/Sense Lines
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