Slew Rate
vO
=
vI
if
1
1+
s
(1)
ωt
v I (t ) = V ⋅ u (t )
then vO (t ) = V (1 − e −t / τ )
where τ = 1 / ω t
(2)
(3)
For V large, the op amp output will be unable to rise at the rate predicted by equation 3.
When the op amp output is unable to rise at the rate predicted by equation 3, i.e., V/τ
(ωt=0), it is said to be slew-rate limited – or slewing.
The slew-rate (SR) is the maximum possible rate of change of the op amp output voltage.
SR =
dvO
dt
V / µ sec
max
Origin of slew rate
At t = 0, v2=vI=V, vO=0; i.e., v1=0, ∴vid=V
∴the trans conductance will saturate.
∴IO = Imax
1
idt
C∫
t
I
1
= ∫ I max ⋅ dt = max ⋅ t
C0
C
vO (t ) =
Hence
or
SR =
I max
C
Full-Power Bandwidth
Op-amp slew-rate limiting can cause nonlinear distortion in sinusoidal waveforms.
v I = Vˆi sin ωt
dv I
= ωVˆi cos ωt
dt
dv I
dt
also
dvO
dt
= ωVˆi
max
= ωVˆo
max
The frequency at which an output sinusoid with amplitude equal to the rated output
voltage of the op amp begins to show distortion due to slew-rate limiting is called the
full-power bandwidth, fM.
ω M Vo max = SR
∴ fM =
SR
2πVo max
For Vo<Vomax (= rated o/p voltage), slew rate distortion will appear at a frequency ω
given by:
ωVo = SR
or ωVo = ωMVomax
i.e., Vo = Vomax ( ωM/ω)
COMMON-MODE REJECTION
Acm = common-mode gain = vo/vIcm
vid = v2-v1
vIcm = (v2+v1)/2
vo = Avid + AcmvIcm
Common-mode rejection ratio (CMRR)
CMRR =
A
Acm
or in dB, = 20 log10
A
Acm
INPUT AND OUTPUT RESISTANCES
DC Problems
Offset voltage:
The DC output offset will change the bias conditions and drive the amplifier to
saturation. To avoid this problem, we capacitively coupled amplifiers.
C is selected large enough to appear almost as a short circuit for input frequencies – i.e.,
1
≈0
ω ∈ [ω min , ω max ].
ωC
Input Bias Currents
The average value IB is called the input bias current. I B =
Input offset current: I off = I B1 − I B 2
Typical values:
I B1 + I B 2
2
IB= 10nA, Ioff= 10nA (BJT’s)
PA. (FET’s)
IB1 Ioff
Add an R3 at terminal 2
VO = − I B 2 R3 − (
if
I B1 ≈ I B 2 = I B
VO → 0 if
or
I B 2 R3
− I B1 ) R2
R1
R3 =
R2 = R3 (1 +
∴VO = I B [ R2 − R3 (1 +
R2
)]
R1
R2
)
R1
R1 R2
R 1 + R2
C is to minimize DC input offset voltage
R3 is to minimize input bias current effect.
Note: when using ad coupling always provide a dc path to ground.