VOLTAGE SAG COMPENSATION OF POINT OF COMMON
COUPLING (PCC) USING FAULT CURRENT LIMITER
IN THREE PHASE LINES
1
P.ANUSHA & 2K. SWARNASRI
Department of Electrical & Electronics Engineering,
R.V.R &J.C.College of Engineering, Chowdavaram, Guntur, A.P, India.
E-mail: peram00@gmail.com, : swarnasrik@gmail.com
Abstract-This paper presents a new component called Fault Current Limiter (FCL) in three phase lines. Voltage sag
compensation is provided on both sides of the Point of Common Coupling (PCC) by using FACTS Devices (STATCOM,
APF, DSTATCOM, DVR, UPFC) and FCL. The FACTS devices provide compensation on input side and FCL provides
compensation on output side. A sensitive load is considered at output side of PCC. The main objective of the designed
component is to protect the sensitive load from the shunt faults. The compensation is being provided at output side of PCC.
Load voltage reduces upon the occurrence of shunt fault. This results in unbalance of the system voltages and phase angle
jump. The foremost purpose of the FCL would be to limit the voltage sag and the phase angle change of the substation point
of common coupling. IGBT based FCL is designed in this paper instead of Thyristor based FCL. When IGBT is used as
switching device, FCL will have reduced ac side losses and increased speed of operation. DC side reactor value can be
reduced to a lower value. Lowered Total Harmonic Distortion (THD) and improved voltage wave form at PCC shows the
effective ness of the designed FCL. The analysis and design is carried out in MATLAB with SIMULIN K simulation
package.
Index Terms— Fault Current Limiter (FCL),Point of Common Coupling (PCC), Total Harmonic Distortion (THD), Power
Quality (PQ).
coil in the FCL. The non conducting coil exhibits
power loss which is negligible as compared with the
total power provided by the radial feeders.
In this paper IGBT based FCL is proposed for
voltage sag and phase angle jump mitigation of the
substation PCC.
I. INTRODUCTION
Now a day‟s power system network becomes very
complex due to rapid changes in development. There
is a great desire for improving power quality because
of growing demand of electrical energy. There are so
many power quality problems i.e. malfunctioning of
the control systems and voltage sag etc. that are
affected on the power transmittable capacity of the
transmission system. The voltage sag problem rises
due to increasing the sensitive load demand. The
voltage sag problems are mostly appears in buses
which are connected to radial feeders [1]-[6]; results
loss of voltage quality.
The dynamic voltage restorer (DVR) is most
commonly used for voltage sag compensation which
will inject the compensated voltage with magnitude
and phase angle in series with the distribution feeders
[7],[8]. During the fault the voltage sag is
proportional to the short circuit current level. The
levels of fault current in different places have often
exceeded the withstand capacity of existing power
system equipment due to this the stability and
reliability of the power system will be reduces[9].
Thus, the fault current of the power system is limiting
to a safe level can greatly reduce the risk of failure to
the power system equipment due to high fault current
flowing through the system.
II. VOLTAGE SAG IN POWER SYSTEM
Fig.1 shows the single-line diagram of the three
phase power system. This figure shows a substation
with six feeders (F1,F2,F3,F4,F5,F6). For an easy
analysis of the three phase lines we are consider only
one phase instead of three phases.
PCC
F1
BUS BAR
Sensitive load
FCL
F2
F3
Sensitive load
FCL
F4
F5
AC
AC
AC
TRANSFORMER
Sensitive load
FCL
F6
Figure 1. Single-line diagram of the three phase power system
The levels of fault current are controlled by super
conducting fault current limiter (SFCL) due to their
variable impedance characteristics but the cost of
super conductors is high. Therefore, the super
conducting coil is replaced with non superconducting
The below figure shows the single line diagram
of the power system, here we are considering only
one phase which is having two feeders F1 and F2.
Feeder F1 supplies a sensitive load and F2 is faulted.
International Conference on Electrical Electronics and Computer Science-EECS-9th Feb 2014-ISBN-978-93-81693-54-2
106
Voltage SAG compensation of point of common coupling (PCC) using fault current limiter in three phase lines
BUS BAR
PCC
F1
Sensitive load
𝑍- Phasorof the load impedance at the F2.
In the normal state ZK(N),is larger than|𝑍𝑆 + 𝑍𝑡 | .
So the PCC voltage is approximately equal to the
source voltage. In the fault condition in the F2, the
voltage and phase angle of substation PCC can be
expressed as follows:
FCL
F2
TRANSFORMER
AC
Fault
Figure 2. Single-line diagram of the power system
𝑉𝑃𝐶𝐶(𝐹) =
Fig.3. shows the positive-sequence equivalent circuit
of the case study system in the fault condition. To
calculate the voltage sag, the simple voltage divider
method is introduced in [10].
Φ𝑃𝐶𝐶
BUS BAR
Zs
𝑉𝑃𝐶𝐶
PCC
Zl1
Zsl
Zl2
Z
Sensitive load
Where
VPCC(F)
during fault
ΦPCC(F)
during
𝑉 PCC(F)
fault
ZF
Figure3.Positive-sequence equivalent circuit of the case study
system in the fault condition.
In the normal operating condition, the voltage
magnitude and its phase angle in the substation PCC
can be expressed as follows:
𝑍𝑆 +𝑍𝑡 +𝑍 𝐾 (𝑁 )
Φ𝑃𝐶𝐶
𝑁
=
𝑍 𝐾 (𝑁 )
= 𝑎𝑟𝑐 tan
𝑋 𝐾 (𝑁 )
𝑅𝐾 (𝑁 )
(5)
𝑉𝑆
(6)
𝐹
𝐹
𝑋 𝐾 𝐹 +𝑋 𝑆 +𝑋𝑡
𝑅𝐾 𝐹 +𝑅𝑆 +𝑅𝑡
(7)
- Voltage magnitude of the PCC
-Phase angle of voltage of the PCC
the fault
-voltage phasor of the PCC during
- Fault
impedance.
Equivalent impedance of parallel feeders during fault
is
𝑉𝑆
𝑍 𝑆 +𝑍𝑡 +𝑍𝐾 (𝑁 )
−1
𝑋𝐾
𝑅𝐾
𝑉𝑆
𝑍𝐾(𝐹) = 𝑅𝐾(𝐹) + 𝑗𝑋𝐾(𝐹)
(1)
𝑁
= tan−1
F2
Fault
𝑍 𝐾 (𝑁 )
𝑍 𝐾 (𝐹)
𝑍 𝑆 +𝑍𝑡 +𝑍𝐾 (𝐹)
− tan
Zt
Zf
𝑉𝑃𝐶𝐶
𝐹
=
F1
AC
𝑉𝑃𝐶𝐶(𝑁) =
𝐹
𝑍 𝐾 (𝐹)
𝑍𝑆 +𝑍𝑡 +𝑍 𝐾 (𝐹)
𝑍𝐾(𝐹) = 𝑍𝐿1 + 𝑍𝑆𝐿
(8)
𝑉𝑆
− 𝑎𝑟𝑐 tan
𝑍𝐿2 + 𝑍𝐹
(2)
In the three-phase fault condition i.e.symmetrical
fault
condition,
the
fault
impedance
(ZF)isapproximately equal to zero and according to
equation (8) the magnitude of 𝑍K(F)will be small.
During the faultthe voltage sag and phase angle jump
of the sensitive load is comparatively worse. To
prevent voltage sag and phase angle jump during a
fault, a new component is introducing between the
substation PCC and the fault location for providing
large limiting impedance. A new component is
known as FCL.
𝑋 𝐾 (𝑁 ) +𝑋 𝑆 +𝑋𝑡
𝑅𝐾 (𝑁 ) +𝑅𝑆 +𝑅𝑡
(3)
Where
VPCC(N)-Voltage magnitude of the PCC in normal
state.
𝑉 PCC(N) - Voltage phasor of the PCC in normal state.
ΦPCC(N)
- Phase angle of voltage of the PCC in
normal
state. Where the phase angle of 𝑉 s is considered
to be zero
𝑍𝑡 -Phasor of transformer impedance.
𝑍𝐾(𝑁) = 𝑅𝐾(𝑁) + 𝑗𝑋𝐾(𝑁) - Equivalent impedance of
parallel
feeders in normal state.
𝑉S
-Phasor of source voltage.
𝑍𝑆 = 𝑅𝑆 + 𝑗𝑋𝑆 - Phasor of source impedance.
II. FCL CONFIGURATION AND ITS
OPERATION
The Fault Current Limiter (FCL) is defined as “it
is a variable impedance device connected in series
with a circuit to limit the currentunder fault
conditions [4]”. During normalcondition the „FCL‟
should have very low impedance and under fault
condition it should have high impedance [5,6]. FCL
has potential to reduce fault level on the electricity
power networks and may ultimately lead to lower
rated components being used or to increased capacity
𝑍K(N) =( 𝑍L1+𝑍SL )∥(𝑍L2+𝑍)
(4)
International Conference on Electrical Electronics and Computer Science-EECS-9th Feb 2014-ISBN-978-93-81693-54-2
107
Voltage SAG compensation of point of common coupling (PCC) using fault current limiter in three phase lines
onexisting systems[4]. FCL limits the
circuitcurrent to an acceptable level[7,8].
short
VSWF
- Forward voltage drop on the
semiconductor switch
Iave
- Average of diodes current in each cycle
that is
equalto Ipeak/π
Fig.4 shows Fault Current Limiter (FCL) circuit
topology which is formed by composing of two
individual parts.
Considering (9) the power loss FCL becomes a very
small percentage of the feeder‟s transmitted power. In
the fault condition, the PCC voltage drops on the
shunt impedance. Therefore, the line current will
bypass through the shunt resistor (Rsh). As a result,
power loss on the Rsh depends on its value. Note that
the fault condition is more than a few cycles and it is
a small time interval.
1) Bridge part that includes a diode rectifier
bridge, a small dc limiting reactor (Ldc)
.resistance (Rdc), a semiconductor switch
(IGBT or GTO),and a freewheeling
diode(D5) .
2) Shunt branch as a compensator that includes
a resistor and an inductor (Rsh + jωLsh).
III. CONTROL STRATEGY
Fig.5 shows the control circuit of the FCL. In the
normal operating condition of the power system,
IGBT is turned ON and the line current (i L) flows
through “D1, Ldc, IGBT, D4” and “D3, Ldc, IGBT,
D2” in positive and negative alternatives,
respectively. So, Ldc is charged to the peak of the line
current and behaves as a short circuit. Using
semiconductor devices and a small dc reactor cause a
negligible voltage drop on the FCL.
During fault condition, Idc become greater than
the maximum permissible current I m. The control
circuit detects it and turns the semiconductor switch
off. So the bridge retreats from the feeder, and the
shunt impedance enters the faulted line and limits the
fault current. At this moment, the freewheeling diode
discharges Ldc. In fact, the freewheeling diode is used
to provide a free route for the dc reactor current when
the semiconductor switch is OFF.
Figure 4. Fault Current Limiter (FCL) circuit topology.
Previously thyristor based FCL is used instead of one
semiconductor device (IGBT) at bridge arms for
reducing the levels of the fault current.Thyrister
based FCLposses two limitations first, they have
more complicated control system. Second,
considerable voltage drop on the FCL and the ac
power loss on the shunt branch impedance, dc reactor
power loss in the normal operating condition.
In the proposed topology IGBT based FCL is
used to reduce the voltage drop and power losses,
increase the speed of operation. It is possible to
choose a small value for Ldc to prevent severe rate of
change of current at the beginning of the fault
occurrence. In the normal operating condition the
FCL has the power losses on the rectifier bridge
diodes, IGBT, Rdc.Therefore,the power loss of this
FCL can be calculated as
Figure 5. Control circuit of the proposed FCL
After the fault is removed, while the
semiconductor switch is OFF, shunt impedance will
be connected in series with the load impedance.
Therefore,
line
current
will
be
reduced
instantaneously. To detect this instantaneous
reduction of line current, iLis compared fault current
(If) with that can be calculated from
𝑃𝑙𝑜𝑠𝑠 = 𝑃𝑅 + 𝑃𝐷 + 𝑃𝑆𝑊
2
= 𝑅𝑑𝑐 𝐼𝑑𝑐
+ 4𝑉𝐷𝐹 𝐼𝑎𝑣𝑒 + 𝑉𝑆𝑊𝐹 𝐼𝑑𝑐
where
Idc
VDF
(9)
- dc side current which is equal to the peak
of line
current
-Forward voltage drops on each diode
I𝑓 =
𝑉 𝑃𝐶𝐶
𝑅𝑠ℎ + 𝑗𝜔 𝐿𝑠ℎ
(10)
International Conference on Electrical Electronics and Computer Science-EECS-9th Feb 2014-ISBN-978-93-81693-54-2
108
Voltage SAG compensation of point of common coupling (PCC) using fault current limiter in three phase lines
When the difference of line current (iL) and fault
current(If)becomelarger than as the fault removal
sign, the control circuit turns the semiconductor
switch ON. So, the power system proceeds to the
normal state. The value of k can be calculated from as
k=
𝑉 𝑃𝐶𝐶
𝑍𝑠ℎ
−
𝑉 𝑃𝐶𝐶
𝑍𝑠ℎ + 𝑍𝐿,𝑚𝑖𝑛
However, it is difficult to equate these impedances
exactly because of the load variation on distribution
feeders. So it is difficult to estimate the suitable value
for Lsh and Rsh. From a practical point of view,
parameters of the shunt branch can be resolute by
using the history of load measurements at the
protected distributed feeder. It is obviously the power
and current flowing through the feeders is change.
For the calculation of Lsh and(3.11)
Rsh values, average
impedance of the protected feeder is calculated. So
Lshand Rshare chosen to be equal to its inductance and
resistance.
The horizontal axis of this Fig.6(a) shows the
magnitude of load impedance in per unit where the
base value is its impedance of the ideal case. The
dashed line represents the existence of the ideal case.
The ratio of reactance to resistance of shunt branch is
kept constant in this figure. The parameter of this
figure is the magnitude of source impedance. This
figure shows that for a large range of load magnitude
variations (0.5 to 2 p.u. with a fixed shunt branch
impedance), the voltage magnitude of PCC for the
post fault condition changes in an acceptable range
especially for low values of 𝑍𝑆 .
Fig.6(b) shows the phase-angle deviation of the
PCC from its base value that is the phase-angle
deviation of pre fault PCC voltage. The horizontal
axis of this figure is the ratio of reactance to
resistance of shunt branch in per unit where the base
value is obtained from the ideal condition. This figure
shows that it is possible to decrease the resistance of
the shunt branch (without changing the magnitude of
itsimpedance) in a large range without any
considerable phase-angle jump during fault.
Decreasing Rsh reduces the power loss of the shunt
branch during the short-circuit interval. So its design
becomes simpler.
(11)
whereZsh is the shunt impedance, and ZL,min is the
minimum impedance of load on the protected feeder.
By the use of diodes,IGBTs and small dc reactor
there is a voltage drop on FCL.This results harmonic
distortion on load voltage and power loss in shunt
branch in normal operating conditions.the voltage
drop on power electronic devices is compensated by
considering a dc source in the proposed FCL. So it
reduces the total harmonic distortion (THD) of
voltage waveform.
Benefits of the FCL:
FCLs offer numerous benefits to electric utilities.
For instance, utilities spend millions of dollars each
year to maintain and protect the grid from potentially
destructive fault currents. These large currents can
damage or degrade circuit breakers and other
expensive T&D system components. Utilities can
reduce or eliminate these replacement costs by
installing FCLs. Other benefits include:
1. Enhanced system safety, stability, and
efficiency of the power delivery systems.
2. Reduced or eliminated wide-area blackouts,
reduced localized disruptions, and increased
recovery time when disruptions do occur.
3. Reduced maintenance costs by protecting
expensive downstream T&D system
equipment from constant electrical surges
that degrade equipment and require costly
replacement.
4. Improved system reliability when renewable
and DG are added to the electric grid.
5. Elimination of split buses and opening bustie breakers.
6. Reduced voltage dips caused by high
resistive system components.
7. Single to multiple shot (fault) protection plus
automatic resetting
Figure 6(a) Magnitude of the PCC voltage.
III. DESIGN CONSIDERATIONS
For designing shunt branch parameters, it is
possible to consider the following conditions.
1.
2.
In the ideal case, shunt branch impedance is
equal to load impedance.
When a fault occurs in the protected feeder,
the voltage sag at the PCC will be zero.
International Conference on Electrical Electronics and Computer Science-EECS-9th Feb 2014-ISBN-978-93-81693-54-2
109
Voltage SAG compensation of point of common coupling (PCC) using fault current limiter in three phase lines
Figure 6(b) Phase angle deviation of the PCC.
Figure7. Simulation model of three phase system without FCL
Three single phase sources are taken for
simulation and the combined voltage wave form at
PCC during the three phase fault created at t=0.1 sec
to t=0.2 sec is plotted in Fig.8, Fig.9 shows the
instantaneous power in first phase of the system at
PCC with fault condition.
IV. SIMULINK MODELING AND RESULTS OF FCL
This FCL topology has been implemented
on three phase system and the results are presented in
this section. Three phase system is considered for the
analysis and simulation because it would be more
practical to carry out the analysis on the widely used
three phase sensitive loads in industries.
During the three phase balanced fault
condition, without using the FCL, the voltage sag
appears severely at PCC.when FCL is used it will
reduces the fault current as well as the voltages of the
other feeders are restores to the normal value. The
FCL improves the system reliability and voltage
quality. The system parameters are in Table I. The
simulations
are
obtained
using
the
MATLAB/SIMULINK software.
Figure 8.Three phase voltages at PCC without FCL.
Table I: System parameters
Power
20kv,50Hz,X/R ratio:5
source
Total Impedance:1.608Ω
Source
Side Data Transform
20kv/6.6kv,10MVA,0.1
er
pu
Feeder F1
j0.314Ω
Distributi
on
Feeders
Feeder F2
J0.157Ω
Data
Ldc=0.01H,Rdc=0.03Ω
VDF=3V,VSWF=3V,Im=0.
DC Side
6kA
FCL Data
Switch type: IGBT
Shunt
Lsh=0.08H,Rsh=5Ω
Branch
Sensitive
10+j15.7Ω
load
Load Data
Load Of
15+j31.3Ω
F2
Figure9.Power Waveform at PCC for one phase
Fig. 10.Sshows simulation model of three phase
system with FCL.when the fault is occurs the FCL
inserts large impedance in to the faulted line and
prevents the voltage sag and phase angle jump at the
substation PCC.
I1
Goto2
+
v
-
r
v1
+
l3
i3
V1
Goto1
i
-
AC Voltage Source
l3
i3
l1
Goto2
+
v
-
v1
l1
I1
V1
Goto1
i
-
+
1
Measurements
2
tf1
r
+v e
AC Voltage Source
1
l2
+
i
-
+
-v e
Measurements
2
c
Pulse
Generator
+
i
-
+
i
-
I2
v2
Breaker
i
-
+
I2
l7
i5
l5
V2
Goto3
Goto4
+
v
-
2
1
Breaker
V2
Goto3
c
Pulse
Generator
l4
2
1
l4
i
i1
l2
i
-
i
i1
FCL
tf1
Goto4
+
v
-
v2
+
r1
i
-
l7
i5
l5
AC Voltage Source1
1
2
tf2
r1
AC Voltage Source1
1
2
+v e
l6
i
-
+
i
-
+
-v e
c
c
Pulse
Generator1
I3
2
1
2
1
Breaker1
l8
i2
i4
l6
Pulse
Generator1
i
-
+
i
+
-
Goto5
Breaker1
V3
+
v
-
Discrete,
Ts = 5e-005 s.
Goto6
powergui
v3
I3
Goto5
+
V3
+
v
-
Discrete,
Ts = 5e-005 s.
Goto6
+
i8
i
-
l9
i
-
l11
i8
powergui
v3
l9
l8
i2
i4
FCL1
tf2
r2
l11
AC Voltage Source2
1
2
r2
tf3
AC Voltage Source2
1
2
+v e
tf3
l10
+
l10
+
i
-
l12
i6
i7
c
Pulse
Generator2
1
-v e
FCL2
+
+
i
-
i
-
l12
i6
i7
c
i
-
Pulse
Generator2
1
2
Breaker2
2
Breaker2
Figure10. Simulation model of three phase system with FCL
International Conference on Electrical Electronics and Computer Science-EECS-9th Feb 2014-ISBN-978-93-81693-54-2
110
Voltage SAG compensation of point of common coupling (PCC) using fault current limiter in three phase lines
V. CONCLUSION
In this paper, voltage sag compensation, phaseangle jump mitigation, and fault current limiting
operation were analyzed. The designed FCL is
capable of mitigating voltage sag and phase-angle
jump to acceptable levels. By using the
semiconductor switch in the dc current path instead of
two numbers of Thyristors at the bridge branches, the
FCL will have high speed and consequently, the dc
reactor value is reduced to a lower value.In addition,
the dc voltage source placed in the FCL structure
reduces its THD and ac losses in normal operation. In
general, this type of FCL, with the simple control
circuit and low cost, is useful for the voltage-quality
improvement because of voltage sag and phase-angle
jump mitigating and low harmonic distortion in
distribution systems. In addition to that three phase
power systems are developed with and without the
FCL as well as their behaviors are also observed.
Figure 11.Three phase voltages at PCC with FCL.
REFERENCES
Figure 12.Voltage drop across FCL.
[1] J. V. Milanovicand y. Zhang, “Modeling of Facts devices for
voltage sag mitigation studies in large power systems,” IEEE
Trans. Power del., vol. 25, no. 4, pp. 3044–3052, oct. 2010.
[2] T. J. Browne and G. T. Heydt, “Power quality as an
educational opportunity,”IEEE Trans. Power Del., vol. 23,
no. 2, pp. 814–815, May2008.
[3] N. Ertugrul, A. M. Gargoom, and W. L. Soong, “Automatic
classificationand characterization of power quality events,”
IEEE Trans. PowerDel., vol. 23, no. 4, pp. 2417–2425, Oct.
2008.
[4] M. Abapour, S. H. Hosseini, and M. T. Hagh, “Power quality
improvementby use of a new topology of fault current
limiter,” in Proc. ECTICON,2007, pp. 305–308.
Figure 13.Shunt Current.
[5] M. Brenna, R. Faranda, and E. Tironi, “A new proposal for
powerquality and custom power improvement: Open
UPQC,” IEEE Trans.Power Del., vol. 24, no. 4, pp. 2107–
2116, Oct. 2009.
[6] W. M. Fei, Y. Zhang, and Z. Lü, “Novel bridge-type FCL
based on selfturnoffdevices for three-phase power systems,”
IEEE Trans. PowerDel., vol. 23, no. 4, pp. 2068–2078, Oct.
2008.
[7] E. Babaei, M. F. Kangarlu, and M. Sabahi, “Mitigation of
voltage disturbancesusing dynamic voltage restorer based on
direct converters,”IEEE Trans. Power Del., vol. 25, no. 4,
pp. 2676–2683, Oct. 2010.
Figure 14.DC Side Current.
[8] M. Moradlou and H. R. Karshenas, “Design strategy for
optimum ratingselectionof interline DVR,” IEEE Trans.
Power Del., vol. 26, no. 1,pp. 242–249, Jan. 2011.
[9] Fabio, Tosto; “Voltage Sag mitigation on Distribution
Utilities”, ETEP- European Transaction on Electric power,
Vol. 11(1), pp. 17-21, January/February 2001.
.
[10]
L. E. Conrad, “Proposed chapter 9 for predicting voltage
sags (dips) inrevision to IEEE std. 493, the gold book,” IEEE
Trans. Ind. Appl., vol.30, no. 3, pp. 805–821, May/Jun. 1994.
***
Figure 15.Three phase power.
International Conference on Electrical Electronics and Computer Science-EECS-9th Feb 2014-ISBN-978-93-81693-54-2
111