Power Failure Management
White Paper
June 11th, 2013
Version 1.5
Apacer Technology Inc.
th
4 Fl., 75 Hsin Tai Wu Rd., Sec.1, Xizhi, New Taipei City, 221, Taiwan
Tel: +886-2-2698-2888
Fax: +886-2-2698-2889
Power Failure Management (PFM)
Overview
Solid State Drives (SSD) has generally been recognized as far more reliable and faster in data
transmission than traditional hard disk drives (HDD). Without the mechanical components and magnetic
parts, the NAND Flash based SSD memory devices can take on higher levels of shock, vibration, and
wider range of ambient temperature. At the same time, less heat is generated during operation, making
SSDs the more stable storage device for various applications in industrial, military, enterprise,
communication network, consumer electronics and embedded purposes. Like other electronic devices,
SSDs are vulnerable to power failure issues such as voltage disruptions, power supply fluctuations and
surges. When a power disruption occurs, data in transmission from the HOST to the SSD could be lost or
damaged. Since memory devices are designed to work as the safety deposit for important data, Apacer
PFM becomes critical for SSD.
Apacer PFM ensures data transmission when experiencing unstable power supply. The controller will
cache multiple write-to-flash cycles ; which requires several milliseconds to complete. When the supplied
voltage dips below the required percentage, the flash controller will be triggered by a low power detection
signal. Then the firmware will communicate with the controller to flush all the data into the cache of Flash
storage area.
State Tracking & ECC Algorithm for Data Integrity
If the write-to-flash cycles cannot be completed during the remaining time held up by the capacitor, data
in the cache will lost. The controller will track the write command state and when power restores, it
retrieves the mapping table and successfully resumes programmed data before power failure occurred .
The controller will scan all operational blocks to build/compare mapping table every time the power is on
and keeps track of the sector/block states for valid data., In order to prevent mapping table from damage,
there is a state-tracking mechanism to record and re-build the mapping table. It will also check each
block points, from logical to physical address with the ECC engine to ensure data / table accuracy.
Link Table Rebuilding in Power Failure Management Process
Link Table is a built-in block (usually a SRAM block) inside the controller that provides logic to physical
address translation. . While the data is under programming process, the controller is programming the
corresponding logical block address with firmware information in the spare bytes.
Logical
Physical/Actual
Translates logical to physical addresses
Link Table
Data / Firmware Info / Parity
Host / OS
Controller
Physical Flash block address
Logical block
Address
NAND flash devices are designed to cache multiple write-to-flash cycles to securely store data when
power disruption occurs. Since the NAND flash is non-volatile memory, the controller can read every
NAND flash block in sequence and retrieve the logical address mapping to rebuild the link table as soon
as the power supply is resumed.
Succeed
Power Resumed
Rebuild complete
Controller reads block
address information to
rebuild the Link Table
Fail
Repeat reading the block
address information
Data Preservation Mechanism
Primary block is the main and initial storage space for data. However, since NAND flash data cannot be
overwritten, a Subsidiary block is needed whenever an update is made for the data stored in the Primary
block. Take the following figure for instance. Page s1, s2 and s3 of the Subsidiary block are the updated
data for Page p1, p2, and p3 for the Primary block. If, a power disruption occurs when a data update is
taking place at Page s4 on the Subsidiary block then operation is stopped and the data will be invalid and
inaccurate.
In this case, the controller will read Page s4 with the ECC engine and detect the ECC error on page
S4.As a result, it will merge both the Primary and Subsidiary blocks to form a Destination block by
combining the valid parts of data. The controller will extract Page s1, s2 and s3 from the Subsidiary block
as they are the valid updated data before the power disruption occurred. Since Page s4 is invalid data
due to power failure, the controller will take Page p4 from the Primary block to form a complete
Destination block, which will become the “new” Primary block. The Subsidiary block and the “old” Primary
block will be put into the spare block
A sudden power failure scenario
Page p1
Page s1
Page p2
Page s2
Page p3
Page s3
Page p4
Page s4
Last Page
Last Page
Suddenly, a power failure
occurs during operation at
Page s4
Data in s4 is invalid
and ECC error is
detected
Form the Destination block
Primary block
Subsidiary block
Destination block
Page p1
Page s1
Page s1
Page p2
Page s2
Page s2
Page p3
Page s3
Page s3
Page p4
+
Page s4
=
Page p4
From Primary
block
Last Page
Last Page
*Page p4 on Primary block is extracted to
make up the Page s4 on Subsidiary block
A “new” Destination
block is formed.
The “old” Primary &
Subsidiary blocks are
put in spare blocks
Revision History
Date
Description
1.0
May 5, 2009
Official release
1.1
May 21, 2009
Updated power failure test details
1.2
May 26, 2009
Updated flow charts
1.3
June 1, 2009
Refined flow charts
November 21st, 2012
Added Link Table Rebuilding,
Management
Mechanism, and
Tracking & ECC sections
Revision
1.4
1.5
Remark
Power
State
Revised the Link Table Rebuilding and state
tracking sections
June 11th, 2013
Apacer Technology Inc.
th
4 Fl., 75 Hsin Tai Wu Rd., Sec.1
Xizhi, New Taipei City, 221, Taiwan
Tel: +886-2-2698-2888 Fax: +886-2-2698-2889
www.apacer.com
Copyright © 2013 Apacer Technology Inc. All Rights Reserved.
Information in this document is subject to change without prior notice.
Apacer and the Apacer logo are trademarks or registered trademarks of Apacer Technology Inc.
Other brands, names, trademarks or registered trademarks may be claimed as the property of
their respective owners.