A COMPARATIVE STUDY OF THREE-PHASE AND SINGLE-PHASE PLL
ALGORITHMS FOR GRID-CONNECTED SYSTEMS
Rubens Marcos dos Santos Filho
Paulo F. Seixas, Porfírio C. Cortizo
Centro Federal de Educação Tecnológica - CEFET-MG
Coord. Eletrônica - Av. Amazonas 5253
Belo Horizonte - MG - CEP. 30.480-000 - BRASIL
Fax: +55.31 3319.5135 - e-mail: rsantos@deii.cefetmg.br
Universidade Federal de Minas Gerais - UFMG
EE.UFMG-DELT - Av. Antônio Carlos 6627
Belo Horizonte - MG - CEP. 31.270-901 - BRASIL
Fax: +55.31 3499.5480 - e-mail: paulos@cpdee.ufmg.br
Abstract – This work presents a comparative study of
two three-phase and five single-phase PLL structures. It
is shown through analytical and simulation results that
the three-phase SRF PLL and the instantaneous power
based three-phase PLL behave exactly equal, what is
corroborated by tests of voltage and frequency
disturbances, harmonic injection and line unbalance.
However, the power PLL algorithm is more efficient
since it requires fewer computations in its phase detector.
The five different types of single-phase PLL structures
are briefly reviewed and their performances are
evaluated under several line disturbances.
Index terms – Phase-locked loop (PLL), synchronous
reference frame (SRF), adaptive linear combiner (ALC).
I. INTRODUCTION
The correct phase angle is a very important information in
grid-connected systems such as UPS, controlled rectifiers,
active filters, dynamic voltage restorers and also in the
emerging distributed generation systems such as eolic and
photo-voltaic. To estimate the phase angle open loop and
closed loop methods are available [7]. The closed loop
methods are commonly known as Phase-Locked Loops or
PLLs. The figures of merit of a PLL are the steady state
phase angle error, speed of response to phase, frequency and
voltage amplitude disturbances, harmonic rejection and line
unbalance in the case of three-phase systems.
Generally, the line frequency varies within a limited range
even in isolated systems, and its rate of change is limited by
generators’ mechanical inertia. But when (unbalanced) grid
faults occur, equipments are subjected to phase angle jumps
and voltage sags [13]. The unbalanced situation may last for
several cycles before the fault is cleared.
Thus, the development of robust synchronizing algorithms
is needed for the growing performance requirements of
modern grid-connected equipments. In recent years, several
PLL algorithms have been developed and presented in the
literature [1]-[15].
The main objective of this work is to briefly review and
evaluate some PLL algorithms for grid-connected systems
under diverse line disturbances. In Section II, analytical
results of the three-phase synchronous reference frame PLL
structure (dqPLL) [1] and three-phase instantaneous power
based PLL (pPLL) [2]-[4], will be presented. Section III will
present five different single-phase structures. The first two
are based on the SRF method, the third is based on the
instantaneous power PLL, and the two later are based on
adaptive filter theory.
II. THREE-PHASE PLLS
In the following subsections the block diagrams and
equations of the phase detector of the two three-phase PLL
structures will be shown.
A. Three-Phase SRF PLL (dqPLL)
The block diagram of the dqPLL is shown in Fig. 1 [1].
The grid voltage samples are va, vb and vc. Comparing this
diagram to the conventional PLL used in telecommunications, it can be seen that the PI controller is analogous to
the low pass filter, the integrator is analogous to the voltage
controlled oscillator, and the SRF transformation blocks
scheme is analogous to the phase detector. Its working
principle relies on regulating to zero the direct component of
the rotating frame. This component is calculated using the
estimated phase angle θˆ , closing the loop.
kp
+
Vd* = 0
-
ωff
+
ki
s
+
+
+
Vd
1
s
θ̂
dq
αβ
Vq
va
vb
vc
Vα
abc
Vβ
αβ
Fig. 1. Three-Phase SRF PLL
Assuming balanced and harmonic free input voltages, the
expression of the d-axis component which is feed to the PI
controller is:
Vd = Vα sinθˆ + Vβ cosθˆ
(1)
Vd = V cos θ sin θˆ − V sin θ cosθˆ
(2)
Vd = − V sin(θ − θˆ )
(3)
or
leading to:
where: Vd is the phase detector output signal;
V is the amplitude of the input voltages;
θ is the angle of phase A;
θ̂ is the estimated angle.
Using the same procedure for the q-axis component Vq,
we find its amplitude:
Vq = V cos(θ − θˆ )
(4)
When θ̂ approximates θ , Vd in (3) will approximate zero
and the PLL will be locked. In this situation, according to
(4), Vq will be equal to the input voltage amplitude.
B. Instantaneous Power Three-Phase PLL (pPLL)
The block diagram of the three-phase pPLL is shown in
Fig. 2 [2]-[4]. The working principle of its phase detector is
based on regulating to zero the fictitious instantaneous threephase power. This power is calculated using the voltages
samples and the fictitious currents ia and ic depicted in Fig. 2
and generated through the estimated angle θ̂ .
kp
p*=0 +
p
ωff
+
ki
s
-
+
+
+
ic
+
+
ia
va
vb
vc
1
s
θ̂
The kp and ki gains determine the speed of response and
disturbance rejection of the PLL in a direct relation.
However, there is a trade off between noise, harmonic and
voltage unbalance rejection and speed of response. The
higher the gains, the worse the noise, harmonic and line
unbalance rejection. The adequate bandwidth will depend on
the application purposes.
The following simulation results have been obtained for
the discretized three-phase dqPLL and pPLL. There have
been used 64 samples per line period or 3840Hz. The input
voltages amplitude and frequency were normalized at
1p.u./60Hz. The same PI gains were set for both PLLs:
kp=200V-1s-1, ki=20,000 V-1s-2. The PI gains were adjusted
such that a suitable settling time and damping and an
acceptable harmonic rejection were obtained. The 3/2 factor
has been included in the dqPLL.
1) Phase Angle Jump Response – The PLL response to a
30 degrees phase angle step at t=1s is shown in Fig. 3. Both
PLLs behave exactly equal as pointed out by (3) and (7) with
a settling time of about 40ms and zero steady-state error.
− cos (θˆ + 120 )
− cos(θˆ )
+
+
Fig. 2. Three-phase pPLL
Assuming balanced and harmonic free input voltages, the
expression of the phase detector output signal p which is fed
to the PI controller can be found by writing the instantaneous
three-phase power expression:
p = v a i a + vb i b + vc ic
(5)
Since i a + i b + ic = 0 , (5) can be rewritten as:
p = ( v a − v b ) i a + ( vc − v b )i c
(6)
Fig. 3. Response of the three-phase pPLL and dqPLL to a 30degrees phase-angle jump in the input voltages.
2) Frequency Step Response – Fig. 4 shows the response
of the three-phase PLLs to a +5Hz frequency step at t=1s.
Although the line utility frequency commonly changes in a
narrow range even in isolated systems and its rate of change
Substituting v a = V sin( θ ) ,
and
v b = V sin( θ − 2π / 3 )
v c = V sin( θ + 2π / 3 ) in (6) and making the simplifications
we obtain:
3
p = − V sin(θ − θˆ )
2
(7)
C. Simulation Results and Performance Comparison
The phase detector expressions of both three-phase PLLs
depend on input voltage amplitude and phase. Equations (3)
and (7) are similar, except for the factor 3/2 in (7). As they
were obtained for balanced and harmonic free grid voltages,
the following tests will evaluate the PLLs’ behavior under
non ideal and transient situations.
Fig. 4. Response of the three-phase PLLs to a +5Hz frequency step.
is limited due to the generators’ inertia, the frequency step
test intends to give an idea of systems’ speed and adaptivity.
The overlap of both responses can be seen again. The PLLs
achieve zero error in steady-state after the frequency change.
3) Harmonic Rejection – The presence of harmonics in the
line voltages leads to oscillating phase angle errors at PLLs’
output with near to zero average value. The test was
performed applying one harmonic at a time. The peak phase
angle error obtained for both PLLs as a function of harmonic
order and amplitude is shown in Fig. 5. As stated before,
both PLLs behave equally. It can be seen that higher
harmonic frequencies lead to lower errors.
The inability of the dqPLL to accurately track unbalanced
line voltages is well known in the literature. Several schemes
have been proposed in order to improve the unbalance
rejection of the dqPLL [7],[11],[14]. Those schemes usually
compute the instantaneous positive sequence component of
the input voltages and feed them to the dqPLL. The
simulation and analytical results obtained suggest that such
schemes are also applicable to the three-phase pPLL and
would produce the same results.
5) Computational Load – Table I displays the number of
computations needed in the phase detector stages of the
three-phase dqPLL and pPLL. The PI and the integrator were
not included because they are equal in both PLLs. As can be
seen, the phase detector of the three-phase pPLL is more
efficient since it requires fewer computations. Actually,
effective computational load of the PLLs algorithms will
depend on used processor’s architecture.
Table I
Computational Load of Three-Phase Algorithms
Number of Operations in the Phase Detector
Algorithm
Mult.
Addition
Trigon.
Total
dqPLL
7
4
2
13
100%
pPLL
2
3
2
7
54%
III. SINGLE-PHASE PLLS
Fig. 5. Peak phase angle error of the three-phase PLL in the
presence of harmonic distortion in input voltages.
4) Phase Unbalance Response – This test has been
performed using the ANSI/IEEE standard 141-1986 which
quantifies the three-phase unbalance as the relative
maximum individual line rms voltage deviation in relation to
the average rms value of the three phases:
Unbalance% =
(
)
a ,b ,c
max |VRMS
− VRMS |
× 100%
VRMS
(8)
where VRMS is the average rms value of the three phases.
Fig. 6 shows the peak and average phase angle errors of
both PLLs as a consequence of line unbalance, which has
been calculated through (8).
Five different single-phase PLL structures have been
studied: two single-phase versions of the three-phase dqPLL
(PLL-dqFIFO and PLL-dq-Park) [5],[6]; one single-phase
version of the three-phase pPLL (pPLL) [15]; the enhanced
PLL (EPLL) [7],[8]; and finally one PLL which employs an
adaptive filter to estimate line phase angle (PLL-ALC) [12].
A. Single-phase Transport Delay PLL (PLL-dq-FIFO)
Fig. 7 shows the block diagram of the PLL-dq-FIFO
[5],[6]. Its working principle is the same of its three-phase
version. It uses a first-in-first-out register to build the
quadrature component to the dq transformation. Due to the
fixed length delay, it is not able to adjust to input voltage
frequency deviations, leading to phase angle errors as will be
shown in the simulation results. Other alternative to generate
the quadrature component is the Hilbert transformer, but it is
very difficult to implement in low frequency (50/60Hz).
kp
+
Vd* = 0
ki
s
-
ωff
+
+
+
1
s
+
Vd
Vq
dq
αβ
Vβ
PLL input
Fig. 6. Peak and average phase angle errors of the three-phase
PLLs as a function of input voltage unbalance.
Delay
1/4 Cycle
(FIFO)
Vα
Fig. 7. Single-phase transport delay PLL
θ̂
B. Single-phase Inverse Park PLL (PLL-dq-Park)
Fig. 8 displays the block diagram of the single-phase dq
inverse Park based PLL [5],[6]. It is also based on frame
orientation. The quadrature component Vα is build through
the inverse Park transformation.
kp
u +
e
+
^
Vd* = 0
+
-
+
+
+
Vd
1
ps + 1
Vα
Vβ
PLL input
αβ
dq
C. Single-phase Power PLL (pPLL)
Fig. 9 displays the block diagram of the single-phase pPLL
[15]. As its three-phase version, it is also based on annulling
the fictitious instantaneous power. Assuming purely
sinusoidal input voltage in the form V sinθ , the expression
of the phase detector output signal is:
p = −V sinθ cosθˆ
system’s output (the desired signal), as depicted in Fig. 11. In
the PLL context, the desired signal y(t) is the grid voltage.
The estimated signal ŷ(t) is built with the estimated phaseangle, as well as the inputs x(t) to the filter.
ŷ(t) (estimated signal)
Adaptive Filter
(9)
e(t)
or
e
+
-
2nd order
filter
State Fbk.
Controller
x(t)
(10)
y(t)
System
(desired signal)
As pointed out by (10), there is a strong drawback to this
structure: the product of input voltage and “virtual” current
has a second harmonic component which has to be filtered
out. Thus, a low pass filter with low cutoff frequency is
needed, slowing down system’s speed. The adopted approach
in the performed simulations was to use the state feedback
technique to allocate closed loop poles and hence system’s
dynamics, as presented in [15].
p*=0
+
-
V
V
p = − sin(θ − θˆ ) − sin(θ + θˆ )
2
2
ωff
x2
cos
x2
reconstructed (or estimated) modifying the gains of a linear
combiner as a function of an error e(t), which in turn is the
difference between the estimated signal ŷ(t) and the
Fig. 8. Single-phase inverse Park PLL
x1
sin
This PLL is based on adaptive filter theory. Basically, it
reconstructs in real time the fundamental component of the
input signal by estimating its amplitude, phase and frequency
through the steepest descent algorithm. In other words, this
PLL has a non-linear phase detector. The gain K controls the
convergence speed of the estimated amplitude  .
Roughly speaking, the adaptive filter theory is based on
the idea that an output signal y(t) of a system can be
αβ
1
ps + 1
x1
+ ω̂
+
Fig. 11. Adaptive filter structure
E. Single-phase Adaptive Linear Combiner PLL (PLL-ALC)
Fig. 12 displays the block diagram of the PLL-ALC, which
is also based on adaptive filter theory [12].
kp
W 2* = 0
1
s
+
ki
s
-
θ̂
ωff
+
+
+ ˆ&
θ
+
u(t)
is(t)
1
s
W2
W12 + W22
x3
x1
W1
PLL input
θ̂
Fig. 10. Single-phase Enhanced PLL
dq
Vq
1
s
+
θ̂
1
s
+ ˆ&
θ
+
K
s
ωff
ki
s
+
ki
s
A
kp
ωff
PLL input
sin
+
− cos(θˆ )
+
x2
W2
cos
Fig. 9. Single-phase power PLL
PLL input
D. Single-phase Enhanced PLL (EPLL)
Fig. 10 displays the block diagram of the EPLL [7],[8].
u
-
e
Adaptation Algorithm
+
Fig. 12. Single-phase Adaptive Linear Combiner PLL
θ̂
The filter inputs x1 and x2 are built with the estimated
phase angle θ̂ , what is analogous to the EPLL scheme in Fig.
10. The linear combiner gains W1 and W2 are updated on-line
using the delta rule. The PI controller regulates the gain W2
to zero. Thus the W1 gain becomes equal to the input voltage
amplitude when θ̂ equals θ. The normalizing block which
computes W12 + W22 improves transient response to voltage
2) Phase-Angle Jump Response – Fig. 14 shows the
results for this test, and Table III shows the ISE of all five
responses. The pPLL has the slowest response due to its filter
with small cutoff frequency. PLL-dq-FIFO has the smallest
undershoot, and PLL-dq-Park has the smallest settling time.
disturbances but it is not essential.
F. Simulation Results and Performance Comparison
All single-phase PLL were discretized with a sample rate
of 64 samples per 60Hz cycle or 3840Hz. The same PI gains
were set to the PLL-dq-FIFO, PLL-dq_Park, and EPLL:
kp=200V-1s-1, ki=20,000V-1s-2. Half this value had to be set to
the PLL-ALC PI controller due to stability issues. The EPLL
gain K was set to 200. The pPLL filter was implemented by
two cascaded first order filters with cutoff frequency of
24Hz, resulting in 28dB of attenuation at 120Hz. The state
feedback gains were set so that the closed loop poles were at
15Hz and 20Hz with optimum damping factor. In the dqPLL-Park the cutoff frequencies of the two first order filters
were set to 120Hz. In the PLL-ALC the convergence gain α
of the adaptation algorithm was set to 0.25.
1) Voltage Sag Response – Fig. 13 shows the simulation
results for this test. It can be seen that the PLL-dq-FIFO has
the best response to voltage disturbances. The closed loop
poles chosen to the pPLL led to a noticeable oscillation in the
phase angle error in steady state, though smaller than 0.5
degree peak-to-peak. The PLL-dq-Park presented the highest
overshoot with the shortest settling time. Table II shows a
more objective comparison criterion of all five responses
through the ISE – integral of square error index.
Fig. 14. Single-phase PLLs responses to a phase-angle jump of 30
degrees
Table III
Phase-Angle Jump Test ISE – Single-Phase Algorithms
ISE – Integral of Square Phase-Angle Error
Algorithm PLL-dq-FIFO PLL-dq-Park pPLL EPLL
ISE
3.96
3.18
23.3%
18.7%
16.96
5.19
100% 30.6%
PLL-ALC
7.10
41.8%
3) Frequency Step Response – Fig. 15 shows the
simulation results for this test. As can be seen, PLL-dq-FIFO
can not deal with frequency deviations due to its fixed delay,
which have been adjusted to the line nominal frequency.
Again, the pPLL presented the slowest response but zero
steady state error. The best response was achieved by the
PLL-dq-Park, as indicated in Table IV.
Fig. 13. Single-phase PLLs responses to a voltage sag of 30%
Table II
Voltage Sag Test ISE – Single-Phase Algorithms
ISE – Integral of Square Phase-Angle Error
Algorithm PLL-dq-FIFO PLL-dq-Park pPLL
ISE
EPLL
PLL-ALC
0.12
1.12
0.04
0.28
0.63
10.7%
100%
3.5%
25%
56.2%
Fig. 15. Single-phase PLLs responses to a frequency step of +5Hz
Table IV
Table V
Frequency Step Test ISE – Single-Phase Algorithms
Computational Load of the Single-Phase Algorithms
Total Number of Operations
ISE – Integral of Square Phase-Angle Error
Algorithm PLL-dq-FIFO PLL-dq-Park pPLL EPLL
ISE
PLL-ALC
Algorithm
Mult
Add.
Trig.
Div
Shift
Total
%
5.53
0.62
53.5
1.85
2.25
PLL-dq-FIFO
2
2
2
0
2
8
36%
10.3%
1.2%
100%
3.5%
4.2%
PLL-dq-Park
13
7
2
0
0
22
100%
4) Harmonics Response – Fig. 16 shows the time response
to 5% 3rd harmonic injection in the line input voltage. In
some responses there is a dc error superimposed to the
oscillating phase-angle error.
pPLL
9
7
1
0
0
17
77%
EPLL
4
3
2
0
0
9
41%
PLL-ALC
14
7
2
2
0
38*
172%
* Division has been weighted by a factor of 10.
IV. CONCLUSIONS
Fig. 16. Single-phase PLLs responses to 5% 3rd harmonic injection
in the input voltage
Fig. 17 shows how each PLL behave in presence of the
3rd, 5th and 7th harmonics. The PLL-ALC has the lowest
sensitivity (degrees of deviation per harmonic %).
In this work, it was shown that the phase detector stage of
the two main three-phase PLL structures for grid-connected
systems found in the literature have practically the same
equation, leading to identical behavior under line
disturbances, harmonics and line unbalance. Furthermore, the
three-phase power PLL algorithm is more efficient from the
computational point of view, demanding about half the
number of calculations on its phase detector stage. Although
not tested in this work, the simulation and analytical results
suggest that the positive sequence detection schemes used in
the traditional three-phase SRF PLL are also applicable to
the three-phase power PLL and would produce the same
results.
Five different types of single-phase PLLs found in the
literature have been briefly reviewed and its simulation
results have been presented. The single-phase power PLL
algorithm presented the slowest responses to frequency and
phase disturbances but it is the stiffest to voltage sags and
harmonics due to the low cutoff frequency of its filters. The
transport delay PLL requires the lowest computational effort,
followed by the EPLL. The PLL-ALC is the heaviest
algorithm from processing time viewpoint, but is less
sensitive to harmonics and so fast as the EPLL and PLL-dqPark.
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Fig. 17. Single-phase PLLs sensibilities to harmonics
5) Computational Load – The total number of calculations
for each single-phase PLL algorithm is shown in Table V.
The normalizing block was not considered in the PLL-ALC
computational load, and the division operation has been
weighted by a factor of 10 due to its inherent implementation
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