AN-1011 Defining Maximum Operating Junction Temperature Application Note AN-1011: Defining Maximum Operating Junction Temperature (TJ) Applications Department, APD Semiconductor, San Jose CA Introduction There are three main factors that determine the maximum operating junction temperature (TJ) of a diode. They are the following: (1) Melting Temperature of the Device Materials (2) Maximum Thermal Runaway Temperature (3) Reliability Considerations, including High Temperature Operating Life (HTOL) and High Temperature Reverse Bias (HTRB) 1) Melting Temperature of Device Materials The melting point of both the material used for the molding compound and the material used for the solder during the die-attached must be higher than the maximum operating junction temperature (TJ). The lower of the two melting points will be the upper limit to the maximum operating junction temperature (TJ). 2) Maximum Thermal Runaway Temperature Thermal runaway occurs when the reverse power exceeds the diode’s capability to dissipate heat at the same rate it is generated. The failure mode is defined at the point where the heat generated is greater than the heat dissipated, thus eventually destroying the barrier of the diode. This point is defined as the maximum thermal runaway temperature. The thermal runaway test is performed by applying a reverse voltage equivalent to the maximum rated blocking voltage, VR, to the diode. For a device in a TO-220 package, a standard vaned heatsink1 is mounted on the device. The device under test (DUT) is then placed in a temperature oven as the temperature is increased incrementally. The device will have to withstand the reverse power at the ambient temperature for a period of 20 minutes and show a stable leakage before the device can qualify for that junction temperature. This test is continued until the device reaches an ambient temperature where thermal runaway occurs in the device. 1 Standard heatsink size of 2cm x 3cm x 0.2cm November 2005, Rev 1.0 Page 1 of 2 AN-1011 Defining Maximum Operating Junction Temperature Application Note 3) Reliability Considerations (A) High Temperature Operating Life (HTOL) HTOL test is used in determining if the device can reliably withstand the forward and reverse power generated at the rated maximum operating junction temperature for a time period of 1000 hours. A 50% duty cycle pulse is used at the rated output current and at the rated blocking voltage. A sample waveform of the HTOL test is illustrated in Figure 1. The final forward voltage (VF) and the final reverse leakage (IR) of the DUT are measured at 25C to determine if it is still within the maximum specifications. Figure 1. Diode Operating Life Waveform (B) High Temperature Reverse Bias (HTRB) HTRB test consists of applying a DC voltage that is 80% of the maximum rated blocking voltage at the maximum operating junction temperature for a time period of 1000 hours. The final forward voltage (VF) and the final reverse leakage (IR) of the DUT are measured at 25C to determine if it is still within the maximum specifications. Information furnished is believed to be accurate and reliable. However, APD Semiconductor assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of APD Semiconductor. Specifications mentioned in this publication are subject to change without notice. This publication superseded and replaces all information previously supplied. APD SEMICONDUCTOR products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the APD SEMICONDUCTOR product could create a situation where personal injury or death may occur. APD logo and SBR are registered trademarks of APD Semiconductor. All other names are the property of their perspective owners. © 2005 APD Semiconductor – All rights reserved www.apdsemi.com November 2005, Rev 1.0 Page 2 of 2