Signal Integrity Tools for
Multi-Gigabit/s Chip-Chip
Data Links
Herman Westra
Application Engineer
Agilent EEsof EDA
herman_westra@agilent.com
Copyright 2012 Agilent Technologies, Inc.
Agilent EEsof EDA
• EDA Division of Agilent Technologies
• Focused on design tools for the physical layer (signal path) of
communications products
• Strong synergies with Agilent T&M equipment divisions
• R&D sites in US, Europe and Asia
• WW Direct sales & support organization
•> 65% RF EDA market share
1985
HP's first commercial
RF/uW EDA product (MDS)
(Gary Smith EDA)
1999
2005
2008
Agilent starts as an
Acquisition of
Introduction of
independent company Eagleware-Elanix SystemVue & EMPro
1993
Acquisition of EEsof
2006
Acquisition of Xpedion
and FDTD simulator IP
2011
Introduction of
ADS OA
Copyright 2012 Agilent Technologies, Inc.
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Agilent EEsof HSD Strategic Intent
Provide the industry’s premier HSD EDA software.
– Integration of premier simulation technologies for microwave effects (which are
inherent in the multigigabit/s regime), tuned to the needs of high speed digital designers.
Key Technology Investments
IC Model Builder:
SystemVue
HSD Designer:
ADS/EMPro
Physical Designer:
Constraint-based tool e.g.
Allegro, Expedition,
CR-5000 etc.
Copyright 2012 Agilent Technologies, Inc.
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Success Story: Why Did Cisco Choose ADS For
Signal Integrity?
“Our systems include multi-gigabit per second chip-to-chip
serial links across PCBs and backplanes. We selected ADS
because it lets us couple simulations at the channel-, circuit-,
and physical-levels with measured data from the instruments.
“The resulting workflow requires fewer respins of the physical
prototypes. We get fewer unwanted surprises, and get to market
quicker.”
-- Straty Argyrakis, CPP Integrity Engineer, Cisco Systems
Copyright 2012 Agilent Technologies, Inc.
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Trends in SI
“There are two kinds of engineers. Those that have signal integrity problems and those that will.”
-- Eric Bogatin
In a given company, signal integrity seems to go through several phases:
100s of Megabit/s: Constraint-based layout causes few problems
~1 Gigabit/s: Firefighting mode: post-layout board spins and/or EM
simulations to fix SI problems
Multi-Gigabit/s: Predictive design mode: Optimize pre-layout channel design,
de-emphasis, equalizers, to mitigate the impairments before layout.
Integrated approach to SI/PI/EMI/EMC issues both pre- and post-layout.
Our focus, our value.
Copyright 2012 Agilent Technologies, Inc.
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Organization of this presentation ...
• Pre-layout: Optimize Tx/Rx settings, stack up, controlled impedance lines,
and via design. Use parameters in constraint manager of autorouter of your
enterprise PCB tool
• Post-layout: Reuse the pre-layout Tx/Rx models and simulator set up but
swap out pre-layout channel model with an EM-based model of the
candidate artwork before committing to fabrication. Verification and adjust.
• Methodology: Closing the loop.Verification whith measurements. Improve
modeling skills. (Determine the most important aspects to model. What
level of accuracy is sufficient. Check model assumptions. E.g. PCB
properties.)
• A demo when time permits
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High Speed Digital Link Design
Design Space Exploration
& Optimization
Layout
Place Route DRC
pre-layout
Layout
verification
post-layout
(Proto)
Manufacturing
HW
Verification
Copyright 2012 Agilent Technologies, Inc.
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High Speed Digital Link Design
Design Space Exploration
& Optimization
Layout
Place Route DRC
pre-layout
Layout
verification
post-layout
(Proto)
Manufacturing
HW
Verification
Copyright 2012 Agilent Technologies, Inc.
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Pre-layout design space exploration
BER < 1.0E-12
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Challenges in pre-layout design space exploration
• Large multi-dimensional design space: Tx, channel, Rx
• Design goal is an extremely low BER (10-10 - 10-12)
 Megabit eye diagrams required for this figure of merit
 Millions of simulation time steps
• BER at each point affected by:
- Jitter (ISI, DCD, PJ & RJ)
- Channel impairments: attenuation, reflections, crosstalk
- Tx and Rx equalizers
• Some components specified in frequency-domain and/or band-limited
 Beware of causality and passivity translation errors
• Traditional SPICE-like transient simulation requires hours per megabit
 Optimization of Tx, channel, and Rx characteristics is impractical
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Why You Can’t Use SPICE or Traditional IBIS Flow
For Multigigabit/s SERDES
• Circuitry is too complex
– 10’s k transistors in the logic block
• Design space is just too large
– Tx settings × Channel design ×
Rx setting = Thousands of
simulations to find the optimum
eye height/width
Sub-gigabit/s yesterday
Multigigabit/s today
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Why You Can’t Use SPICE or Traditional IBIS Flow
For Multigigabit/s SERDES
• Circuitry is too complex
– 10’s k transistors in the logic block
• Design space is just too large
– Tx settings × Channel design ×
Rx setting = Thousands of
simulations to find the optimum
eye height/width
Sub-gigabit/s yesterday
Multigigabit/s today
Introducing the Agilent ADS Channel Simulator ...
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Channel Simulator: Describing the channel
Integrate layout
artwork into
schematic
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Pre-Layout High Frequency Component Models
Multi-Layer Transmission Lines
Vias T-Lines
Cross-Overs
Bends
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Pre-Layout Multi-Technology Custom EM Models
USB 3.0 Connector
StdA_SSTXGND
StdA_SSTX+
3D View of Design
StdA_SSRX−
On Board
Differential line
StdA_SSRX−
Backside
differential line
Vias
SATA Connector
Differential Lines
(Receive)
Substrate: 4/5 Layer Board
Differential Lines
Vias
(Transmit)
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Channel Simulator: Describing the channel
Integrate layout
artwork into
schematic
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Channel Simulator: Describing the transmitter
Integrate layout
artwork into
schematic
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Channel Simulator: Describing the transmitter
Integrate layout
artwork into
schematic
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Channel Simulator: Describing the transmitter
Integrate layout
artwork into
schematic
Copyright 2012 Agilent Technologies, Inc.
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Channel Simulator: Describing the transmitter
Integrate layout
artwork into
schematic
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Channel Simulator: Describing the transmitter
Integrate layout
artwork into
schematic
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Channel Simulator: Describing the Receiver
Integrate layout
artwork into
schematic
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Channel Simulator: Describing the Receiver
Integrate layout
artwork into
schematic
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Channel Simulator: Simulation output
Integrate layout
artwork into
schematic
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Channel Simulator: Bit-by-bit and Statistical Modes
Integrate layout
artwork into
schematic
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Channel Simulator: Easily 'tune' channel parameters
Integrate layout
artwork into
schematic
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Channel Simulator: under the hood
Impulse response is
calculated using a
short, traditional
transient simulation
Bit by bit mode : Superposition of bits
ISI
Statistical mode : Statistical techniques
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Causal Models from S-Parameters
• Causal condition: Kramers-Kronig Relation
v( ' )
u ( )  P 
d '
'
    
1  u ( ' ) '
v( )   P 
d
     '
h( )  u ( )  jv ( )
• Real and imaginary parts are not
independent. They are Hilbert
transforms of each other.

1
• Hilbert integrals involves the entire
spectrum
 and  are complex (Laplace domain) frequency
• Truncation in band-limited spectrum breaks K-K relations. Rigorous approach
is required to restore causality in time domain simulations. (Patented)
Non-rigorous
Reference
S-parameter
0.8
0.6
0.4
0.2
Reference
S-parameter
1.0
Voutv, V
Voutv_S, V
Voutv, V
Voutv_S, V
1.0
Rigorous
1.2
1.2
0.8
0.6
0.4
0.2
0.0
0.0
-0.2
-0.2
0
5
10
15
time, nsec
20
25
30
0
5
10
15
20
25
30
time, nsec
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Multilevel Transmission Lines Models in ADS are
Base-delay Causal
Base-delay = length/speed of light in the dielectric
ADS transmission lines models use a causal frequency-dependent loss
formulation for dielectrics (Svensson-Djordjevic model)
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Small Things Can Make a Big Difference
unit interval
Step responses
Blue: Non-causal
Red: Causal
• Non-causal simulation “takes off” too early
– Before the bit “arrives”
– Eye appears more open than reality
• Causal simulation gives correct eye opening
HIT February
30
Agilent Confidential
Non-Causal Model Underestimates Eye Closure
Incorrect Eye
Measurements
with Non-Causal
Model
Correct Eye
Measurements
with Causal Model
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Design space exploration example:
Determine the Optimum Value of De-emphasis
Optimum de-emphasis value: 5.6 dB
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Example of a more elaborate design analysis
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Example of a more elaborate design analysis
PCIe channel including EM model for IC-package
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Measurement-hardened Methodology Validation
and Refinement
Key Technology Investments
IC Model Builder:
SystemVue
HSD Designer:
ADS/EMPro
Physical Designer:
Constraint-based tool e.g.
Allegro, Expedition,
CR-5000 etc.
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Verified Versus Measurement
1) Time-domain
TycoTM
XAUI Backplane
Measured TDR waveform
(blue) corresponds exactly to
ADS simulation (red)
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Verified Versus Measurement
2) Frequency-domain, time-domain “round trip”
S-parameters
from VNA
FFT
HDMI cable (7 meters):
Eye diagram
Measured (pink) and simulated
(blue) response correspond exactly
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How about simulation with my specific FPGA,
DAC, DDR3 device?
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Solution: Channel Simulator with IBIS AMI models
• IBIS is “Input/output Buffer Information Specification”
• AMI is “Algorithmic Modeling Interface”
• IBIS Open Forum added the AMI flow as an alternate to the traditional
(SPICE-based) flow in IBIS version 5.0
– http://www.eda-stds.org/ibis/
• Agilent supports IBIS 5.1:
– Two Agilent experts serve on IBIS Open Forum
– SystemVue for AMI model builders (typically IC vendors)
– ADS for model users (both IC vendors and OEMs)
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Traditional
flow
versus
AMI
flow
IBIS Compliant
Transient Simulator
(SPICE)
IBIS Compliant
Channel Simulator
Traditional *.ibs text
file
Traditional *.ibs text
file plus ref. to…
Signal processing logic
block
Examples:
• Tx pre-emphasis
• Rx adaptive Eq
• Rx CDR
*.ami header file
(text)
*.dll or *.so
executable
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What Does IBIS AMI Flow Offer?
Portability & IP Protection: One IC model
runs in many EDA tools, without the need for
non-portable, proprietary encryption keys
Interoperability: IC Vendor AIC Vendor B
Performance: Ultralow BER contour in
seconds not days
Flexibility:
• Supports statistical and bit-by-bit (“time domain”)
modes
• Models can have LTI and/or NLTV algorithms
• IC vendor can expose arbitrary model-parameters
Optimization:
Simulator can
sweep modelspecific
parameter
quickly
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SystemVue for IC Model Builders
Key Technology Investments
IC Model Builder:
SystemVue
HSD Designer:
ADS, EMPro
Physical Designer:
Constraint-based tool e.g.
Allegro, Expedition,
CR-5000 etc.
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ADS 2012 Supports IBIS 5.1 Plus Pre-standard
Capabilities
• Mid-channel repeaters - electrical and
optical – LTI and NLTV
– ADS 2012 and SystemVue 2012 unique
in the industry
– Agilent and Maxim plan to propose this
to IBIS Open Forum in 2012
• Advanced jitter parameters plus jitter
“stress tester” UI
– Consistent with a pre-standard proposal
known as “BIRD 123”
• On-die s-parameters
– Consistent with a pre-standard proposal
known as “BIRDs 116-118”
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Mid-channel Repeaters and Rack-to-rack Opto
• 10 Gb/s and 25Gb/s can propagate:
– Only a few centimeters on FR4 board  Electrical repeater
– Only a few meters on CAT5 twisted pair Optical fiber comms
• SystemVue 2012 and ADS 2012: Unique modeling based on IBIS AMI
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Customer Experience With ADS TC Versus HSPICE
• Solved circuits from 6k transistors to 86k transistors
• ADS Transient Convolution:
–
–
–
–
–
–
Faster than HSPICE in ALL cases
DC solve much more robust than HSPICE
Accuracy much better than HSPICE
Multilayer models much better than HSPICE fieldsolver
Post-processing much better than HSPICE/MATLAB
In addition: HSPICE doesn’t even support NVIDIA GPU acceleration
Run times on customer’s most challenging circuit:
Stop time
HSPICE
ADS TC
ADS TC GT
Speed up
versus
HSPICE
2 ns
192 hours
(8 days)
40 hours
10 hours
19
40 ns
No result
136 hours
34 hours
???
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Method
Netlists &
IBIS traditional
flow
IBIS AMI flow:
Bit-by-bit (“timedomain”) mode
IBIS AMI flow:
Statistical mode
Computational
expensive:
Modified nodal
analysis of
Kirchoff’s current
laws
Bit-by-bit
Statistical
superposition of
calculations based
impulse responses on impulse
response
BER floor in one ~10-3
minute simulation
~10-6
~10-18 or lower
Applicability &
Restrictions
LTI analog &
channel*
LTI analog &
channel
NLTV analog &
channel
NLTV Tx/Rx
*SystemVue and ADS can handle
NLTV mid-channel repeaters using
proprietary extension
NLTV Tx/Rx
LTI Tx/Rx
Notes: LTI = linear and time invarient, NLTV = non-linear and/or time varying
Red: Slow/bad; Yellow: in between/slightly restrictive; Green: Fast/good/flexible
Copyright 2012 Agilent Technologies, Inc.
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High Speed Digital Link Design
Design Space Exploration
& Optimization
Layout
Place Route DRC
pre-layout
Layout
verification
post-layout
(Proto)
Manufacturing
HW
Verification
Copyright 2012 Agilent Technologies, Inc.
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Analysis of critical nets after layout
Key Technology Investments
IC Model Builder:
SystemVue
HSD Designer:
ADS/EMPro
Physical Designer:
Constraint-based tool e.g.
Allegro, Expedition,
CR-5000 etc.
Copyright 2012 Agilent Technologies, Inc.
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Post-layout verification methodology
FEM
Momentum
Bring parts of your PCB into ADS layout
for 3D Planar and/or Full 3D EM analysis
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Post-layout Success Story: NVIDIA
Company: High-end graphics subsystems
for computers
Problem: Trial-and-error board spins to
eliminate signal integrity problems. No
insight. Stressful, non-deterministic product
schedules. Product delays and
cancellations.
Solution: Evaluate EM simulators for fast,
post-layout verification and rapid “what-if”
insight, and compelling field plots of fixes.
Results: Deterministic schedules. Millions
saved. Whole projects saved from
cancellation. New, differentiated service
(“Virtual EMI Lab”) offered to help their
customers be successful quickly
“Competitor tools took 3 days just for 4ports. Momentum gives accurate results
on our 18-port extractions in only 2.5
hours.”
-- Hany Fahmy, Director of Compliance and
Regulatory Engineering, NVIDIA Corporation
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Allegro/APD to ADS Flow
APD/Allegro Momentum
Export Setup
Select Critical Nets
or Entire Layout
Cookie-cut Power and
Ground Planes
Portion
Import in ADS Layout
“Sandbox”
Create Ports
Ground Ref Port
Adjustments if
required
Select Stackup Layers
Export to
.ads file
Verify Layout using
3-D Preview and
Simulate
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High Capacity Layout Pre-processor
• Imports ODB++ and IPC-2581 Offspring layout data from all board tools
• Critical net selection and cookie cutting
• Exports ADFI format files (ADS Design Flow Integration)
• Aimed at large designs in Mentor board tools
• Still recommend our SKILL code library for Allegro flow
• Still recommend Zuken integration for CR-5000/CR-8000
• Native ODB++ and Gerber/drill imports still recommended for small PCBs
or IPC-2581
Offspring
High Capacity
Layout PreProcessor
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ADS with Momentum for 3D Planar EM (Multilayer)
ADS
Import and draw
schematics and
multilayer structures
Momentum Simulator
3D Planar EM
Method of Moments
Multilayer Structures+
“Momentum is great for multilayered
structures like PCBs and IC packages. But
what about arbitrary 3D geometries like
connectors, ball grid array breakouts,
dielectric bricks, bond wires, shields,…?”
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Agilent EM Simulation Portfolio
ADS
EMPro
Parameterized
3D EM Components
ADS Layout Export
EMDS-for-ADS
Momentum Simulator
FEM Simulator
FDTD Simulator
Method of Moments
Finite Element Method
Finite Difference Time Domain
Planar Assumption
3D Accuracy
Time Domain Excitation
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Momentum for Power Integrity Challenges
𝑑𝑖𝐶𝑃𝑀
𝑉𝑟𝑖𝑝𝑝𝑙𝑒 𝑑𝑒𝑝𝑒𝑛𝑑𝑠 𝑜𝑛 𝑖𝐶𝑃𝑀 , 𝑅𝑃𝐷𝑁 ,
, 𝐿𝑃𝐷𝑁
𝑑𝑡
IC: packaged die
Chip has high i and high di/dt
Ceramic cap
Bulk cap
On-pkg cap
Die
Voltage
Regulation
Module
PCB
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ADS Momentum provides EM Model of Heavily
Perforated Power Distribution Networks
• SI/PI Analyzer handles:
– Grouping of many physical pins to one electrical port
– Net-based EM setup
• User identifies the nets, wizard selects minimum geometric objects required of
EM
• Momentum generates s-parameter EM-based model and look alike symbol
• Wizard places the symbol into a schematic along with lumped elements
– VRM, CPM chip model, decoupling capacitors
• Ideally suited to 2 to 8 layer packages and boards, up to ~15cm
– Lowest layer count is typically associated with heaviest perforation
– Consumer electronics boards are typically this size range
– This segment is not well served by traditional PI tools
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Power Integrity Example
• JEDEC DDR3 Reference Design
– 240-pin UDIMM (unbuffered dual inline memory module)
– 6 layer board, single power plane for core and I/O buffers
• Example objectives:
– Provide impedance profiles for power/ground from DC to 500
MHz
– Investigate the impact of the decoupling capacitors
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PDN Extraction for U1-U9 – J1
Select ports, import layout in ADS,
run EM simulation
PI-wizzard helps to set up circuit
Simulation with EM results
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Impedance Profiles – Without Decaps
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PDN Extraction for U1–J1
Without Decaps
WithDecaps
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Usability for HSD designers
• Flexible S-parameter import
• Object/Net navigator for complex layouts
• Via Designer
• DesignGuides and Compliance DesignKits
– IBIS AMI, DDR2/3, PCIe, USB3, HDMI, SAS2, UHS2
• Workshop and Classroom training
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Via Drawing Utility
• For accurate via modeling use a field
solver even for pre-layout
• Via Drawing Utility automates via
design ready for EM modeling in
Momentum or FEM
• Explore the design space to generate
constraints
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Via drawing utility. Auto-generate layout.
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Via drawing utility. EM simualtion-ready layout.
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Post-sales Classroom Training
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More Info
• Product page http://www.agilent.com/find/signal-integrity-analysis
• Blog http://www.agilent.com/find/signal-integrity
• Workshop http://www.agilent.com/find/eesof-hsd-workshop2011
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Validation with measurements
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Validation with measurements
Tyco Backplane
Simulated eye diagram without FFE
1.
Measured eye diagram without FFE
Comparison of measured and
simulated data
2.
5.
Simulated eye diagram with four tap FFE
equalizer using statistical simulator
3.
Measured eye diagram with four
tap FFE equalizer
4.
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Measurement Based Material Verification
Material Data Sheets do not tell the whole story when it comes to PCB Trace
Loss. Surface roughness, glass weave, pre-preg curing process, plating,
coatings, etc. can cause measureable differences at higher frequencies.
Agilent 5500
Atomic Force Microscope
Hammerstad
Measurement vs Loss Model
Loss, dB
dB(yunhui_bb4_hfcorr1_9..S(2,1))
dB(S(2,1))
dB(yunhui_bb4_hfcorr0..S(2,1))
dB(meas_2000mil_ro4350b..S(2,1))
0
-1
-2
Hemispherical
-3
-4
The original hemispherical model
-5
Multilevel
-6
0
2
4
6
8
10
12
14
16
18
20
freq, GHz
Frequency, GHz
SEM photograph of rough copper at
5000x magnification
at a 30 degree
angle.
ADS
Multi-Level
Hemi-Spherical
Model
Courtesy of Steven Hall et al. 2007
correlated with AFM measurements.
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Summary
• Our microwave expertise enables engineering in the multigigabit/s regime
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Thank You!
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