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School Of Engineering Department Of Electrical Engineering EE 348: Homework Assignment #04 (Due 02/27/2001) Spring, 2001 Choma Problem #16:

In monolithic circuits, diodes are commonly realized as appropriate inter connections of bipolar junction transistors (BJTs). To this end, the static volt–ampere charac teristics of each of the bipolar circuits shown in Fig. (P16) emulate those of a PN junction diode; that is, the indicated current,

I

, relates to the indicated voltage,

V

, in accordance with the approximate algebraic expression,

I

I eff

 

e

 For each configuration, use the Ebers–Moll model to deduce an expression for the effective diode saturation current,

I eff

, in terms of the transport saturation current

(I s )

, the forward beta

(

f )

, the reverse beta

(

r )

, and the base-emitter junction injection coefficient

(n f )

, of the bipolar junction transistor. For simplicity, assume that the injection coefficients of both BJT junctions are identical, and ignore the intrinsic base

(R b )

, emitter

(R e )

, and collector

(R c )

resistances. Also, assume that the junction injection coefficients,

n f

and

n r

, are identical.

I I

 

I

 

V

V

V

(a).

(b).

Fig. (P16)

(c).

Problem #17:

The basic current mirror in Fig. (P17) is typically designed to ensure that transistor

Q1

is biased within in its linear active domain. If the circuit is to provide a static col lector biasing current,

I CQ

, that is nominally independent of temperature over reasonable base emitter junction temperature excursions, the circuit must be designed so that the two transistors,

Q1

and

Q2

, are electrically identical and conduct equal collector current densities. In turn, this design constraint guarantees that the two transistor base-emitter voltages, emitter junction area of transistor

Q1

is

A 21 –times V BE1

larger than that of transistor and

Q2

.

V BE2

, match one another over a wide range of operating temperatures. Consider the case in which the base (a). Assuming that the circuit is designed correctly to ensure acceptable temperature desensitization, derive an expression for the static collector current,

I CQ

, in terms of circuit

EE 348 University of Southern California J. Choma, Jr.

parameters, applied static voltages, and transistor

h FE

and

V BE

. (b). What design criterion must be satisfied to render

I CQ

almost independent of

h FE

? (c). Why is the biasing current,

I CQ

, nominally independent of the voltage,

V P

? (d). For a fixed collector load resistance,

R l

, what smallest value of applied static voltage,

V P

, ensures transistor

Q1

operation in its linear regime?

+V CC +V P R 1 R l I CQ Q1 Q2 R 2 R ee

Fig. (P17)

Problem #18:

The three transistors in the base current–compensated bias current mirror of Fig. (P18) are electrically identical and conduct identical collector current densities. As usual, the circuit is designed to ensure that all transistors operate in their respective linear regimes.

+V CC +V P R R l Q3 I CQ Q2 Q1 R x

Fig. (P18)

(a). Derive an expression for the bias current,

I CQ

, in terms of circuit parameters, transistor

h FE

, and transistor

V BE

. (b). What design requirements must be satisfied to render

I CQ

almost independent of

h FE

? (c). What purpose is served by resistor

R X

? Would the circuit operate acceptably over wide

Homework #04 35 Spring Semester, 2001

EE 348 University of Southern California J. Choma, Jr.

temperature ranges if

R X

were supplanted by an open circuit?

Problem #19:

The TN2219AM NPN transistor has the following abridged set of SPICE parameters. Use SPICE to generate, and submit plots of, the following static characteristic curves. Save copies of these plots; you will need them in subsequent homework assignments! (a). Base current

(I B )

-versus- base-emitter voltage

(V BE )

for collector-emitter voltages

(V CE )

of

1.5, 2.5,

and

3.5 volts

. Vary

V BE

from zero -to-

800 mV

. (b). Collector current

(I C )

-versus-

V BE

for

V CE =1.5, 2.5,

and

3.5 volts

. Vary

V BE

from zero to-

800 mV

. (c). Static current gain

(h FE = I C /I B )

-versus-

I C

for

V CE =1.5, 2.5,

and

3.5 volts

. Vary

I C

from

100 nA

-to-

10 mA

, and plot

I C

on a logarithmic scale.

DESCRIPTION VALUE UNITS PARAMETER

IS

F NF VAF IKF

Transport Saturation Current Forward Current Gain B-E Junction Emission Coefficient Forward Early Voltage Forward Knee Current 1.80 140 1.0 54 22 fA –– –– volts mA

ISE NE

R NR RB RE RC CJE VJE MJE CJC VJC MJC CJS VJS MJS TF TR

B-E Leakage Saturation Current B-E Leakage Emission Coefficient Reverse Current Gain B-C Junction Emission Coefficient Average Base Resistance Average Emitter Resistance Average Collector Resistance Zero Bias B-E Junction Capacitance B-E Built-In Potential B-E Junction Grading Coefficient Zero Bias B-C Junction Capacitance B-C Built-In Potential B-C Junction Grading Coefficient Zero Bias Substrate Capacitance Substrate-Collector Built-In Potential Subs.-Collector Junction Grading Coeff. Forward Minority Carrier Transit Time Reverse Minority Carrier Transit Time 800 2.05 0.2 1.0 150 2 120 5 950 0.5 10 790 0.34 50 700 0.5 9 46.9 fA –– –– –– ohms ohms ohms fF mV –– fF mV –– fF mV –– pSEC nSEC

Problem #20:

Use the TN2219AM NPN transistor to design the circuit of Fig. (P17) to

Homework #04 36 Spring Semester, 2001

EE 348 University of Southern California J. Choma, Jr.

meet the following requirements and specifications (presumed quoted at

27 ºC

).

V CC = V P = 3.3 volts Both transistors biased for linear operation Both transistors identical, inclusive of junction areas I CQ = 1.5 mA @ V CE1 = 1.5 volts R l

6R ee I CQ changes by no more than 10% for temperatures ranging from 27 ºC - to- 75 ºC.

Simulate the circuit, making sure to check the following performance indices. When the simu lations do not track with either specifications or calculations, find out why and execute the required corrective actions. (a). Collector current

(I CQ )

at temperature

(T) = 27 ºC, 50 ºC, 75 ºC

. (b). Voltage at base of transistor

Q1

, with respect to ground, at

T = 27 ºC, 50 ºC, 75 ºC

. (c). Voltage at collector of transistor

Q1

, with respect to ground, at

T = 27 ºC, 50 ºC, 75 ºC

. (d). Voltage at emitter of transistor

Q1

, with respect to ground, at

T = 27 ºC, 50 ºC, 75 ºC

.

Homework #04 37 Spring Semester, 2001

EE 348 University of Southern California J. Choma, Jr.

U

niversity of

S

outhern

C

alifornia

School Of Engineering Department Of Electrical Engineering EE 348: Homework Assignment #04 (SOLUTIONS: Due 02/27/2001) Problem #16: Spring, 2001 Choma

Homework #04 38 Spring Semester, 2001

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