U niversity of S outhern C alifornia
School Of Engineering
Department Of Electrical Engineering
EE 348:
Homework Assignment #04
(Due 02/21/2002)
Spring, 2002
Choma
Problem #13:
The two PN junction diodes in the circuit of Fig. (P13) are identical, and the
current sink, I, is a constant current. Show that to a reasonable approximation, the diode currents, Id1 and Id2, relate to the applied voltage, V, in accordance with
I
Id 2 
V/nVT
1e
and
I
I d1 
.
V/nVT
1e
Id1
I d2
D1
D2
 V ee
Fig. (P13)
Problem #14:
Repeat Problem #13 but now, assume that the two PN junction diodes are
identical except for the fact that the junction area of diode D2 is Kd2-times larger than that of
diode D1.
Problem #15:
Wideband analog and high-speed digital integrated circuits necessarily use
minimal geometry transistors whose small breakdown voltages preclude their capability to sustain large biasing voltages over even relatively small time periods. To protect these devices
from transient voltage overstress, a second order LC filter of the form shown in Fig. (P15) is
often inserted between the ON/OFF power line switch and the power supply pad of the integrated circuit. In this circuit, Rl represents the steady state load to which power is to be supplied
and is nominally the ratio of the steady state load voltage -to- the steady state load current.
Thus, if the desired quiescent pad voltage of an integrated circuit is 3.3 volts and if this circuit is
EE 348
University of Southern California
J. Choma, Jr.
to draw a quiescent current of 12 mA, Rl = 3.3/12 mA = 275 . The filter itself consists of the
inductance, Ls, which includes any parasitic inductance associated with the power supply bus
line routing on chip, and the capacitance, Cl, which includes parasitic power supply pad capacitance. The resistance, Rs is generally small and includes the effects of power bus losses and
finite inductance quality factor (Q). By the way, the rubberized or plastic-coated “bump” you
see in the power line that connects your laptop computer to an energy source is the inductance in
Fig. (P15). The indicated voltage, Vp is the Thévenin energizing voltage for the chip, while the
switch, which is closed at time t = 0, allows the filter input voltage, vi(t), to emulate the step
function, Vpu(t). It is to be understood that the fundamental purpose of the filter is to slow the
rate of power delivery from the input port, where vi(t) is measured, -to- the output port, where
voltage vo(t) is established, so that vo(t) rises monotonically with time toward its steady state
value with little or no voltage overshoot.
Ls
Rs
vi(t)
vo(t)
t=
0

Rl
Cl
Vp

Fig. (P15)
(a). The filter in Fig. (P15) is clearly a second order circuit. In view of the discussion provided
above, should the circuit poles, whose frequencies might be labeled, p1 and p2, be real
numbers or complex conjugates? Briefly explain your rationale.
(b). Derive an expression for the transfer function, H(s) = Vo(s)/Vi(s) and in the process, show
that the pole frequencies satisfy the relationships,
Ls
1
1


 R R C
s l
l
p1
p2
Rl  Rs


and
 R

l
 L C  H( 0 )L C .
 
s l

p1 p2
R  Rs  s l
 l

(c). Assume that the poles are real and that their frequencies relate as p2 = kp1, where k is
understood to be greater than or equal to one. For k > 1, show that the time domain
response, normalized to the steady state value of the response, is
vo ( t )
 k   p1 t
 1  k p1 t
von ( t ) 
 1  
 
,
e
e
H( 0 )V p
 k  1
 k  1
1
while for k = 1, confirm that
Homework #04
28
Spring Semester, 2002
EE 348
University of Southern California
vo ( t )
von ( t ) 
H( 0 )V p
 1 
1  p t  e
1
 p1 t
J. Choma, Jr.
.
(d). Plot the normalized responses determined in Part (c) -versus- the normalized time parameter, tn = p1t for k = 1, 1.5, 3, and 10. What value of k might be desired to ensure the realization of the slowest possible step response for any given real number value of p1?
(e). Let TR represent the rise time of the filter; that is, TR is the time required after the switch is
closed for the output response to achieve 90% of its steady state value. For the optimal
value of k (in the sense of a maximally slowed response) determined in Part (d), confirm
that p1TR  3.9.
(f). Assume now that Rl >> Rs and Ls >> RsRlCl. For the optimal operating condition stipulated in Part (e), show that a rise time of TR is achieved if
Ls 
T
R
 Rl  Rs 
1.95
and
C 
l
T
R
.
7.8Rl
(g). Assume that a certain integrated circuit is to be energized by a 3.3 volt battery that is
switched on at time t = 0. Assume further that the net effective Thévenin source resistance
(Rs) is 15  and that the effective steady state load resistance (Rl) is 1020 . The latter
resistance corresponds nominally to 3.3 volts delivered to a load drawing 3.23 mA. A 0 to- 90% rise time (TR) of at least 200 μSEC is desired to protect the active devices in the
given circuit. Design the protection filter and simulate it on SPICE to confirm the stipulated rise time objective.
Problem #16:
Do Problem #2.32, Page 91, of the assigned textbook.
Problem #17:
Do Problem #2.33, Page 91, of the assigned textbook.
Homework #04
29
Spring Semester, 2002
EE 348
University of Southern California
J. Choma, Jr.
U niversity of S outhern C alifornia
School Of Engineering
Department Of Electrical Engineering
EE 348:
Homework Assignment #04
(SOLUTIONS: Due 02/21/2002)
Spring, 2002
Choma
Problem #13:
Homework #04
30
Spring Semester, 2002