Low Cost Pure Sine Wave Solar Inverter Circuit

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Low Cost Pure Sine Wave Solar Inverter Circuit
ECE Capstone Design Project, Spring ‘14
Cameron DeAngelis
Luv Rasania
Advisors: Professor Yicheng Lu and Rui Li
Introduction
Ever thought about what goes on behind the scenes when you simply flick the
power switch to on? There is an entire process as to how this electricity is created to help
power on your lights and devices. In todays world most of the electricity is generated
through the use of electromechanical generators which are driven by heat created from
chemical combustion or nuclear fission. This process however, exerts pollution into the air
and small amounts of radiation.
Motivation
The world today is slowly transforming into a green world where pollution is going
to be at an all time minimum. A solution to cut down pollution created by these generators
is to have an alternate form of energy production. Through the use of solar panels, energy
from the sun is almost always readily available to be harnessed into electricity. This energy,
however, is in the form of DC voltage and needs to be inverted to an AC voltage to be
compatible with our electrical grid. This is where a solar inverter circuit becomes
necessary.
Design
In order to invert the DC voltage, the group made use of a 555 timer IC, a decade
counter IC, and H-bridge circuit, and a passive filter circuit. The 555 timer is responsible for
generating a clock voltage input for the decade counter at the correct frequency. The
decade counter provides an optimized square wave for triggering the transistors in the Hbridge circuit. The H-bridge inverts the input signal into a modified sine wave, which then
enters the filter where it becomes very similar to a sine wave. The filter is a 3rd order low
pass design which values were chosen by trial and error.
Results
The circuit produced a relatively good output signal at the required frequency and
amplitude, so the project was an overall success. The design came out to a total cost of
$45.71. The pure sine wave output is shown below.
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