Instruction Sets and Beyond
Computers, Complexity, and
Controversy
Brian Blum, Darren Drewry
Ben Hocking, Gus Scheidt
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Outline
Points of Clarification
RISC and CISC defined
Points of Attention and Contention
RISC II and the MCF Evaluation
Multiple Register Sets
The 432
Summary
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Points of Clarification
1985 - What is RISC today?
RISC – Number of Instructions
RISC I – 31
88000 – 51
R4000 - 94
Pyramid - 90
VAX 11/780 – 303
Intel 80486 - 235
IBM 370/168 – 208
Ridge – 100
RISC:academic .vs. CISC:commercial
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RISC Defined
Single Cycle Operation
Load / Store Design
Hardwired Control (No microcode)
Few Instructions and Addressing Modes
Fixed Instruction Format
More Compile Time Effort
(Split Data and Instruction Cache)
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CISC in Comparison
Larger and more Complex (Insn & Addr)
Multiple Cycle Execution (micro-instructions)
Upward Compatible (w/ Obsolete Insn)
Standardized
More Hardware (on-chip logic)
Fewer Registers – Unified Cache?
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RISC and CISC: General Points
CISC Built for Language (Assembly)
CISC Built for Memory Conservation
CISC Focuses on Standards and Compatibility
RISC Designed for Speed
RISC Simultaneous Access to Code and
Operands
RISC Reliance on Compilers
Worse: or just Different?
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Two Misconceptions about
RISC and CISC
Implication that discussion is limited to
selection of instruction set.
Tradeoffs across various boundaries:
architecture / implementation
hardware / software
compile-time / run-time
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Two Misconceptions about
RISC and CISC
Implication that any machine is one or
the other.
Machine performance difficult to interpret
Absolute number of instructions is not the
only criterion
- compiler / architecture coupling
- non-instruction set design
decisions
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Early arguments for RISC
Simpler designs could be realized more
quickly
Avoid performance disadvantages of old
implementation technology.
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DEC’s MicroVAX-32
Qualifies as a CISC
Very short development period
Standardization of instruction set
RISC can benefit from standardization
Demonstrates importance of assigning
function to appropriate implementation
level
Microcoding can be a valuable technique
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Misleading RISC Claims
Amount of design time saved.
Academic vs. commercial design and
production
Performance claims.
Typical benchmarks avoid metrics of
reliability and response time
Use of micro-benchmarks vs. large,
heterogeneous benchmarks
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Multiple Register Sets
Performance feature independent of
RISC aspect of processor
Reduce frequency of register
saves/restores on procedure calls
Overlap register sets for parameter
passing
MRS impact performance for both RISC
and CISC
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Effect of MRS on
CISC
Effect of MRS on
RISC
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RISC II and the MCF Evaluation
Used by Department of Defense to
evaluate life-cycle cost of computers
Efficiency defined as: program size;
memory bus traffic; canonical processor
cycles
VAX (CISC) judged best by MCF
RISC II evaluation compared to VAX
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RISC II and the MCF Evaluation
Results of comparison
VAX requires 3.5 times less memory (for
program instructions)
RISC II has 2.5 times more processormemory traffic
VAX requires fewer cycles than RISC II
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A CISC Example – The 432
Object-oriented
Geared towards Ada
Every object protected uniformly
Variable length instructions (6-321 bits)
On-chip microcode
Every memory reference is checked
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Problems with the 432
10-20 times as slow on low-level
benchmarks (such as Hanoi)
No on-chip data caching
No instruction stream literals
No local registers
Ada compile performs almost no
optimization
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Advantages of the 432
Reliability
Could be faster at more realistic
benchmarks (especially ones that use
IPCs)
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Lessons from the 432
Even with all of the oversights of the
432, it has an important advantage –
reliability
More realistic benchmarks should be
used to compare RISC with CISC
CISCs should take advantage of
multiple register sets
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Conclusions
When comparing RISC with CISC you
should use similar hardware
organizations
Benefits depend on
Types of programs being run
Whether requirements are based on
Performance
Reliability
Some other factor or set of factors
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And now to thank those who
made this all possible!
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