EECS 373 Final Exam
Winter 2011
Name: ____________________________________ unique name: _______________
Sign the honor code:
I have neither given nor received aid on this exam nor observed anyone else doing so.
___________________________________
Scores:
Problem #
1
2
3
4
5
6
7
8
9
10
11
Total
Points
/10
/15
/12
/13
/6
/8
/10
/6
/8
/4
/8
/100
NOTES:
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There are 13 pages including this one.
Closed book, closed notes.
Calculators are allowed, but no PDAs, Portables, Cell phones, etc.
Don’t spend too much time on any one problem and be sure you get to the design
problem with plenty of time to spare.
You have about 120 minutes for the exam.
Be sure to show work and explain what you’ve done when asked to do so. Getting
partial credit without showing work will be rare.
1) Fill-in-the-blank [10, -1 per wrong or blank answer, minimum 0]
a) If a given message scheme allows for two bits of error correction, the Hamming distance
of the underlying code must be at least 4/5/6/7/8/9. If the scheme could correct any
two-bit error and simultaneously detect any four-bit error, the Hamming distance of the
underlying code must be at least 4/5/6/7/8/9.
b) In Verilog an @(posedge clock) block would be used when creating a MUX / adder /
flip-flop / priority encoder.
c) Direct Memory Access (DMA) is an alternative to Programmed IO / Direct Disk Access /
synchronous interrupts. One factor that limits the use of DMA is that
processors using it must support synchronous interrupts / you need virtual timers /
the memory bus must support arbitration.
d) With respect to PCBs, a “via” is part of the rat’s nest / a plated hole in the board used
to connect different layers / a pad to solder surface-mount parts to.
e) “Bit stuffing” is used to
 send data more quickly over a wire by inserting extra bits between clock edges.
 add transitions on a serial bus so the receiver can synchronize its clock.
 add error correction bits to error-correction algorithms.
 increase the Hamming distance of a code.
f) A principle advantage of storing music digitally is that
 error correction is much easier.
 digital data doesn’t suffer from quantization issues.
 analog data typically requires a much more complex processor to be able to
actually playback the data.
g) A clock that has a duty cycle of 25% and a frequency of 2MHz will have a period of
_________________ ns.
h) Consider a 5-bit digital to analog converter that has an INL of no more than ±¼ LSB and a
Vref of 8V. Say an input of “00000” should (ideally) generate an output of ⅛V.
The range of values you could reasonably expect for an input of “10111” is
_________V to __________ V.
2) Consider the following C function.
int max(unsigned char w[], int z)
// Find the max of the first z elements of the array w.
// print and return that value. All values are positive
{
int i, max=0;
for(i=0;i<z;i++)
if(w[i]>max)
max=w[i];
printit(max); // a function which prints the value
return(max);
}
Rewrite the above code in ARM assembly while following the ABI and being reasonably
efficient about your use of stack space. You are to assume the char data type is 8-bits and
that printit has the following prototype: [15 points]
int printit(int);
3) Short answer [12 points]
a) Many serial buses use differential signaling to reduce the impact of noise on the data
(and thus the error rates).
 What is differential signaling? [2]

Why does differential signaling help with noise reduction? [2]
b) If a given ADC is non-monotonic, what does this imply about its differential non-linearity
(DNL)? [3]
c) Both the AHB and PCI buses are designed to work with fairly fast and complex
peripherals. The PCI bus uses a shared Address/Data bus while the AHB bus not only
has separate address and data buses but has two different data buses. What design
considerations caused such radically different design decisions? [5]
4) Your design team has been asked to create a “positive edge detector”. That is, there is
some glitch-free signal (Bin), which is not synchronized to the system clock (a debounced
push button perhaps) and you are to detect when the button is pressed (with some small
amount of delay being acceptable). When that happens you are to output a “1” for one or
two periods of the system clock (sysclock). You output should be labeled as Pdetect.
[13 points]
a) One member of your team implemented the following design, but it isn’t working at all.
Explain the expected behavior of this circuit. Recall that “R” implies a synchronous
reset. [3]
D Flip-Flop
1
Bin
D
Q
Pdetect
Clock
R
b) Another teammate created this design and it works, but only erratically. Explain why.
You should assme the reset is connected to ground. [4]
D Flip-Flop
Bin
D
sysclock
Q
Clock
Pdetect
R
(Continued from the previous page)
c) Now design a positive edge detector that will work reliably. You may use flip-flops,
gates, and standard MSI logic devices (comparators etc.) as needed. Use the same input
and output names as the previous designs (sysclock, Bin, Pdetect). Be sure to clearly label
all parts that aren’t standard gates. [6]
5) Answer the following questions using the above figures. Assume Vref=8V and that all
converters have a INL of ± 1/8 LSB. There may be more than one possible answer (or a range
or ranges of possible answers). Provide all possible answers!
a) If 2.1V is put into the ADC and Dout is connected to Din of of DAC#2, what is/are the
value(s) that could be found on Vout of the DAC? [3]
b) If the value “01” is put into DAC#2 and the Vout of the DAC is connected to the Vin of
the ADC, what value(s) might you find on the Dout of the ADC? [3]
6) You are working on a design for our SmartFusion which has 5 interrupt sources: A, B, C, D, and E.
Recall that the SmartFusion only implements the 5 highest priority bits, the other 3 are ignored. You
want the following to be true:
 A should be able to preempt all the other interrupts.
 B should be able to preempt C, D and E.
 C, D and E should be unable to preempt any interrupt. C should have a higher priority than D or
E, and E should have the lowest priority of all.
a) List all PRIGROUP setting or settings you could use in this case. Assume no two interrupts can be
assigned the same priority. Provide your answer in 3-digit binary and explain. [4]
b) Indicate, in 8-bit binary, what priorities you will assign to each interrupt. Let us know
which PRIGROUP setting you are using (mainly if you have more than one PRIGROUP
listed above). Again, no two interrupts may be assigned the same priority. [4]

PRIGROUP=________________________ (3-digit binary)

A priority= ________________________ (8-digit binary)

B priority= ________________________ (8-digit binary)

C priority= ________________________ (8-digit binary)

D priority= ________________________ (8-digit binary)

E priority= ________________________ (8-digit binary)
7) Consider the following data being that has been received. It was originally sent using the
Viterbi algorithm as described in class.
Data
1 0 1 0 0 1 1
Parity 1 1 0 1 1 1 0
Show a table/chart similar to the one drawn in class that would show how the errors, if any,
would be corrected. Clearly show your work to get any credit. [10 points]
8) Write ARM assembly code which performs the same task as the following code segment.
Your code must be no longer than 10 assembly instructions. [6 points]
uint32_t *reg = (uint32_t *)0x40003340;
*reg =*reg+*reg;
9) Write a C function void clear_pending(int x) that clears interrupt source x. You are to not
check if the value x is reasonable. The table below may prove useful.[8 points]
void clear_pending(int x)
{
10) In lab 4 you had the following Verilog code:
// swregwrp.v
module swregwrp(
PCLK,
PENABLE,
PSEL,
PRESERN,
PWRITE,
PREADY,
PSLVERR,
PWDATA,
PRDATA,
SWCON,
TPS);
input PCLK,PENABLE, PSEL, PRESERN, PWRITE;
input [7:0] PWDATA;
input [1:0] SWCON;
output [7:0] PRDATA;
output PREADY, PSLVERR;
output [4:0] TPS;//test points
wire rd_enable;
wire wr_enable;
assign rd_enable = (!PWRITE && PSEL); //Data is ready during first
cycle to make it availble on the bus when PENABLE is asserted
swreg swreg_0 (.clk(PCLK), .nreset(PRESERN),
.rd_en(rd_enable), .data_out(PRDATA), .sw_port(SWCON));
assign PREADY = 1'b1;
assign PSLVERR = 1'b0;
assign
assign
assign
assign
assign
TPS[0]
TPS[1]
TPS[2]
TPS[3]
TPS[4]
=
=
=
=
=
PCLK;
PWRITE;
PSEL;
PENABLE;
PREADY;
endmodule
Why is it we aren’t using the APB address bus in this code? [4 points]
11) Consider a packet consisting of 11 bits. There are 7 data bits (A-G) and 4 parity bits (W-Z) in the
packet. So a packet looks as follows:
A
B
C
D
E
F
G
W
X
Y
Z
The intent of the scheme is to be able to correct one bit of error (one bit-flip) in the packet. Let the
function P() return a 1 if there are an odd number of 1s provided as arguments, otherwise it is a zero.
So P(0,1,0,0) would return a “1”, while P(0,1,1,0) would return a “0”.
Say that W, X, and Y are computed as follows:
W=P(A, B, C, D, E)
X=P(A, B, F)
Y=P(A, B, C, D, G)
In order to be able to correct any one-bit error (in the data or parity bits) what should the function for
“Z” be? (If there is more than one correct answer, you must provide just one of them!) [8 points]