ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 28: November 8, 2013
Memory Overview
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Penn ESE370 Fall2013 -- DeHon
Today
• Memory
– Motivation
– Organization
– Basic components
– Optimization concerns
• Project 2 is on this
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Penn ESE370 Fall2013 -- DeHon
Know how to store state
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Register Storage
• Could just put together a large number
of registers
• Concerns?
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Concerns?
• Large number of wires
– Could determine area
– 5l wire pitch  how wide?
• May want to store for many cycles
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Usage Scenario
• How many state
values read on each
cycle?
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Concerns?
• Large number of wires
– Could determine area
• May want to store for many cycles
• Not able to update all on every cycle
• Not able to use all on every cycle
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Penn ESE370 Fall2013 -- DeHon
Limited Data Use
• What else do we need to share the wires
if can only use one register on each
cycle?
– Use with shared data path
• Need to select the one output
– Can only update one
• Need to control which one gets written
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Penn ESE370 Fall2013 -- DeHon
Limited Data Use
• Add load enable
to register
• Logic to enable
one register on
write
• Mux to select
output
Penn ESE370 Fall2013 -- DeHon
we
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Good Solution?
• Could get away
with just latch
– Not full register
with master/slave
latch
• Pay large amount
for decode and
mux
– Proportional to
memory bits
Penn ESE370 Fall2013 -- DeHon
we
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Memory Idea
• Maximize storage density (bits/cm2)
• By minimizing the size/complexity of the
repeated element
• Use shared periphery circuits to provide
full functionality
• Trades off bandwidth (concurrent
access) to save area
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Memory Bank
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Share Address Decode
• Word – group of bits read/written together
– All have same control
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Share Address Decode
• Words
• Mux select bits (words) from row read
– When only want a subset
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Penn ESE370 Fall2013 -- DeHon
Share Address Decode
• Result: only spend N0.5 area (perimeter)
on selecting rather than linear in bits
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Gate Density
• When is 14n > 5n+32*sqrt(n) ?
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Penn ESE370 Fall2013 -- DeHon
Memory Row
• Use shared enable for wire economy
– Word line
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Penn ESE370 Fall2013 -- DeHon
Memory Column
• Use shared bus for area and
wire economy
– Row enable selects the cells to
read/write from bus
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Penn ESE370 Fall2013 -- DeHon
Memory Cell
• Hold data
• Conditionally drive onto output bus
• Conditionally overwritten with data from bus
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5T SRAM Memory Bit
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SRAM Memory bit
• Core is back-to-back
inverters for storage
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Penn ESE370 Fall2013 -- DeHon
SRAM Memory bit
• Pass gate mux for
output to column
– Bit-Line (BL)
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SRAM Memory bit
• How do we write
into this cell?
– No directionality to
pass gate
– If drive BL strong
enough, can flip
value in selected cell
• Ratioed operation
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Column Capacitance
• What is capacitance of bit line (column)?
– Waccess (M5,M6) – transistor width of column
device
– d rows
 g=Cdiff/Cgate
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Time Driving Bit Line
• In terms of Waccess, Wbuf (M1,M3), d
• For Waccess=Wbuf=1, d=512, g=0.5
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Penn ESE370 Fall2013 -- DeHon
Column Capacitance
Consequence
• Want Waccess, Wbuf small to keep
memory cell small
• Increasing Waccess, also increases Cbl
– Don’t really win by sizing up
• Conclude: Driving bit line will be slow
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Column Sensing
• Speedup read time by sensing limited
swing
• Sense circuit detects small change in
bit line voltage
– Precharge to intermediate voltage
• Amplifier for output
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Output Amps
• Bottom of array includes Sense
Amplifiers from bit lines to output
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Penn ESE370 Fall2013 -- DeHon
Column Write
• Writes driven from outside array
• Use large driver
– Strong enough to flip memory bit
– Strong so can charge column quickly
• Disable when not write
– Be careful on your
project2
– Could overwrite wrong
row
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Complete Memory Bank
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Idea
• Memory for compact state storage
• Share circuitry across many bits
– Minimize area per bit  maximize density
• Aggressively use:
– Pass transistors, Ratioing
– Precharge, Amplifiers
to keep area down
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Penn ESE370 Fall2013 -- DeHon
Admin
• HW7 due Tuesday
• MT2 solutions by Monday
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