ESE534:
Computer Organization
Day 5: February 10, 2014
VLSI Scaling
1
Penn ESE534 Spring 2014 -- DeHon
Today
•
•
•
•
•
•
VLSI Scaling Rules
Effects
Historical/predicted scaling
Variations (cheating)
Limits
Note: Most gory MOSFET equations
will see  goal is to understand trends
– Give equations … then push through
scaling implications together
Penn ESE534 Spring 2014 -- DeHon
2
Why Care?
• In this game, we must be able to predict
the future
• Technology advances rapidly
• Reason about changes and trends
• Re-evaluate prior solutions given
technology at time X.
• Make direct comparison across
technologies
– E.g. to understand older designs
• What comes from process vs. architecture
Penn ESE534 Spring 2014 -- DeHon
3
Why Care
• Cannot compare against what competitor
does today
– but what they can do at time you can ship
– Development time > Technology generation
• Careful not to fall off curve
– lose out to someone who can stay on curve
4
Penn ESE534 Spring 2014 -- DeHon
Scaling
• Premise: features scale “uniformly”
– everything gets better in a predictable
manner
• Parameters:
 l (lambda) -- Mead and Conway
 F -- Half pitch – ITRS (F=2l)
 S – scale factor – Rabaey
 F’=S×F
5
Penn ESE534 Spring 2014 -- DeHon
ITRS Roadmap
• Semiconductor Industry rides this
scaling curve
• Try to predict where industry going
– (requirements…self fulfilling prophecy)
• http://public.itrs.net
6
Penn ESE534 Spring 2014 -- DeHon
Preclass
• Scale factor S from 32nm  22nm?
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Penn ESE534 Spring 2014 -- DeHon
MOS Transistor Scaling
(1974 to present)
S=0.7
[0.5x per 2 nodes]
Pitch
Source: 2001 ITRS - Exec. Summary, ORTC Figure
Penn ESE534 Spring 2014 -- DeHon
Gate
[from Andrew Kahng]
8
Half Pitch (= Pitch/2) Definition
Metal
Pitch
(Typical
DRAM)
Source: 2001 ITRS - Exec. Summary, ORTC Figure
Penn ESE534 Spring 2014 -- DeHon
Poly
Pitch
(Typical
MPU/ASIC)
[from Andrew Kahng]
9
Node Cycle Time:
0.7x
0.7x
Log Half-Pitch
Scaling Calculator +
1994 NTRS .7x/3yrs
Actual .7x/2yrs
Linear Time
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
N
N+1
Node Cycle Time
(T yrs):
N+2
*CARR(T) =
[(0.5)^(1/2T yrs)] - 1
* CARR(T) = Compound Annual
Reduction Rate
(@ cycle time period, T)
Source: 2001 ITRS - Exec. Summary, ORTC Figure
Penn ESE534 Spring 2014 -- DeHon
CARR(3 yrs) = -10.9%
CARR(2 yrs) = -15.9%
[from Andrew Kahng]
10
Dimensions
• Channel Length (L)
• Channel Width (W)
• Oxide Thickness (Tox)
11
Penn ESE534 Spring 2014 -- DeHon
Scaling
•
•
•
•
•
Channel Length (L)
Channel Width (W)
Oxide Thickness (Tox)
Doping (Na)
Voltage (V)
12
Penn ESE534 Spring 2014 -- DeHon
Full Scaling
(Ideal Scaling, Dennard Scaling)
•
•
•
•
•
Channel Length (L)
S
Channel Width (W)
S
Oxide Thickness (Tox) S
Doping (Na)
1/S
Voltage (V)
S
13
Penn ESE534 Spring 2014 -- DeHon
Effects on Physical Properties?
•
•
•
•
•
•
•
•
•
Area
Capacitance
Resistance
Threshold (Vth)
Current (Id)
Gate Delay (tgd)
Wire Delay (twire)
Energy
Power
Penn ESE534 Spring 2014 -- DeHon
• Go through full
(ideal)
• …then come back
and ask what still
makes sense today.
14
Area
 F FS
 Area impact?
 A=L×W
 A  AS2
 32nm  22nm
 50% area
 2× capacity same
area
L
S=0.7
[0.5x per 2 nodes]
Pitch
W
Gate
15
Penn ESE534 Spring 2014 -- DeHon
Preclass
• When will have have 100-core processor
– What feature size?
– What time frame?
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Penn ESE534 Spring 2014 -- DeHon
Capacity Scaling from Intel
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Penn ESE534 Spring 2014 -- DeHon
Capacitance
• Capacitance per unit
area scaling:
– Cox= eSiO2/Tox
– Tox S×Tox
– Cox  Cox/S
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Penn ESE534 Spring 2014 -- DeHon
Capacitance
• Gate Capacitance
scaling?
 Cgate= A×Cox
 A  A×S2
 Cox  Cox/S
 Cgate 
S×Cgate
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Penn ESE534 Spring 2014 -- DeHon
Resistance
• Resistance
scaling?
• R=rL/(W*t)
• W S×W
• L, t similar
• R  R/S
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Penn ESE534 Spring 2014 -- DeHon
Threshold Voltage
• VTH S×VTH
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Penn ESE534 Spring 2014 -- DeHon
Current
• Saturation Current scaling?
Id=(mCOX/2)(W/L)(Vgs-VTH)2
Vgs=V S×V
VTH S×VTH
W S×W
L S×L
Cox  Cox/S
Id S×Id
22
Penn ESE534 Spring 2014 -- DeHon
Current
• Velocity Saturation Current scaling:
IDS
VDSAT 
L sat
mn

VDSAT 
  satCOX W VGS  VT 


2 
Vgs=V S×V
VTH S×VTH

L S×L
VDSAT  S×VDSAT
WS×W
Cox  Cox/S
Id S×Id
23
Penn ESE534 Spring 2014 -- DeHon
Gate Delay
 Gate Delay
scaling?
 tgd=Q/I=(CV)/I
 V S×V
 Id  S×Id
 C  S×C
 tgd  S×tgd
24
Penn ESE534 Spring 2014 -- DeHon
Overall Scaling Results, Transistor Speed and Leakage.
Preliminary Data
•HP = High-Performance Logic
•LOP = Low Operating Power Logic
from 2005 ITRS.
•LSTP = Low Standby Power Logic
Leakage Current
Intrinsic Transistor
Delay, t = CV/I
10.00
(HP: standby power
dissipation issues)
(lower delay = higher speed)
1.E+00
HP
LOP
1.E-01
LSTP
1.00
CV/I (ps)
(ps)
Isd,leak (uA/um)
1.E-02
LSTP Target:
Isd,leak ~ 10 pA/um
1.E-04
0.10
HP Target:
17%/yr, historical
rate
0.01
2005
LOP
1.E-03
2007
2009
2011
2013
2015
Calendar Year
Penn ESE534 Spring 2014 -- DeHon
17%/yr
rate
2017
1.E-05
Planar Bulk
MOSFETs
1.E-06
2005
2019
2007
2009
2011
Advanced
MOSFETs
2013
2015
Calendar year
25
2017
2019
ITRS 2009 Transistor Speed
RO=Ring
Oscillator
26
Penn ESE534 Spring 2014 -- DeHon
Wire Delay
 Wire delay
scaling?
 twire=RC
• …assuming (logical)
wire lengths remain
constant...
 R  R/S
 C  S×C
 twire  twire
27
Penn ESE534 Spring 2014 -- DeHon
Impact of Wire and Gate
Delay Scaling
• If gate delay scales down
but wire delay does not scale,
what does that suggest about the
relative contribution of gate and wire
delays to overall delay as we scale?
28
Penn ESE534 Spring 2014 -- DeHon
Energy
• Switching Energy per operation scaling?
• E=1/2 CV2
 V S×V
 C  S×C
 E  S3×E
29
Penn ESE534 Spring 2014 -- DeHon
Power Dissipation (Dynamic)
• Capacitive
(Dis)charging
scaling?
 P=(1/2)CV2f
• Increase
Frequency?
 tgd  S×tgd
 V S×V
 C  S×C
 So: f  f/S ?
 P
 P  S2×P
S3×P
Penn ESE534 Spring 2014 -- DeHon
30
Effects?
•
•
•
•
•
•
•
•
•
Area
S2
Capacitance
S
Resistance
1/S
Threshold (Vth)
S
Current (Id)
S
Gate Delay (tgd) S
Wire Delay (twire) 1
Energy
S3
Power
S2S3
Penn ESE534 Spring 2014 -- DeHon
31
Power Density
• P S2P (increase frequency)
• P S3P (dynamic, same freq.)
• A  S2A
• Power Density: P/A two cases?
– P/A  P/A increase freq.
– P/A  S×P/A same freq.
32
Penn ESE534 Spring 2014 -- DeHon
Cheating…
• Don’t like some of the implications
– High resistance wires
– Higher capacitance
– Atomic-scale dimensions
• …. Quantum tunneling
– Not scale speed fast enough
33
Penn ESE534 Spring 2014 -- DeHon
Improving Resistance
•
•
•
•
R=rL/(W×t)
W S×W
L, t similar
R  R/S
What might we do?
Don’t scale t quite as fast  now taller than wide.
Decrease r (copper) – introduced 1997
http://www.ibm.com/ibm100/us/en/icons/copperchip/
Penn ESE534 Spring 2014 -- DeHon
34
35
Penn ESE534 Spring 2014 -- DeHon
Capacitance and Leakage
• Capacitance per unit
area
– Cox= eSiO2/Tox
– Tox S×Tox
– Cox  Cox/S
What’s wrong with Tox = 1.2nm?
source: Borkar/Micro 2004
36
Penn ESE534 Spring 2014 -- DeHon
Capacitance and Leakage
• Capacitance per unit
area
– Cox= eSiO2/Tox
– Tox S×Tox
– Cox  Cox/S
What might we do?
Reduce Dielectric Constant e (interconnect)
and Increase Dielectric to substitute for scaling Tox
(gate quantum tunneling)
Penn ESE534 Spring 2014 -- DeHon
37
ITRS 2009
Table PIDS3B Low Operating Power
Technology Requirements
Grey cells delineate one of two time periods: either before
initial production ramp has started for ultra-thin body fully
depleted (UTB FD) SOI or multi-gate (MG) MOSFETs, or
beyond when planar bulk or UTB FD MOSFETs have reached
the limits of practical scaling (see the text and the table notes
for further discussion).
2009 2010 2011 2012 2013 2014 2015 2016 2017
Year of Production
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)
(contacted)
54
Lg: Physical Lgate for High Performance logic
(nm)
29
Lg: Physical Lgate for Low OperatingPower
(LOP) logic (nm) [1]
32
EOT: Equivalent Oxide Thickness (nm) [2]
Extended planar bulk
1
UTB FD
MG
Gate poly depletion (nm) [3]
Bulk
0.27
Channel doping (E18 /cm3) [4]
Extended Planar Bulk
3
Junction depth or body Thickness (nm) [5]
Extended Planar Bulk (junction)
14
UTB FD (body)
MG (body)
EOTelec: Electrical Equivalent Oxide Thickness (nm) [6]
Extended Planar Bulk
1.64
UTB FD
MG
Penn ESE534 Spring 2014 -- DeHon
2018
2019
2020
2021
2022
2023
2024
45
38
32
27
24
21
18.9
16.9
15
13.4
11.9
10.6
9.5
8.4
7.5
27
24
22
20
18
17
15.3
14
12.8
11.7
10.7
9.7
8.9
8.1
7.4
29
27
24
22
18
17
15.3
14
12.8
11.7
10.7
9.7
8.9
8.1
7.4
0.9
0.9
0.85
0.8
0.9
0.85
0.8
0.8
0.75
0.8
0.7
0.75
0.73
0.7
0.7
0.65
0.65
0.6
0.6
0.27
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3.7
4.5
5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
13
11.5
10
9
7
6.2
6
8
5.1
7.6
4.7
7
6.4
5.8
5.4
4.8
4.4
4.2
4
1.2
1.2
1.15
1.2
1.1
1.15
1.13
1.1
1.1
1.05
1.05
1
1
1.53
1.23
1.18
1.14
1.3
1.25
38
High-K dielectric Survey
Wong/IBM J. of R&D, V46N2/3P133—168, 2002
39
Penn ESE534 Spring 2014 -- DeHon
Intel NYT
Announcement
• Intel Says Chips Will Run Faster,
Using Less Power
– NYT 1/27/07, John Markov
– Claim: “most significant change in the
materials used to manufacture silicon chips
since Intel pioneered the modern integratedcircuit transistor more than four decades ago”
– “Intel’s advance was in part in finding a new
insulator composed of an alloy of
hafnium…will replace the use of silicon
dioxide.”
40
Penn ESE534 Spring 2014 -- DeHon
Improving Gate Delay
 tgd=Q/I=(CV)/I
 V S×V
How might we
accelerate?
 Id=(mCOX/2)(W/L)(Vgs-VTH)2
 Id  S×Id
 C  S×C
 tgd  S×tgd
Lower C.
Don’t scale V.
Penn ESE534 Spring 2014 -- DeHon
Don’t scale V:
VV
II/S
tgd  S2×tgd
41
…But
Power Dissipation (Dynamic)
• Capacitive
(Dis)charging
 P=(1/2)CV2f
 V V
 C  S×C
• Increase
Frequency?
 f  f/S2 ?
 P  P/S
If not scale V, power dissipation not scale down.
42
Penn ESE534 Spring 2014 -- DeHon
…And Power Density
• P P/S (increase frequency)
• But… A  S2×A
• What happens to power density?
• P/A  (1/S3)P
• Power Density Increases
…this is where some companies have gotten into trouble…
43
Penn ESE534 Spring 2014 -- DeHon
Historical Voltage Scaling
http://software.intel.com/en-us/articles/gigascale-integration-challenges-and-opportunities/
• Frequency impact?
• Power Density impact?  HW3.1
Penn ESE534 Spring 2014 -- DeHon
44
uProc Clock Frequency
MHz
The Future of Computing Performance: Game Over or Next Level?
National Academy Press, 2011
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Penn ESE534 Spring 2014 -- DeHon
http://www.nap.edu/catalog.php?record_id=12980
uP Power Density
Watts
The Future of Computing Performance: Game Over or Next Level?
National Academy Press, 2011
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Penn ESE534 Spring 2014 -- DeHon
http://www.nap.edu/catalog.php?record_id=12980
Power Density Impact
• What is the impact of power density
growing to hit our practical thermal
density limit?
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Penn ESE534 Spring 2014 -- DeHon
What Is A “Red Brick” ?
• Red Brick = ITRS Technology Requirement
with no known solution
• Alternate definition: Red Brick = something
that REQUIRES billions of dollars in R&D
investment
Penn ESE534 Spring 2014 -- DeHon
[from Andrew Kahng]
48
The “Red Brick Wall” - 2001 ITRS vs 1999
Source: Semiconductor International - http://www.e-insite.net/semiconductor/index.asp?layout=article&articleId=CA187876
Penn ESE534 Spring 2014 -- DeHon
[from Andrew Kahng]
49
ITRS 2012
Table PIDS2 High-performance (HP) Logic Technology Requirements
Year of Production
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (contacted)
38
32
27
24
21
18.9
16.9
15.0
13.4
11.9
10.6
9.5
8.4
7.5
6.7
6.0
Lg: Physical Lgate for HP Logic (nm) [1]
24
22
20
18
17
15.3
14.0
12.8
11.7
10.6
9.7
8.9
8.1
7.4
6.6
5.9
0.90
0.87
0.85
0.82
0.80
0.77
0.75
0.73
0.71
0.68
0.66
0.64
0.62
0.61
0.59
0.57
0.88
Vdd: Power Supply Voltage (V) [2]
Bulk/FD SOI/MG
EOT: Equivalent Oxide Thickness (nm) [3]
0.84
0.79
0.73
0.67
0.61
0.55
FD SOI
0.88
0.84
0.8
0.76
0.72
0.68
0.63
0.58
0.54
MG
0.92
0.88
0.84
0.8
0.76
0.72
0.68
0.65
0.62
0.59
0.56
0.53
0.5
0.47
0.45
4.5
5
6
7
7.7
8.4
9
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
10
6.3
5.7
5.2
4.7
4.2
3.7
0.99
0.96
0.93
0.9
0.87
0.85
0.338
0.320
0.301
0.284
0.261
0.238
Extended Planar Bulk
Channel Doping (1018/cm3) [4]
Extended Planar Bulk, FD SOI/MG
Junction Depth or Body Thickness (nm) [5]
8.8
8
7.2
6.4
5.7
5
FD SOI (body)
7.4
6.6
5.8
5.2
4.6
4.1
3.7
3.3
3
MG (body)
15
13.6
12.3
11.3
10.3
9.4
8.5
7.7
7
18
17
16
15
14
13
12
11
10
Extended Planar Bulk (junction)
TBOX: Buried Oxide Thickness for UTB FD (nm) [6]
UTB FD
EOTelec: Electrical Equivalent Oxide Thickness (nm) [7]
1.16
1.1
1.04
0.98
0.92
0.86
FD SOI
1.28
1.24
1.2
1.16
1.12
1.08
1.03
0.98
0.94
MG
1.32
1.28
1.24
1.2
1.16
1.12
1.08
1.05
1.02
Extended Planar Bulk
1.2
Cg ideal (fF/µm) [8]
0.658
0.632
0.611
0.594
0.576
0.565
FD SOI
0.596
0.562
0.529
0.500
0.471
0.447
0.429
0.412
0.393
MG
0.578
0.545
0.512
0.483
0.455
0.431
0.409
0.385
0.362
Extended Planar Bulk
0.696
Vt,sat: Saturation Threshold Voltage (mV) [9]
289
296
302
306
310
312
FD SOI
219
219
222
225
227
230
234
237
242
MG
206
206
207
212
217
220
223
224
225
226
228
230
231
238
237
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.15
1.21
1.27
1.33
1.40
1.47
1.54
1.62
1.70
1.78
1.87
1.97
2.07
2.17
2.32
2.47
255
171
160
143
133
114
104
Extended Planar Bulk
285
Isd,leak (nA/µm) [10]
Bulk/FD SOI/MG
Mobility Enhancement Factor due to Strain [11]
Bulk/FD SOI/MG
Effective Ballistic Enhancement Factor, Kbal [12]
Bulk/FD SOI/MG
Rsd: Effective Parasitic Series Source/Drain Resistance (Ω-µm) [13]
232
206
183
165
149
134
FD SOI
322
298
274
249
228
208
187
172
153
MG
366
343
318
285
257
235
218
202
186
Extended Planar Bulk
Penn ESE534 Spring 2014 -- DeHon
2014
50
Physical Limits
• Doping?
• Features?
51
Penn ESE534 Spring 2014 -- DeHon
Physical Limits
• Depended on
– bulk effects
• doping
• current (many electrons)
• mean free path in conductor
– localized to conductors
• Eventually
– single electrons, atoms
– distances close enough to allow tunneling
52
Penn ESE534 Spring 2014 -- DeHon
Dopants/Transistor
1000
100
1
10
100
0
500
250
130
65
Technology Node (nm)
32
16
Dopant Fluctuation
Mean Number of Dopant Atoms
10000
0.1
0.01
1000
100
Technology Nodes (nm)
53
Penn ESE534 Spring 2014 -- DeHon
10
Leads to Variation
[Borkar, IEEE Micro Nov.-Dec. 2005]
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Penn ESE534 Spring 2014 -- DeHon
Conventional Scaling
• Ends in your lifetime
• Perhaps already:
– "Basically, this is the end of scaling.”
• May 2005, Bernard Meyerson, V.P. and chief
technologist for IBM's systems and technology
group
55
Penn ESE534 Spring 2014 -- DeHon
Bob Colwell
March 2013
Penn ESE534 Spring 2014 -- DeHon
56
Conventional Scaling
• Ends in your lifetime
• Perhaps already:
– "Basically, this is the end of scaling.”
• May 2005, Bernard Meyerson, V.P. and chief
technologist for IBM's systems and technology
group
• Dennard Scaling ended
• Feature scaling another decade?
57
Penn ESE534 Spring 2014 -- DeHon
Finishing Up...
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Penn ESE534 Spring 2014 -- DeHon
Big Ideas
[MSB Ideas]
• Moderately predictable VLSI Scaling
– unprecedented capacities/capability growth
for engineered systems
– change
– be prepared to exploit
– account for in comparing across time
– …but not for much longer
59
Penn ESE534 Spring 2014 -- DeHon
Big Ideas
[MSB-1 Ideas]
• Uniform scaling reasonably accurate for
past couple of decades
• Area increase 1/S2
– Real capacity maybe a little less?
• Gate delay decreases (S)
– …maybe a little less
• Wire delay not decrease, maybe increase
• Overall delay decrease less than (S)
• Lack of V scale  Power density limit 60
Penn ESE534 Spring 2014 -- DeHon
Admin
• HW3 out
• HW1 graded
• Reading for Wednesday on Web
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Penn ESE534 Spring 2014 -- DeHon