FAULT DIAGNOSIS AND REDESIGN OF A 12-BIT SUCCESSIVE
APPROXIMATION ANALOG-TO-DIGITAL CONVERTER
A Project
Presented to the faculty of the Department of Electrical and Electronic Engineering
California State University, Sacramento
Submitted in partial satisfaction of
the requirements for the degree of
MASTER OF SCIENCE
in
Electrical and Electronic Engineering
by
Heather Renée Richardson
SPRING
2013
FAULT DIAGNOSIS AND REDESIGN OF A 12-BIT SUCCESSIVE
APPROXIMATION ANALOG-TO-DIGITAL CONVERTER
A Project
by
Heather Renée Richardson
Approved by:
__________________________________, Committee Chair
Perry Heedley, Ph.D.
__________________________________, Second Reader
Thomas Matthews, Ph.D.
____________________________
Date
ii
Student: Heather Renée Richardson
I certify that this student has met the requirements for format contained in the University
format manual, and that this project is suitable for shelving in the Library and credit is to
be awarded for the project.
__________________________, Graduate Coordinator
Preetham Kumar, Ph.D.
Department of Electrical and Electronic Engineering
iii
___________________
Date
Abstract
of
FAULT DIAGNOSIS AND REDESIGN OF A 12-BIT SUCCESSIVE
APPROXIMATION ANALOG-TO-DIGITAL CONVERTER
by
Heather Renée Richardson
The objective of this project was to debug and redesign as needed an existing but broken
12-bit successive approximation analog-to-digital converter (SA ADC) for use in an
analog front-end integrated circuit in an electrocardiogram monitoring application. The
simulation results initially obtained for the SA ADC showed that the converter obtained
roughly 6-bit resolution. The redesign effort included correcting problems found in the
connections for the reference voltage and biasing circuits, as well as redesigning the
successive approximation digital logic.
_______________________, Committee Chair
Perry Heedley, Ph.D.
_______________________
Date
iv
ACKNOWLEDGEMENTS
I would like to thank Dr. Perry Heedley for his invaluable technical insight contributing
to the completion of this report and Dr. Thomas Matthews for his involvement with not
only this project but with other endeavors over the years as well. I am so grateful to both
of them for the professional guidance I have received as well as the numerous technical
discussions I have been the beneficiary of while studying at CSUS. I would also like to
thank Steven Dehaas and Dr. Milica Markovic for believing in me as an undergraduate
student and actively encouraging my academic and professional pursuits.
I would like to thank my benevolent boss Jeff Ottlinger for supporting my academic and
professional goals and my employer, DMEA, for financially supporting my MSEE. I
would like to thank my mentor Kevin Geoghegan for all of his insight and guidance.
Special thanks to my colleagues Mike O, Ivan, Scott, Bridge, Mike G, Sack, Bill D and
Dave P from whom I have learned so much and have been great resources of support,
experience and comic relief.
My humbled thanks to my family, especially to my brilliant and wonderful father for his
insight, hilarious emails and awesome advice which were invaluable to my growth as an
individual and as an engineer. Thank you to my best friend and favorite cheerleader, my
gorgeous sister Lisa.
v
Finally and most importantly, I owe my deepest thanks to my loving, funny and
handsome husband Donald. I am indebted to and grateful for his quiet strength, patience,
steady character and loyal support throughout the last eleven years. I am truly blessed to
be married to a man who loves, inspires and challenges me the way that he does. I am
excited to close this chapter of our lives and move on to the next!
‫דֹודא יִ נֲ א‬
ֲ ‫ִדֹודא ִי‬
ֲ ‫ֲיא י‬
vi
TABLE OF CONTENTS
Page
Acknowledgements ..............................................................................................................v
List of Tables ..................................................................................................................... ix
List of Figures ......................................................................................................................x
Chapter
1. INTRODUCTION ..........................................................................................................1
1.1.
Motivation ..................................................................................................... 1
1.2.
Background ................................................................................................... 2
1.3.
Report Organization ...................................................................................... 5
2. SPECIFICATION AND ARCHITECTURE ..................................................................6
2.1.
Overview: Analog-to-Digital Converters ..................................................... 6
2.2.
Successive Approximation ADC .................................................................. 7
2.2.1.
Binary Search Algorithm .............................................................................. 7
2.2.2.
SA ADC Architecture: General Description................................................. 8
2.2.3.
Digital-to-Analog Converter ....................................................................... 12
2.2.4.
Comparator ................................................................................................. 23
2.2.5.
SAR Control Logic ..................................................................................... 29
2.2.6.
SA Architecture: Detailed View ................................................................. 32
2.3.
Error Sources .............................................................................................. 46
3. TESTING AND FAULT DIAGNOSIS ........................................................................50
3.1.
Overview of SA ADC Testing .................................................................... 50
vii
3.2.
Static ADC Testing ..................................................................................... 51
3.3.
Dynamic ADC Testing ............................................................................... 52
3.4.
ADC4 SA ADC Simulation Results ........................................................... 55
3.5.
SA ADC Fault Analysis .............................................................................. 56
3.6.
Simulation Results ...................................................................................... 60
4. REDESIGN AND SIMULATION RESULTS .............................................................64
4.1.
SAR Logic Redesign .................................................................................. 64
4.2.
SA ADC Simulation Results....................................................................... 68
5. CONCLUSION .............................................................................................................70
References ..........................................................................................................................71
viii
LIST OF TABLES
Tables
Page
Table 3.1 Specifications for the SA ADC......................................................................... 50
Table 4.1 SA ADC Performance Summary ...................................................................... 69
ix
LIST OF FIGURES
Figures
Page
Figure 2.1: SA ADC – Block Diagram ............................................................................... 8
Figure 2.2: Flow Chart for the Binary Search Algorithm used in the SA ADC ............... 10
Figure 2.3: DAC – Block Diagram ................................................................................... 13
Figure 2.4: Ideal 6-bit DAC Transfer Curve..................................................................... 14
Figure 2.5: Binary Weighted Charge Redistribution DAC............................................... 16
Figure 2.6: Binary Weighted Charge Redistribution DAC with Sample and Hold .......... 17
Figure 2.7: DAC with the MSB set = 1 and all other bits = 0 .......................................... 19
Figure 2.8: Capacitive voltage divider formed when b5 = 1 and all other bits = 0 .......... 19
Figure 2.9: Equivalent Voltage Divider with a DAC code of 100000 ............................. 20
Figure 2.10: Capacitive voltage divider formed when b4 = 1 and all other bits = 0 ........ 20
Figure 2.11: Equivalent Voltage Divider with a DAC code of 010000 ........................... 20
Figure 2.12: Example of a 3-bit Resistor String DAC ...................................................... 22
Figure 2.13: Comparator – Block Diagram ...................................................................... 24
Figure 2.14: Ideal Comparator Transfer Curve ................................................................ 24
Figure 2.15: Effect of Finite Gain and Offset on the Comparator Transfer Curve ........... 25
Figure 2.16: Fully Differential Comparator – Block Diagram ......................................... 26
Figure 2.17: Latching Comparator [12] ............................................................................ 27
Figure 2.18: SAR State Machine ...................................................................................... 29
Figure 2.19: 6-bit SA ADC ............................................................................................... 33
x
Figure 2.20: 6-bit SA ADC – Clock Cycle 1 of Bit Cycling Mode .................................. 34
Figure 2.21: 6-bit SA ADC – Clock Cycle 2 of Bit Cycling Mode .................................. 35
Figure 2.22: 12-bit SA ADC ............................................................................................. 37
Figure 2.23: Ideal bipolar 6-bit DAC Transfer Curve ...................................................... 40
Figure 2.24: Example 6-bit ADC Transfer Curve ............................................................ 42
Figure 2.25: 12-bit Fully Differential SA ADC ................................................................ 43
Figure 2.26: Illustration of DNL and INL Errors [15] ...................................................... 48
Figure 3.1: Input Signal and Window Function Effects on Spectral Leakage [16] .......... 55
Figure 3.2: Comparator Swing Minimizing Circuit.......................................................... 58
Figure 3.3: Comparator Overdrive Recovery Test ........................................................... 59
Figure 3.4: Simulation of the SAR Logic block demonstrating error in B1 and B0 bits . 63
Figure 4.1: SAR Logic Schematic – Four Bit Example ................................................... 64
Figure 4.2: SAR Logic Simulation Results – Four bit Example ...................................... 67
Figure 4.3: SA ADC FFT Results with new control logic................................................ 68
xi
1
Chapter 1
INTRODUCTION
1.1.
Motivation
With recent healthcare trends focused on a proactive, preventative and personalized
approach the demand for portable, intelligent, reliable and low power biomedical
diagnostic devices has increased dramatically. A crucial aspect of medical diagnostics
systems is the monitoring of biopotential signals [1], such as the electrocardiogram. An
electrocardiogram (ECG or EKG) is the measurement and graphical representation of the
electrical signals associated with the heart muscles with respect to time [2].
Some applications for ECGs include monitoring the heart rate, diagnosing specific heart
problems, detecting if a heart attack has occurred, monitoring the effects of heart
medicines and aiding in the treatment of breathing problems, such as asthma. Biomedical
devices that monitor a patient’s ECG increase the patient’s autonomy and improve the
quality of their healthcare as well as their quality of life. The necessity for continuous
monitoring, ultra-low power consumption, light weight and portability of the ECG
monitoring devices have forced the design methodology to evolve from a board level
approach to system-on-a-chip (SoC) solutions [3]-[4]. The SoC approach benefits from
reduced power consumption and also results in a more compact biomedical device.
The applications of and demand for ECG monitoring devices present a challenging and
rewarding design opportunity; the goal of the BME2 graduate student design team is to
design an Analog Front-End (AFE) integrated circuit (IC) for an ECG monitoring
2
application. The role of the AFE in an ECG device is to digitize the heart signal. The
primary components of a traditional discrete ECG AFE include instrumentation
amplifiers, active filters, and analog-to-digital converters (ADCs) [5].
A 12-bit Successive Approximation (SA) ADC was designed by a prior California State
University, Sacramento (CSUS) Mixed-Signal Design Laboratory (MSDL) project team,
the ADC4 team. However, the simulated dynamic testing of the SA ADC revealed only
6-bit resolution. To leverage the work of the ADC4 project team, a fault diagnosis and
redesign of the SA ADC was performed with the ultimate goal of utilizing the SA ADC
in the BME2 project. This report presents the fault diagnosis and redesign of the SA
ADC performed using the Mentor Graphics IC Station CAD tools and targeting the
MOSIS 0.5µm 5-Volt CMOS process.
1.2.
Background
ECGs detect heart signals through electrodes placed in specific external locations on the
human body. The differential voltage between electrodes, referred to as a channel, is
displayed on a monitor and allows for the electrical activity of the heart to be monitored.
The amplitude of the differential signal is typically a few millivolts and the bandwidth of
interest is 0.5Hz to 150Hz. The actual ECG signal contains the differential signal, a
common mode signal as well as a differential electrode offset. The ECG device must
detect the heart signal as well as two reference signals; the pace and the lead-off. The
pace is a man-made signal which is generated from an implanted pacemaker. The leadoff is also a man-made signal and is used to detect when an electrode is not making good
3
contact with the body. The lead-off signal is generated by the ECG device by measuring
the impedance between the electrode and the body.
The AFE in an ECG device digitizes the input signals detected by the electrodes. Since
the ECG device is connected directly to a patient the AFE must not produce a shock
hazard for the patient or interfere with any other nearby medical equipment. The AFE
must be able to detect the three signals listed above, reject electrical noise and signals
from other equipment and muscles, operate on signals which vary in amplitude and
frequency, and also recover quickly from a defibrillation event.
The dynamic range specification of the AFE is determined by the magnitude of the actual
heart signal along with the required resolution of the heart signal and the bandwidth
specification is determined by the frequency of the heart signal. The availability and
specifications of the AFE components will determine the AFE architecture, and the
features of an AFE vary with the architecture.
The speed and resolution of the ADC will determine the processing of the ECG signal.
The speed of the ADC available for use in the AFE dictates the approach to sampling the
input signals. If a high speed ADC is available, the input channels can be multiplexed
and one ADC can be used to sample the inputs one at a time; this is referred to as
sequential sampling. If a low speed ADC is to be used in the AFE, each channel will
have a dedicated ADC which will sample all the signals at the same time; this is referred
to as simultaneous sampling. If a low resolution ADC is available for use in the AFE, a
low noise amplifier is necessary to increase the amplitude of the input signal.
4
Conversely, if a high resolution ADC is available for use in the AFE, an amplifier with a
much lower gain could be used.
Designing an AFE for an ECG application provided the BME2 team the opportunity to
not only become familiar with analog design methodology but also offered valuable time
with the professors for technical interchanges and access to industry design tools while
completing a real world project in the team environment of the CSUS MSDL. The team
environment of the CSUS MSDL emulates industry design culture where continued
technology scaling, increased IC complexity and decreased time-to-market for new
products have caused the IC design process to evolve into a project team driven effort. It
is therefore desirable that design engineers are not only technically competent but also
familiar with the IC design process and able to work effectively in a team environment.
The professors at CSUS recognized this crucial educational facet and thus created the
MSDL [6] to give graduate students valuable design and teamwork experience prior to
entering the workforce.
The analog design methodology implemented by CSUS MSDL design teams includes
four phases: the architecture phase, preliminary design phase, layout phase and the final
design phase [7]. Each phase of the design process is concluded with a structured review
during which the design team presents the results of that phase’s completed tasks to their
peers, professors and industry professionals. The goal of these reviews is to catch
mistakes before the project is fabricated in silicon and also give the students exposure to
the design review atmosphere and process.
5
The purpose of the architecture phase is to research design solutions to similar problems,
identify possible solutions, examine tradeoffs between alternative designs, and identify
potential issues. The purpose of the preliminary design phase is to design the circuit, use
simulations to show that the design meets the specifications, verify that borrowed blocks
meet the required functionality, resolve any issues, and prepare for the layout phase. The
purpose of the layout phase is to layout the new design blocks as well as to connect any
blocks which are being reused. The purpose of the final design phase is to identify and
correct any issues in the layout which will cause performance issues.
1.3.
Report Organization
Chapter 2 discusses the theory of operation of a SA ADC as well as the functions and
limitations of the sub-circuits. Chapter 3 presents the target specifications of the SA
ADC for use in the BME2 project and addresses the fault diagnosis of the SA ADC
originally designed by the ADC4 project team. Chapter 4 presents the detailed results of
the redesign effort and Chapter 5 is the summary of the project.
6
Chapter 2
SPECIFICATION AND ARCHITECTURE
2.1.
Overview: Analog-to-Digital Converters
For electronics to be used in biomedical applications, such as heart rate monitoring, the
electronics must be able to not only detect but also analyze the input signal. The heart
rate is an analog signal; a signal that has a continuous time and amplitude representation.
The electronics used to process and analyze signals in biomedical applications are
typically digital devices. Digital devices operate on binary signals and are typically
faster, less susceptible to noise, and consume less area than their analog counterparts. It
is also more straightforward to perform complex arithmetic operations on a digital signal
than on an analog signal. Thus for signal processing in biomedical applications it is
advantageous to analyze and process the signals in the digital domain.
To analyze digital signals in a biomedical device, an ADC must be available to translate
the analog biomedical signal into a digital signal which can be used by the digital signal
processing electronics. The ADC performs this function by sampling the analog input
signal and creating a digital representation of the signal which can then be used for
analyzing or processing.
ADCs are characterized by their speed and resolution. Many ADC architectures exist and
the choice of architecture is application specific and involves tradeoffs between speed
and resolution. The speed of the ADC refers to the rate at which the input is sampled.
Converters which sample the input at a rate near the theoretical minimum of twice the
7
input signal frequency are referred to as Nyquist-rate converters. The resolution of the
ADC is determined by the number of digital output bits; for an ADC with N-bit
resolution, 2N digital output codes exist to describe the sampled analog input.
2.2.
Successive Approximation ADC
SA ADCs are a type of Nyquist-rate converter. They are medium speed and resolution
converters and are commonly used due to their moderate circuit complexity. SA ADCs
utilize a binary search algorithm to convert an analog input signal to an N-bit digital
code. The SA ADC designed by the ADC4 graduate student design team is a 12-bit
fully-differential SA ADC implemented with a hybrid capacitor-resistor approach. To
understand the functionality and architecture of the SA ADC it is useful to understand a
general description then add detail incrementally to the description so that the switching,
control signals and the expected voltage values can be understood.
2.2.1. Binary Search Algorithm
The main operating principle of the SA ADC is the binary search algorithm [8]. The
binary search algorithm can be explained by a guessing game in which one has to guess a
number between 1 and 64. To find the answer by asking the fewest questions the search
space should first be divided in half. Thus the question “Is the number greater than 32?”
is asked. If the answer is yes the search space is then between 33 and 64. The search
space can again be divided in half by asking “Is the number greater than 48?”, if the
answer is yes, the search space is then between 49 and 64 and again can be divided in
half and another guess can be made. This continues until the correct answer is
8
determined; for a data set with 2N values the correct answer will always be found after N
steps.
2.2.2. SA ADC Architecture: General Description
The general building blocks needed to implement a binary search algorithm in a typical
SA ADC are shown in Figure 2.1. The sample and hold circuit is used to capture the
analog input, VIN , and the comparator is used to compare the analog input to a variable
reference voltage, VDAC . The SAR and control logic is a digital logic block which
implements the bit switching sequence necessary for the binary search algorithm and
controls the bit settings for the digital-to-analog converter (DAC). The DAC generates
the reference voltage which is varied during the binary search, VDAC .
VIN
S/H
+
COMP
Successive Approximation
Register
(SAR) and Control Logic
b0
VDAC
b1 ……….
bN
DAC
VREF
Figure 2.1: SA ADC – Block Diagram
For implementation in an SA ADC, the binary search will use a sequence of possible
N-bit ADC output codes to determine the final code that represents a particular analog
voltage. For an N-bit ADC the search space is between the positive and negative
reference voltages and is divided in half N times by the digital sequence so that the
9
correct code representing an analog input value can be found in N steps. Essentially, the
output voltage of the DAC, VDAC , will be the “guessed” value of the binary search
algorithm. Each step in the binary search algorithm will determine one bit of the final
ADC digital output code. Figure 2.2 is a flowchart illustrating the binary search
algorithm implemented in the SA ADC.
10
Start Conversion
Sample Vin, Reset i  N -1, VDAC  0
bi = 1
VDAC  VDAC +
VREF
2 N i
VIN > VDAC
No
bi =0
Yes
VDAC  VDAC -
VREF
2N-i
i  i 1
Yes
i0
No
End Conversion
Figure 2.2: Flow Chart for the Binary Search Algorithm used in the SA ADC
11
Consider a 4-bit case where the top of the ADC input range is VREF and the bottom of the
ADC input range is zero. A code of 0000 represents input voltages near the bottom of the
ADC input range and a code of 1111 represents input voltages near the top of the ADC
input range. At the start of the conversion cycle the analog input signal, VIN , is captured
by the sample and hold block and the bit count variable, i, is reset. The DAC voltage is
reset to the lowest reference voltage, which is zero in this case. The first step of the
binary search, dividing the search space by two, can be done by simply taking the 4-bit
digital code for the bottom of the ADC input range, 0000, and changing the MSB to a 1,
resulting in the digital code 1000. This code sets the VDAC voltage to one half of the
reference voltage, which is in the middle of the ADC input range.
The comparator in Figure 2.1 implements the VIN  VDAC decision block of Figure 2.2.
The sampled analog input voltage VIN is compared with VDAC and the output of the
comparator indicates whether the analog input voltage is greater than or less than VDAC .
The comparator decision is input to the SAR control logic, which controls the bit settings
of the DAC based on the comparator output. If VIN  VDAC the comparator output will be
high, indicating that the sampled analog input voltage is in the top half of the ADC input
range, and the control logic will keep the MSB set to a 1. If VIN  VDAC the comparator
output will be low, indicating that the sampled analog input voltage is in the bottom half
of the ADC input range. In this case, the MSB will be reset to a 0 by the control logic
and half of VREF will be subtracted from VDAC .
12
The bit count variable is reduced by 1 and if it is still greater than or equal to zero, the
sequence will repeat; this corresponds to the i ≥ 0 decision block of Figure 2.2. For this
four-bit example, the bit count variable i is equal to 2, which is still positive, so the
conversion sequence will repeat.
During the next sequence the next most significant bit will be determined. To divide the
search space in half again, this bit will be changed to a 1. If the MSB bit had remained as
a 1 from the previous sequence, the resulting 4-bit digital DAC code provided by the
control logic would be 1100. VDAC will then be equal to
3
VREF and the sampled input
4
voltage is compared with this new VDAC voltage. After the comparison this second most
significant bit will either remain high or be reset to zero by the control logic. The bit
count variable i is then decremented, compared with 0 and the sequence will repeat two
more times.
2.2.3. Digital-to-Analog Converter
The first detail to add to the general description of the SA ADC in Figure 2.1 is the
functionality, architecture and resolution of the DAC. The role of the DAC is to convert
the digital bits from the SAR control logic to an analog voltage that will be used as a
variable reference voltage for the comparator; thus the resolution of the DAC will
determine the resolution of the ADC.
13
BIN
DAC
VOUT
VREF
Figure 2.3: DAC – Block Diagram
Figure 2.3 illustrates a block diagram for a DAC; BIN denotes the digital input bits and
VOUT is the analog output voltage which is related to the digital code BIN through the
analog reference signal VREF . For a DAC with N-bit resolution, bit bN is the most
significant bit and bit b0 is the least significant bit. The relationship between the input
code and output voltage for a 6-bit DAC is given by the following equation.
VOUT  VREF (b5 21  b4 22  b3 23  b2 24  b1 25  b0 26 )
(Equation 2.1)
For an N-bit DAC there are 2N possible analog output voltages; thus it is useful to define
the minimum incremental voltage step by which the output can increase or decrease.
This is referred to as VLSB and is defined in Equation 2.2.
VLSB 
VREF
2N
(Equation 2.2)
In addition to VLSB it is also convenient to define an LSB unit that can be used when
discussing errors. Equation 2.3 defines this unit, referred to as an LSB, which is
dependent on the resolution of the converter.
1 LSB 
1
2N
(Equation 2.3)
14
From Equation 2.1 the transfer curve for an ideal 6-bit converter can be created. The goal
of the transfer curve is to graphically show the analog output voltage of the DAC as a
function of the input bits increasing from 000000 to 111111, the full scale range of the
DAC. The transfer curve of Figure 2.4 is monotonic since the analog output voltage
increases as the DAC code increases and the slope of the ideal transfer function is 1.
VOUT / VREF
1
63/64
3/4
VLSB / VREF  1/ 64  1 LSB
1/2
1/4
000000
010000
100000
110000
DAC Input Code
111111
Figure 2.4: Ideal 6-bit DAC Transfer Curve
The ideal transfer curve is a straight line, however the transfer function of a non-ideal
DAC will deviate from this straight line, have a different slope and will not match the
15
ideal transfer function at each point on the curve. The deviation of the actual slope from
the slope of an ideal DAC is referred to as the gain error. It is typically expressed in
terms of LSB units or as a percentage of the full scale range of the DAC. Offset error
refers to the difference between the ideal transfer curve and the actual curve at a given
point; this is measured as the analog output voltage of the DAC when an input code of all
zeros is applied to the input. Integral non-linearity, or INL, is the deviation of the
transfer curve from the ideal straight-line. Differential non-linearity, or DNL, is the
difference between each step and the ideal step size of 1 LSB.
2.2.3.1.
Binary-Weighted Charge Redistribution DAC
Binary-weighted charge redistribution DACs are popular architectures since CMOS
technology is conducive to the fabrication of switches and capacitors and the effects of
mismatched capacitors on linearity, gain and offset can be minimized using design and
layout techniques.
Charge redistribution DACs operate using switched capacitor techniques to control the
flow of charge, with the binary-weighted capacitors dividing the total charge applied to
the array. Non-overlapping clocks are required for this architecture to ensure that charge
transfer occurs at the appropriate time and that charge is not lost.
16
VOUT
32C
16C
8C
b5
b4
b3
4C
2C
C
C
S1
b2
b1
b0
bx
BusA
BusB
VREF
Figure 2.5: Binary Weighted Charge Redistribution DAC
An example of a 6-bit binary weighted charge redistribution DAC is depicted in Figure
2.5. The output voltage of the DAC, VOUT , is connected to the top plates of the capacitors
in the array and is reset to zero when the switch S1 is on. The input bits to the DAC are
set by the control logic, and determine if the bottom plates of the capacitors are connected
to BusA or BusB. If a bit value is a 1 then the bottom plate of that capacitor is connected
to BusB and therefore connected to the reference voltage. If instead the bit value is a 0
then the bottom plate of that capacitor is connected to BusA, and therefore connected to
the lowest reference voltage used by the DAC, which is ground in this example.
Digital to analog conversion is achieved in two steps. The first step is to reset the output
voltage of the DAC, VOUT , by closing switch S1 which for this example will result in
VOUT = 0. The second step of the conversion is to set the bits of the DAC according to the
values from the control logic. Bits with a value of a 1 will be connected to the reference
17
voltage through BusB and bits with a value of a 0 will remain connected to ground
through BusA.
The circuit of Figure 2.5 can be modified to provide the sample and hold function
required for the SA ADC as well as the digital-to-analog conversion, as shown in
Figure 2.6.
VOUT
32C
16C
8C
b5
b4
b3
4C
2C
C
C
S1
b2
b1
b0
bx
BusA
BusB
S2
Vi
VREF
Figure 2.6: Binary Weighted Charge Redistribution DAC with Sample and Hold
By first sampling the analog input voltage onto the capacitor array, this circuit creates an
output voltage of VOUT  VDAC  Vi . This subtraction of the analog input voltage is done to
ease the comparator design needed for the final SA ADC which uses this DAC. By
having this circuit combine the DAC function with this subtraction of the analog input
voltage, the comparator only has to compare the output voltage of this circuit to zero
rather than needing to compare Vi to a variable reference voltage.
18
Digital to analog conversion is achieved in four steps. The first step is to reset the output
voltage of the DAC by closing switch S1 which for this example will result in VDAC = 0.
The next step is to sample the analog input voltage by setting all bits to a 1 and setting
switch S2 to connect the bottom plates of the capacitor array to the input voltage, Vi .
Switch S1 is then opened resulting in a charge proportional to Vi being trapped on the
array; at this point the capacitor array can be thought of as a battery with a voltage across
it. The next step is to reset all of the bit values back to 0, thus connecting the bottom
plates of all the capacitors to BusA, and therefore to the lower reference voltage for the
DAC, which is ground in this example. By connecting the bottom plates of all the
capacitors to ground the output voltage VOUT is set equal to - Vi . This is much like
connecting the positive terminal of a battery to ground to create a negative voltage of the
same magnitude. The final step of the conversion is to set switch S2 to connect to the
reference voltage, and then set the bits of the DAC according to the values from the
control logic. Bits with a value of a 1 will be connected to the reference voltage through
BusB and bits with a value of a 0 will remain connected to ground through BusA.
As shown in Figure 2.7, if the MSB, b5 , is set to a 1 to connect the bottom plate of the
32C capacitor to VREF through BusB and the remaining bits are all set to a 0 so that the
other capacitors are connected to ground through BusA, then the capacitors form a
voltage divider as shown in Figure 2.8.
19
VOUT
32C
16C
8C
4C
2C
C
C
b5
b4
b3
b2
b1
b0
bx
BusA
BusB
S1
Vi
VREF
Figure 2.7: DAC with the MSB set = 1 and all other bits = 0
32C
VREF
16C
8C
4C
2C
C
C
VDAC
Figure 2.8: Capacitive voltage divider formed when b5 = 1 and all other bits = 0
The circuit of Figure 2.8 can be simplified to the voltage divider of Figure 2.9, and the
resulting output voltage VDAC will be ½* VREF as long as the total capacitance in the array
is 2*32C. This shows the need for the LSB capacitor to be followed by a second
capacitor of the same value in order to ensure that the total capacitance in the array is
2*32C.
20
32C
VREF
32C
VDAC 
VREF
2
Figure 2.9: Equivalent Voltage Divider with a DAC code of 100000
If instead the second most significant bit, b4 , is set = 1 to connect the bottom plate of the
16C capacitor to VREF through BusB and the remaining capacitors are connected to ground
through BusA as shown in Figures 2.10 and 2.11, then the resulting output voltage VDAC
will be ¼* VREF .
16C
VREF
32C
8C
4C
2C
C
C
VDAC
Figure 2.10: Capacitive voltage divider formed when b4 = 1 and all other bits = 0
16C
VREF
VDAC 
48C
VREF
4
Figure 2.11: Equivalent Voltage Divider with a DAC code of 010000
21
The voltage added to the output by each successive bit can be calculated in the same way.
In general, the voltage VDAC resulting from bi is
VREF
and thus the output voltage of the
2 N i
DAC can be calculated by Equation 2.4:
VDAC  VREF (
b5 b4 b3 b2 b1 b0
     )
2 4 8 16 32 64
(Equation 2.4)
The output voltage of Figure 2.6 including Vi is then given by Equation 2.5:
VOUT  Vi  VREF (
2.2.3.2.
b5 b4 b3 b2 b1 b0
     )
2 4 8 16 32 64
(Equation 2.5)
Resistor String DAC
Another common type of DAC uses a resistive voltage divider to convert a single
reference voltage, VREF , to a set of 2N scaled reference voltages. A decoder selects one of
these reference voltages to connect to the single analog output voltage under the control
of the input digital code [9]. An example of a resistor string DAC is shown in Figure
2.12, including a unity gain output buffer used to supply output current.
22
VREF
R
R
b0
__
b0
b1
R
b0
R
R
R
R
R
-
__
__
b0
b1
b2
VDAC
Buffer
VOUT
+
b0
__
b0
b1
b0
__
__
__
b0
b1
b2
Figure 2.12: Example of a 3-bit Resistor String DAC
For N bits, 2N resistors are required, thus a 3-bit version is shown here. The digital input
bits, bi , control the binary tree-like switch array to create a connection between one point
on the resistor string and the input of the buffer. Note that the switches here are all
23
assumed to be on when their control bit is high, and off when their control bit is low. An
important feature of resistor string DACs is that they are guaranteed to be monotonic
since any node on the string must have a lower voltage than all of the nodes above it.
If the most significant bit in this example, b2 , is set to a 1 while the remaining bits are all
set to a 0 then the output of the DAC will be connected the midpoint of the resistor string
and the output voltage, VDAC , will be ½* VREF . If instead the second most significant bit
in this example, b1 , is set to a 1 while the remaining bits are all set to a zero, the output of
the DAC will be connected to the top of the second lowest resistor in the string and the
resulting output voltage VDAC will be ¼* VREF . In general, the voltage VDAC resulting
from bi is
VREF
and thus the output voltage of the DAC can be calculated by
2 N i
Equation 2.6:
VDAC  VREF (
b2 b1 b0
  )
2 4 8
(Equation 2.6)
2.2.4. Comparator
A comparator is a circuit which compares two analog input voltages and generates a
binary digital output as a result of the comparison indicating which of the analog inputs is
larger. Thus a comparator is essentially a 1-bit analog-to-digital converter. Comparators
are often used to compare a varying voltage to a reference voltage, Figure 2.13 shows the
block diagram of a comparator.
24
VIN
+
VREF
COMP
VOUT
-
Figure 2.13: Comparator – Block Diagram
If the analog input voltage, VIN , is larger than the reference voltage, VREF , the output of
the comparator will be high. If VIN is less than VREF , the output of the comparator will be
low. The transfer curve of an ideal comparator is shown in Figure 2.14.
VOUT
1
0
VIN  VREF
Figure 2.14: Ideal Comparator Transfer Curve
The resolution of the comparator, the minimum input voltage which will cause the output
to change between the two binary states, is determined by the gain of the comparator. If
the gain is infinite, the transfer curve of the comparator will have an infinite slope, as in
Figure 2.14.
A non-ideal comparator has finite gain and thus the transfer curve of a non-ideal
comparator will have a finite slope. In addition to the finite gain, a comparator transfer
curve will vary from the ideal transfer curve due to random variations in the transistors
25
used to construct the comparator. These variations cause an input offset voltage that can
be thought of as an additional voltage source present on one input of the comparator that
results in a horizontal shift of the transfer curve, indicated as VOFFSET . The finite gain of
the comparator and the effect of this offset voltage are shown in Figure 2.15.
VOUT
VOFFSET
0
1
VIN  VREF
Figure 2.15: Effect of Finite Gain and Offset on the Comparator Transfer Curve
2.2.4.1.
Comparator Architecture
The comparator architecture used in this project is a fully differential latching comparator
consisting of a preamplifier stage followed by a track and latch stage. A latching
comparator was chosen due to its availability for reuse from other projects, and its ability
small input voltages quickly while using very little power. For a fully differential
comparator a differential reference voltage, VREFP  VREFN , is compared to a differential
input voltage, VIP  VIN . Figure 2.16 shows the block diagram of a fully differential
comparator.
26
VREFP
VIP
VIN
COMP
VOUT
VREFN
Figure 2.16: Fully Differential Comparator – Block Diagram
For the SA ADC in this project, a differential input voltage needed to be compared to a
reference voltage of zero volts. Therefore the reference voltages VREFP and VREFN were
both connected to a common mode voltage. Thus the differential input voltage, VIP - VIN ,
is compared to a differential reference voltage of zero.
The latching comparator used for this project is shown in Figure 2.17. The preamplifier
is used to provide some gain before the latch, which helps increase resolution [10]. The
track and latch stage uses the positive feedback inherent in the cross-coupled NMOS pair
of devices to cause the voltage difference between the cross-coupled NMOS nodes to
grow exponentially, or “regenerate”, to a full digital logic level after the reset switch
between the two cross-coupled nodes is turned off [10]. The swing minimizing circuit,
SMC, is used to reduce charge injection from the reset switch and to control the reset
time constant in order to reduce memory effects [11].
27
VDD
PHI1
I BIAS
VOUT
V REFP
V IP VIN
VREFN
PHI1a
Preamplifier
Track and Latch
SMC
Figure 2.17: Latching Comparator [12]
The functionality of the latching comparator can be explained over two time periods
utilizing the two clocks, PHI1 and PHI1a , where the latter is an advanced version of the
former. During the first time period when both PHI1 and PHI1a are low, the NMOS reset
switch is on and connects the two sides of the latch to reset the voltage between the nodes
of the NMOS cross-coupled pair. The positive resistance provided by the reset switch is
in parallel with the negative resistance provided by the NMOS cross-coupled pair, which
yields an overall positive resistance that acts as the load for the preamplifier while the
reset switch is on [13]. The preamplifier stage amplifies the difference between the
differential input voltage and the differential reference voltage to create a small voltage
difference between the nodes of the cross-coupled NMOS pair. Then when PHI1a goes
high, the SMC lowers the voltage on the gate of the reset switch by just enough to turn
this switch off. At this point the positive feedback in the cross-coupled NMOS pair
28
causes the voltage difference between the two cross-coupled nodes to begin to grow
exponentially (i.e. regenerate). A short time later PHI1 goes high, which both turns off
the two PMOS switches used to reset the top half of the circuit containing the PMOS
cross-coupled pair, and turns on the two NMOS switches used to connect the PMOS
cross-coupled pair to the NMOS cross-coupled pair. By allowing the signal to grow
before turning on the NMOS switches errors due to charge injection from these switches
are reduced. Once the PMOS cross-coupled pair is connected to the NMOS crosscoupled pair it aids in regenerating the signal to a full digital logic level. At this point
VOUT represents the result of the comparator decision and is latched by an RS latch used
on the output (not depicted in Figure 2.17) to reduce errors from metastability [14]. In
this way, the small analog voltage from the preamplifier is regenerated into a full-scale
digital logic level which can be sent to the subsequent digital logic.
The SMC uses a programmable current source to control the bias voltage on the gate of
the NMOS reset switch. By varying the gate voltage applied to this switch to turn it on,
the resistance of the switch can be adjusted and thus the reset time constant can be
controlled to reduce memory effects. Since the SMC also limits the change in the gate
voltage applied to the NMOS reset switch to the minimum required, charge injection
from this switch is greatly reduced [11].
29
2.2.5. SAR Control Logic
The SAR control logic is a state machine implemented in Verilog which controls the
sample clock and switching scheme for both the binary weighted switched-capacitor
DAC and the resistor string DAC. The conversion sequence of Figure 2.2 is achieved by
the SAR control logic progressing through the fifteen states shown in Figure 2.18.
External
Reset
Reset
Sample
B0
Hold
B1
B11
B2
B10
B3
B9
B4
B8
B7
B5
B6
Figure 2.18: SAR State Machine
30
The first state is the reset state and is the start of the conversion sequence. The SAR
logic remains in the reset state for one clock cycle during which time the top and bottom
plates of the capacitors are reset to the common mode voltage.
The next state is the sample state, the duration of which is also one clock cycle. At the
beginning of the sample state when the clock is high, the switches for the DAC are set to
connect the bottom plates of the capacitor array in Figure 2.6 to Vi in order to sample the
analog input voltage. When the clock goes low the switch connecting the top plates of
the capacitors to ground, switch S1 in Figure 2.6, is opened. This traps a charge
proportional to Vi on the capacitor array, which samples the input voltage onto the
capacitors.
The next state is the hold state during which all the bits in the capacitor array are
switched to a 0 to connect the bottom plates of the capacitor array to BusA. By
connecting the bottom plates of all the capacitors to ground the output voltage in Figure
2.6, VOUT , is set equal to - Vi . The duration of the hold state is one clock cycle.
The SAR control logic now enters the bit cycling mode during which the logic will
progress through the B11-B0 states to determine the bit settings of the capacitor array and
resistor string DACs. The bit settings of the DACs are the digital representation of the
sampled analog input voltage. The SAR control logic will successively switch each bit
on the capacitor array high, beginning with the MSB, to connect the bottom plate of that
capacitor to the reference voltage. By doing so, a fraction of the reference voltage will be
added to the voltage on the top plates of the capacitor array, as discussed previously in
31
section 2.2.3.1. The comparator compares this voltage to a reference voltage of zero, to
determine if the polarity of the resulting voltage has changed from negative to positive. If
it has that indicates that the voltage added was too large, and the bit needs to be reset to
zero. The output of the comparator is sent to the control logic which leaves the bit being
tested high if the comparator output is low, or resets the bit to a logic zero if the
comparator output is high. One clock cycle for each bit is required to determine a
capacitor bit setting, thus the bit settings of the 6-bit DAC will be determined during the
first six clock cycles of the bit cycling mode.
Once the capacitor DAC bit settings have been determined, the control logic will
determine the bit settings for the resistor string in a similar way. Beginning with the
MSB, each bit in the resistor string DAC will be successively set to a 1 and the
comparator output will be sent to the control logic to determine if that bit in the resistor
string should remain a 1 or be reset to a 0. One clock cycle for each bit is required to
determine a resistor string bit setting, thus the six bits in the resistor string will be
determined during the remaining six clock cycles of the bit cycling mode. The end of the
conversion occurs at the end of the bit cycling mode, at which point the output of the SA
ADC is valid. The control logic then returns to the reset state and the conversion
sequence is repeated. Note that the additional clock cycle for the hold state is not really
required and bit cycling could begin immediately after the sample state ends. Also, the
user can reset the SA ADC at any time using an external reset signal to force the
converter into the reset state.
32
2.2.6.
SA Architecture: Detailed View
The circuit blocks discussed above can now be assembled into a complete, detailed view
of the SA ADC designed by the ADC4 graduate student design team. The 12-bit
differential SA ADC was implemented using a hybrid capacitor-resistor approach; the six
most significant bits are resolved using the capacitor array and the six least significant
bits are resolved using the resistor string.
Analog-to-digital conversion is accomplished in three steps. The first step is the sample
step during which the analog input voltage is sampled onto the capacitor array by opening
switch S1 in Figure 2.6. The second step is the hold step where the switches on the
bottom plates of the capacitors connect to ground through BusA, and the voltage on the
top plates of the capacitors is equal to - Vi . The last step is the bit cycling mode, where
the SAR logic cycles through states B11 through B0 in Figure 2.18 to implement the
flowchart of Figure 2.2. This determines the appropriate bit settings for the capacitor
array and resistor string DACs, which are the digital representation of the analog input
voltage and the final ADC output code.
2.2.6.1.
SA Architecture: Conversion Sequence
The description of the SA ADC will begin with a 6-bit example using single-ended
circuits, as shown in Figure 2.19, and more detail will be added as the concepts gain
complexity.
33
S2
32C
16C
8C
4C
2C
C
C
b11
b10
b9
b8
b7
b6
bx
VP
VN
+
-
COMP
VOUT
BusA
BusB
S1
Vi
VREF
Figure 2.19: 6-bit SA ADC
During the sample step, S2 is closed to set the voltage on the top plates of all the
capacitors, VP = 0. S1 is connected to Vi , b11 through b6 and bx are all connected to
BusB and Vi is connected to the bottom plate of the capacitors. At the end of the sample
step S2 is opened, which traps a charge proportional to Vi on all the capacitors in the
array, sampling the input voltage Vi onto these capacitors. During the hold step b11
through b6 and bx are all switched to BusA, which in this case is connected to ground,
resulting in VP  Vi . To prepare for the bit cycling mode, which comes next, S1 is
connected to VREF .
34
S2
32C
16C
8C
4C
2C
C
C
b11
b10
b9
b8
b7
b6
bx
VP
+
VN COMP
VOUT
-
BusA
BusB
S1
Vi
VREF
Figure 2.20: 6-bit SA ADC – Clock Cycle 1 of Bit Cycling Mode
The goal of the bit cycling mode is to incrementally add binary weighted scaled values of
the reference voltage to the voltage on the top plates of the capacitor array, which is
applied to the comparator input, in order to guess the analog input voltage consistent with
Figure 2.2 and Equation 2.1. The MSB is switched from BusA to BusB as shown in
Figure 2.20 to add half the reference voltage to VP . From the previous description of the
charge-scaling DAC the resulting voltage on VP can be calculated by Equation 2.7:
VP  Vi 
VREF
2
(Equation 2.7)
The comparison between VN ( VN  0 ) and VP is performed. If the output of the
comparator is high, the voltage VP has been increased by too much and the SAR control
logic will reset the MSB bit back to zero, thus connecting the capacitor back to ground.
35
If the output of the comparator is low, the voltage VP has not yet been increased by
enough and the MSB bit will remain as a 1 and the bit switch will remain connected to
the reference voltage.
S2
32C
16C
8C
4C
2C
b11
b10
b9
b8
b7
C
b6
C
VP
+
VN
COMP
VOUT
-
bx
BusA
BusB
S1
Vi
VREF
Figure 2.21: 6-bit SA ADC – Clock Cycle 2 of Bit Cycling Mode
If the MSB had remained connected to the reference voltage after the first comparator
decision was made, during the following clock cycle when the second most significant bit
is being determined the switches would be as shown in Figure 2.21. The resulting
voltage on VP can be calculated by Equation 2.8:
VP  Vi 
VREF VREF

2
4
(Equation 2.8)
The bit cycling continues in this way until all the bits have been determined. For the 6bit SA ADC in this example, the output of the ADC will be valid after 8 clock cycles; 1
36
clock cycle for the sample phase, 1 clock cycle for the hold phase and 6 clock cycles for
the bit cycling. Note that the additional clock cycle for the hold phase is not required and
bit cycling could begin immediately after the sample phase.
To implement the charge scaling DAC in the SA ADC, bits bx and b11 through b6 will be
controlled by the SAR control logic. The settings of bits b11 through b6 correspond to the
6 MSBs of the digital output of the ADC. For the SA ADC to obtain 12-bit resolution,
the 6-bit resistor string DAC will be added to the capacitor array using the switch
controlled by bx . By utilizing a hybrid capacitor array and resistor string architecture, the
matching requirements for the capacitors and resistors are greatly reduced.
The resistor string DAC output voltage is used as a variable reference voltage which
replaces the reference voltage for the last capacitor (C) in the array as shown in Figure
2.22. The 6-bit resistor string DAC is identical to the resistor string DAC of Figure 2.12
but with 6-bits instead of 3-bits and without the buffer amplifier. Bits b5 through b0 are
used by the resistor string DAC and controlled by the SAR control logic. The settings of
these bits correspond to the 6 LSBs of the ADC digital output code.
37
S2
32C
b11
16C
8C
b10
4C
b8
b9
2C
b7
C
b6
C
bx
VP
V
+
VN COMP OUT
-
BusA
Vi
BusB
VRES
S1
Vi
VREF
Figure 2.22: 12-bit SA ADC
For the circuit shown in Figure 2.22 the sample and hold steps proceed in the same
manner as they did for the circuit shown in Figure 2.19 with bx set to a 1 to connect to Vi
during the sample state, then bx set to a 0 to connect to VRES during the hold step. The
value of bx will remain a 0 and be connected to VRES for the remainder of the conversion
sequence.
Initially, all bits on the resistor string are set to zero. Thus the voltage VRES is at the
lowest voltage on the resistor string, which for the resistor string DAC shown in Figure
2.12, is zero. Thus the voltage VRES is equal to the voltage on BusA and there is no
change in the operation of the conversion sequence for the 6 MSBs with the addition of
the resistor string DAC.
38
Once the six most significant bits, b11 through b6 have been determined, the bit cycling
then begins on the resistor string. The resistor string MSB is switched from 0 to 1 while
the remaining bits in the string remain at 0. This results in the voltage output of the
resistor string, VRES , to be
1
VREF , resulting in a change in the voltage VP equal to half
2
that provided by the smallest capacitor in the capacitor array. VP is compared to VN and
the result of the comparator decision will determine if the MSB on the resistor string
remains high or is reset to 0. As with the capacitor array, if the comparator output is high
this indicates that too much voltage has been added to VP and so the bit is reset to a logic
0. If the comparator output is low this indicates that the voltage added to VP has not yet
caused VP to go above zero volts, so the bit is kept as a logic 1. If the MSB remains
high, this indicates that the voltage tap on the resistor string which will result in the
correct “guessed” voltage must be higher on the resistor string than
1
VREF . Then when
2
the next most significant bit is switched high the resulting voltage on VRES will be
VREF VREF

. If instead the MSB bit is reset, this indicates that the “guessed” voltage
2
4
value is above the correct reference voltage. Thus the voltage tap on the resistor string
which will result in the correctly guessed voltage value must be lower on the resistor
1
string than VREF . In this case, with the MSB reset to a logic 0, when the next most
2
39
1
significant bit is switched high the resulting voltage on VRES will be VREF . Each
4
subsequent bit in the resistor string is determined in the same way.
2.2.6.2.
SA Architecture: Full Scale Range
The 12-bit SA ADC described in this report uses a bipolar full scale input range of +/- 3V
achieved through two single-ended reference voltages, VREFP and VREFN . These singleended reference voltages establish the full-scale input range of the ADC which is
between VREF and VREF as defined in Equations 2.9 and 2.10:
VREF  VREFP  VREFN
(Equation 2.9)
VREF  VREFN  VREFP
(Equation 2.10)
This requires a modification to the reference voltage scheme described in section 2.2.3
for the capacitor array and resistor string. For the capacitor array, BusA will no longer be
connected to ground but will be connected to the lowest reference voltage, VREFN and
switch S1 will toggle between Vi and VREFP . The top of the resistor string will be
connected to VREFP and the bottom of the resistor string will connect to VREFN . The transfer
curve of Figure 2.4 can be modified to that of Figure 2.23.
40
DAC Output
63VREF
64
VREF
2
0
VREF
2
VREF
000000
010000
100000
110000
111111
DAC Input Code
Figure 2.23: Ideal bipolar 6-bit DAC Transfer Curve
2.2.6.3.
SA Architecture: Differential Input Configuration
The final element to add to the SA ADC description is the differential input scheme. A
fully differential ADC offers improved noise rejection, increased dynamic range and
superior DC and AC common-mode rejection compared to a single-ended
41
implementation. The output of a differential ADC is the digital representation of the
differential input signal. The differential input signal is defined by Equation 2.11:
VID  VIP  VIN
(Equation 2.11)
The single-ended inputs to the ADC, VIP and VIN , are centered around the input commonmode voltage, VCM , and the full-scale range of the differential input is between VREF
and VREF . The SA ADC uses offset binary encoding of the digital output code in order
to represent positive and negative differential input voltages. Figure 2.24 illustrates the
ADC transfer curve.
When the differential input voltage is zero, the MSB in the ADC output code is a one
while the remaining bits are all zeros. The ADC output code increases as the differential
input voltage increases. Conversely, the ADC output code decreases as the differential
input voltage decreases.
42
ADC
Output
Code
111111
100000
000000
VREF
VID
0V
ADC Differential Input Voltage
VREF
Figure 2.24: Example 6-bit ADC Transfer Curve
To create the fully differential SA ADC shown in Figure 2.25 from the single-ended
version shown in Figure 2.22, an identical copy of the capacitor array previously shown
connected to the comparator's VP input must be connected to the comparator's VN input.
Also the single input signal must be replaced with the two single-ended input signals, VIP
43
and VIN , which make up the differential input signal, VID . Similarly, the single reference
voltage must be replaced with the two single-ended reference voltages, VREFP and VREFN ,
which make up the differential reference voltage, VREF . In addition the single output
from the resistor DAC must be replaced with the two single-ended resistor-string DAC
output voltages, VRESP and VRESN , which make up the differential resistor-string DAC
output voltage, VRES . Finally, the S2 switch which shorts the comparator input VP to
ground in Figure 2.22 is instead connected to the common-mode input voltage for the
comparator. The resulting fully differential circuit is shown in Figure 2.25.
32C
16C
8C
4C
2C
C
C
b11
b10
b9
b8
b7
b6
bx
BusA
BusB
VREFN
VCM
S2
VIP
VRESN
S1
VP
VN
VREFP
VREFN
VIP
VIN
+
COMP
-
S1
VREFP
VIN
BusB
BusA
b11
b10
b9
b8
b7
b6
bx
32C
16C
8C
4C
2C
C
C
VRESP
Figure 2.25: 12-bit Fully Differential SA ADC
S2
VCM
VOUT
44
When the analog input to the SA ADC is sampled onto the capacitor arrays, VIP will be
sampled onto the bottom plates of the capacitors connected to VP and VIN will be sampled
onto the bottom plates of the capacitors connected to VN . The differential architecture
results in a modification to the explanation of the voltage on the capacitor arrays during
the hold step. During the sample step the voltage across the capacitor array connected to
VP is equal to the common-mode voltage, VCM , minus the input voltage, VIP . The total
charge on the capacitor array is proportional to this potential difference times the total
capacitance of the array. When the bits are switched to BusA, which is now connected to
VREFN , at the beginning of bit cycling the voltage on VP changes and since charge is
conserved the voltage difference between VREFN and VIP is added to VP . During the bit
cycling mode when the MSB is switched high, the MSB capacitor in the VP array will be
connected to VREFP while all the remaining capacitors are connected to VREFN . Half of the
difference between VREFN and VREFP will be added to VP , and since this is a positive
voltage this will result in the voltage on node VP increasing.
Similarly for the voltage VN , the voltage across the capacitor array during the sample step
is equal to the common-mode voltage minus the sampled input voltage, VIN . When the
bits are switched to BusA at the beginning of bit cycling, the voltage difference between
VREFP and VIN is added to VN . During the bit cycling mode when the MSB is switched
high, the MSB capacitor in the VN array will be connected to VREFN while all the
45
remaining capacitors are connected to VREFP . Half of the difference between VREFN and
VREFP will be added to VN , and since this is a negative value this will result in the voltage
on node VN decreasing. Since the voltage on the VP input to the comparator is increasing
during the bit cycling mode and the voltage on the VN input is decreasing during the bit
cycling mode, the voltages VP and VN converge towards the common-mode voltage
during bit cycling. This causes the differential input voltage for the comparator, VP - VN ,
to converge to zero during bit cycling.
A necessary requirement for the resolution of the comparator emerges from this
explanation. For a 12-bit SA ADC the LSB size is
1
2(VREFP  VREFN ) . Since the inputs
212
to the comparator converge as each bit is resolved, it becomes apparent that the
comparator must be able to resolve a differential input voltage difference smaller than 1
LSB in order for the SA ADC to achieve the required resolution. However, it should be
noted that the input referred offset voltage of the comparator will only cause an offset in
the ADC transfer curve, not a linearity error.
2.2.6.4
SA Architecture: Control Signals
CMOS transmission gates are used for the switches in the SA ADC and the control
signals generated by the digital logic are either 1 or 0. For the bit switches b11 through b6 ,
a bit value of a 1 will connect the bottom plate of that capacitor to BusB, and a 0 will
connect the bottom plate of that capacitor to BusA. The sample signal, SWT, controls
switch S2 and is slightly advanced in time compared to the signal controlling S1 in order
46
to reduce errors from signal dependent charge injection. When the signal SWT is a 1, S2
is connected to the common-mode voltage, thus setting VP and VN to the common-mode
voltage. Shortly after SWT goes to a 1, S1 connects BusB to the input voltage. During
this time all bits are also a 1 and the bottom plates of all the capacitors are connected to
BusB and thus connected to the input voltage. When the SWT signal goes low, the signal
charge is trapped on the capacitor array. Then S1 connects BusB to the reference
voltage.
Since bx is connected to the input signal during the sample phase and connected to the
resistor string at all other times it makes sense to have bx controlled by the same signal
which controls S1. Thus when S1 connects to the input, at the same time bx will connect
to the input, and when S1 connects to the reference, at the same time bx will connect to
the variable reference voltage provided by the resistor string.
2.3.
Error Sources
The performance of the SA ADC will be limited by non-idealities in the circuit blocks
such as the gain and offset errors previously discussed for the DAC. In general, the most
critical non-idealities that must be examined are those which lead to non-linearity and
therefore distortion [12]. The SA ADC architecture will have errors due to mismatches
between the capacitors in the switched-capacitor DAC, mismatches between the resistors
in the resistor string DAC, and the accuracy limitations of the comparator. It should be
noted that charge injection errors due to mismatches between the two S2 switches are not
47
signal dependent, and so only contribute an offset voltage to the overall ADC transfer
curve, not nonlinearity or distortion.
The errors in the DAC are measured in terms of LSB units and degrade the overall
performance of the SA ADC. The actual ADC will suffer from both integral (INL) and
differential (DNL) non-linearity errors.
For an ideal ADC the slope of the transfer curve will be one, meaning for that each
increasing digital code the analog input should have increased by 1 LSB. The difference
between the actual increase of the analog input resulting in a 1 LSB change in the output
code and the ideal difference of 1 LSB is the DNL error. An ADC with a monotonic
transfer curve with no missing codes will have a maximum DNL error less than 1 LSB
[15], where monotonic refers to a transfer function that always increases as the input
increases. The difference between the actual transfer function and an ideal straight line,
measured at each point along the line, is the INL and is the integral of the DNL. Figure
2.26 illustrates the ideal transfer function of a 2-bit ADC including DNL and INL errors.
Note that, as shown in Figure 2.26, INL is typically measured compared to a straight line
passed through the endpoints of the actual transfer curve. This is done to separate
linearity errors from linear gain errors.
48
Figure 2.26: Illustration of DNL and INL Errors [15]
The matching of the capacitors in the switch-capacitor DACs is crucial in order to create
the voltage divider necessary to implement the binary search algorithm. Variations in
capacitor values will result in differences between the theoretical voltage and the actual
voltage by which the inputs to the comparator are incremented during bit cycling. This
will cause the transfer function of the DAC to vary from the ideal transfer function shown
previously in Figure 2.4, resulting in differential and integral non-linearity errors.
The resistors in the resistor string DAC are designed to be the same value and need to
match to ensure that the voltage taps on the string are incremented or decremented by the
same voltage. This is to say that if the voltage between the positive reference and the
first tap below the reference is measured, the ΔV measured will be the same as the ΔV
measured between the first tap below the reference and the second tap below the
reference. This will also hold true for any two adjacent taps on the resistor sting,
assuming good resistor matching. This results in a ΔV step between each tap on the
49
resistor string. If the resistor values do not match properly the result will be variations in
the ΔV between the taps on the resistor string. This variation in voltage values will cause
the transfer function of the resistor string DAC to vary from the ideal transfer function
shown in Figure 2.4, resulting in INL and DNL errors. The hybrid capacitor-resistor
DAC approach used for this SA ADC was chosen to relax the matching requirements for
each of these two DACs.
50
Chapter 3
TESTING AND FAULT DIAGNOSIS
3.1.
Overview of SA ADC Testing
The two main types of testing used to evaluate the performance of an ADC are static and
dynamic testing. The static performance of an ADC relates to the accuracy of the analogto-digital conversion and includes the parameters relating to offset voltage, gain error and
nonlinearity, namely the INL and DNL specifications. The dynamic performance of an
ADC relates to the repeatability of the conversion and includes the signal-to-noise plus
distortion ratio (SNDR) and the total harmonic distortion (THD) specifications. Table
3.1 lists the target performance specifications for the 12-bit SA ADC reported here.
Parameter
VDDA
Resolution
ENOB
SNDR
INL
DNL
Input Range
CLK Freq
Description
Power Supply
Number of Bits
Effective Number of Bits (Accuracy)
Signal-to-Noise plus Distortion Ratio
Integral Non-Linearity Error
Differential Non-Linearity Error
Analog Input Signal (differential)
Conversion Rate
MIN NOM MAX
4.5
5.0
5.5
12.0
11.5
71
+/- 1
+/- 0.5
+/-3.0
8k
Units
Volts
Bits
Bits
dB
LSB
LSB
Volts
Hz
Table 3.1: Specifications for the SA ADC
The signal-to-noise plus distortion ratio, SNDR, is the ratio of the power of the desired
signal in the output to the power of the noise and distortion contributions from the ADC
and is defined in Equation 3.1:
51
SNDR dB =10*LOG10 (
Signal Power
)
Noise + Distortion Power
(Equation 3.1)
The theoretical value of SNDR for an ideal N-bit converter is defined by Equation 3.2:
SNDRdB  6.02* N  1.76
(Equation 3.2)
Another way to represent SNDR is to solve Equation 3.2 for N, resulting in Equation 3.3.
Equation 3.3 is referred to as the effective number of bits (ENOB) and indicates the
number of bits an ideal converter would have with the same SNDR.
ENOB 
3.2.
SNDR  1.76
6.02
(Equation 3.3)
Static ADC Testing
The parameters relating to the static performance of the ADC can be obtained by
measuring the overall transfer function of the ADC. Since INL, the deviation of the
transfer curve from the ideal straight-line, and DNL, the difference between each step and
the ideal step size of 1 LSB, affect the transfer function of the ADC, these two
performance parameters will determine the static performance of the SA ADC.
Static ADC testing is typically performed using histogram techniques. To collect a
histogram, the input of the ADC is driven by an input signal of a known statistical quality
over a large observation window. Since the probability density function of the input
signal is known, each ADC output code also has a known probability of occurrence.
Thus if a large number of samples is measured, the measured histogram can be compared
with the ideal probability density function of the input signal. Sine wave inputs are
52
typically used for this, since extremely pure sine waves can be obtained in practice using
filters.
The measured codes are placed in bins and each bin has a code width which is the
difference between two transition levels, where a transition level is the input voltage
corresponding to a transition between adjacent digital output codes. A histogram bin
with zero measured occurrences of that code indicates a missing code in the transfer
function. For static testing, all available ADC codes must be tested thus an input signal
slightly larger than the full-scale input range of the ADC is used. A ramp input signal
would be ideal, however due to the difficulties associated with generating an extremely
linear ramp signal for testing, a low distortion sine wave is most frequently used for
histogram testing. For a finite number of samples there is statistical error present, thus
the number of samples for the histogram test must be chosen large enough to make this
error sufficiently small [15].
3.3.
Dynamic ADC Testing
The dynamic performance parameters such as ENOB and SNDR require characterization
of the spectral components of the ADC output signal. Since Fast Fourier Transforms
(FFTs) produce the RMS frequency content of a signal over a specified period of time
during which the signal was sampled they are typically used for the dynamic testing of
ADCs.
Considerations for FFT testing include the sample rate, input signal frequency, the
desired number of samples and the sampling window. The number of samples effects
53
both the time required for the test, the sampling window, and also the accuracy of the
results. The sample rate is determined by the clock input to the ADC and the input signal
frequency is chosen such that the data samples capture as many converter codes as
possible and the input signal repeats an integer number of times during the sampling
window. This method of sampling is referred to as coherent sampling, and eliminates the
need for windowing which reduces the accuracy of the results. The integer chosen for the
number of times the input signal repeats during the sampling window should be a prime
number, to insure that all the points sampled on the input sine wave are unique.
For the SA ADC discussed here one conversion is completed every fifteen clock cycles,
thus if 256 samples are desired for an FFT, the sampling window can be calculated by
Equation 3.4:
(Equation 3.4)
sampling window = (sample period) * (number of samples) = (15*clock period)*256
The input signal must repeat an integer number of times during the sample window so
that the FFT measurement will not suffer from spectral leakage [16]. The FFT algorithm
assumes that all signals contained in the sampling window are periodic at intervals
corresponding to the length of the sampling window, meaning that the data used for the
FFT corresponds to one period of a periodic waveform. If a non-integer number of
cycles is present during the sampling window then discontinuities between successive
periods in the waveform will occur. These discontinuities are not actually present in the
signal but are a result of the assumption that the input waveform is periodic. This
violates an assumption of the FFT and the resulting FFT spectrum will not be a discrete
54
frequency spectrum but will appear smeared, as though energy from one frequency
leaked out into energy at all other frequencies. This is called spectral leakage [16].
Windowing functions can be used to minimize the effects of spectral leakage by
multiplying the signal with a windowing function which goes to zero at both ends of the
sampling window. This eliminates the discontinuities, but some accuracy is lost.
Depending on the chosen windowing function the level of the peak or the exact frequency
of a peak can be more accurately indicated. Figure 3.1 depicts the effects of integer and
non-integer numbers of cycles during the sampling window and the effects on the
frequency spectrum. Since the use of windowing functions does reduce the accuracy of
the results, it should be avoided whenever possible. Instead, the frequency of the input
signal should be carefully selected to ensure that an integer number of periods is
contained in the sampling window. Prime integers yield the best results, since this
prevents the same point on the input sine wave from being sampled more than once.
55
Figure 3.1: Input Signal and Window Function Effects on Spectral Leakage [16]
3.4.
ADC4 SA ADC Simulation Results
The ADC4 graduate design team reported FFT results indicating that the SA ADC was
obtaining approximately 6-bit resolution, as opposed to the target design specification of
12-bit resolution. This indicated significant problems with their original design, which
will be discussed in the following.
56
3.5.
SA ADC Fault Analysis
The method for completing the fault analysis of the SA ADC included three steps:
1) Gain a comprehensive understanding of the functionality of the hybrid capacitorresistor SA ADC architecture.
2) Verify the implementation of the blocks within the design.
3) Systematically verify the functionality of each block within the design.
Once the pertinent information regarding the SA ADC was aggregated and a sufficient
foundation of knowledge was developed the second step of the fault analysis began. To
verify the implementation of the blocks in the SA ADC a transient simulation was
performed to observe the digital output code while applying a ramp input signal. The
ramp signal increased at the rate of 1 LSB per conversion (15 clock periods), thus at the
end of each consecutive conversion the ADC output code should increase by 1 LSB,
resulting in the transfer function of Figure 2.18.
Initial simulation results showed incongruous output codes and random errors in the
comparator decisions. Since the comparator had previously been proven to work
correctly in silicon, the functionality of the comparator itself was not presumed to be the
problem. However, the implementation of the comparator used in this ADC could be the
culprit. Review of the netlists and simulation output file revealed two major issues:
1) No bias current was supplied to the comparator.
2) No ground connection was made in multiple design blocks.
These issues were corrected and the ramp simulation was performed again. Missing
codes were present on the 6 LSBs and after investigation it was noted that the reference
57
voltages connecting to the bottom of the capacitor arrays were improperly connected:
VRESN was connected to the capacitor array on the VN input and VRESP was connected to the
capacitor array on the VP input. The correct reference scheme of Figure 2.19 was then
implemented and the circuit was simulated again. Results of these simulations showed
that missing codes still existed and upon further investigation it became clear that the
comparator was making incorrect decisions.
The comparator utilizes a swing minimizing circuit, SMC, which reduces the signal
swing present on gate of the reset switch to reduce the amount of charge injected to the
NMOS cross-coupled pair. The SMC uses a 3-bit current DAC to provide adjustability to
the bias applied to the gate of the reset switch, which in turn sets the time constant during
the reset phase. This time constant sets the speed at which the comparator can track
changes in the input signal, as well as the ability to reduce memory of the last result
obtained.
Simulation results indicated that the comparator output was correct some of the time
however the correctness of the output appeared to be influenced by the comparator input
from the previous conversion, thus suggesting memory effects. The SMC uses 3-bits,
B0-B2, to vary the current from 200uA-900uA and is shown in Figure 3.2.
58
VDD
Vbias
M19
M20
M21
B2
B1
B0
M22
M23
M24
M25
Vreset
M26
M27
M28
phi1a
Figure 3.2: Comparator Swing Minimizing Circuit
The bit settings on the current DAC control the reset signal, Vreset, applied to the gate of
reset switch, thus controlling the impedance of the switch. A large DAC current will
result in a lower switch impedance, so the switch will appear more like a short circuit. In
this case the resulting voltages on the differential nodes of the latch will be nearly equal.
Conversely, a small DAC current will result in a higher switch impedance thus the
voltages on the differential nodes of the latch will not reset to exactly the same value but
rather retain memory of the previous decision. This is the memory affect mentioned
previously and is the subject of the overdrive recovery simulations performed next.
59
For the overdrive recovery simulations the inputs to the comparator are driven with a full
scale input in one direction, then driven to within 1 LSB of the reference in the opposite
direction on the next clock cycle. Figure 3.3 illustrates the comparator clock, input and
output voltages for a successful test.
phi1a
phi1
5V
0V
t
Clocks
+Vref
1LSB
0
Vidm
-Vref
t
Comparator Input
5V
0V
t
Comparator Output
Figure 3.3: Comparator Overdrive Recovery Test
The intent of this test was to highlight memory effects in the comparator if they existed
and also allowed for investigation into the DAC settings which will give the optimum
bias for the SA ADC application. It was noted that the clock scheme of Figure 3.3 was
not being used in the SA ADC, instead non-overlapping clocks were used. When the
overdrive recovery test was performed on the comparator using non-overlapping clocks
60
the comparator output was not always correct. Then the clocks for the comparator were
modified to use the advanced clock scheme of Figure 3.3, and the overdrive recovery
tests were performed again to determine the appropriate SMC bit settings. The bit
settings on the DAC which resulted in correct comparator decisions were 110.
3.6.
Simulation Results
These new SMC bit settings were implemented for the SA ADC comparator and a short
ramp simulation was performed again. The output bits were observed and showed that
the comparator was making the appropriate decisions. Discrete inputs which covered the
ADC input range were simulated for the ADC and a rough transfer function for the ADC
was plotted and showed that the ADC was functioning correctly. Once the coarse
functionality of the SA ADC was verified the static and dynamic testing of the ADC
began. For the dynamic testing a 256 point FFT simulation was performed with the input
signal 1dB below the full-scale range of the converter to avoid clipping. The input signal
frequency was chosen such that a prime, integer number of periods of the input signal
would be contained in the sampling window to insure that all the points sampled on the
input sine wave were unique while avoiding spectral leakage. The simulated ADC output
was imported into MATLAB where the FFT was generated. The FFT plot showed an
ENOB of 9.614 bits.
Analysis of the FFT simulation waveforms showed that the comparator was making
incorrect decisions when the differential input voltage was in the range of hundreds of
microvolts. To determine if the resolution of the comparator was in fact causing the
61
derisory ENOB value obtained in the FFT simulations, another simulation was performed
using the ELDO differential comparator macromodel. These simulation results showed
an ENOB of 9.67 bits. This result showed that the remaining problem with the SA ADC
was not in the comparator, and so further debug efforts were required.
Careful reexamination of the SA ADC output waveforms showed that the SAR logic
appeared to be setting bits B1 and B0 to incorrect values when a certain comparator input
was presented to the SAR logic. To show that the SAR logic was indeed incorrectly
setting the last two bits of the resistor string DAC, the SAR logic was simulated with the
given comparator input condition noted in the SA ADC transient output waveforms.
When the comparator output, COMPOUT, is high after a bit is set to a logic one and a
comparison is performed, the SAR logic output for that bit should remain high for the
remainder of the bit cycling. If instead the comparator output is low, the SAR logic
output for that bit should be reset to a logic zero for the remainder of the bit cycling. The
error in the SAR logic that was observed occurred when the comparator output was high
after B2 was set to a logic one and a comparison performed, then low after B1 and B0
were respectively tested during bit cycling in a similar manner. The correct output of the
digital logic under that condition should be that B2 will remain set to a one and both B1
and B0 will be reset to zeroes. The SAR logic initially correctly resets B1 to a zero,
however B1 does not stay reset for the remainder of the bit cycling. Instead B1 is set to a
one in error when B0 is determined, and B0 is also set to a one instead of a zero. These
errors in the setting of last two bits were successfully reproduced in a simulation of just
the logic block alone, and the output waveforms are shown in Figure 3.4. For this
62
simulation, the output bit B0 is shown as V(B0) in Figure 3.4 and B1 is shown as V(B1);
both bits should have been reset to a zero and remained at that value until the signal
V(SWITCH2) transitioned high. Instead, both V(B1) and V(B0) were set to a logic one
in error.
Figure 3.4: Simulation of the SAR Logic block demonstrating error in B1 and B0 bits
63
64
Chapter 4
REDESIGN AND SIMULATION RESULTS
4.1.
SAR Logic Redesign
The SAR logic was redesigned based on the sequencer architecture described by
Anderson [17]. Figure 4.1 shows a four bit example of the redesigned SAR logic. The
top row of D flip-flops (DFFs) act as a counter and shift a “1” through each DFF thereby
generating the set signals used by the bit register (the bottom row of DFFs) for bit
cycling, as well as the sample and hold signals.
Restart
INT Reset
VDD
VDD
VDD
VDD
VDD
VDD
EXT Reset
D
Q
D
Q
SET
Q
D
SET
D
Q
QB
CLR
CLR
SET
Q
QB
QB
QB
CLR
SET
D
Q
QB
CLR
NotQ3
D
CLR
CLK
Q
QB
CLR
QB
Hold
Restart
CLR
INT Reset
VDD
CLK
SET
SET
SET
D
EXT Reset
NotQ1
NotQ2
NotQ0
Sample
SetQ3
Comp
SetQ2
SET
D
SetQ1
SET
SET
Q
D
D
Q
Sample
SetQ0
SET
Q
D
SET
Q
D
SET
Q
D
Q
Sample
QB
QB
QB
CLR
QB
CLR
CLR
QB
CLR
CLR
SetQ0
NotQ0
SetQ1
QB
CLR
NotQ1
Sample
SetQ2
NotQ2
Hold
Clear
Sample
Clear
EXT Reset
B3
B2
B1
B0
Result Ready
SetQ3
NotQ3
Figure 4.1: SAR Logic Schematic – Four Bit Example
Operation of the SAR logic begins with restarting the counter which is initially
accomplished by momentarily pulling the external reset signal, EXT Reset, low upon
circuit power up then returning it high for normal circuit operation. After the external
reset signal returns high, the SAR logic must complete bit cycling one time before
65
analog-to-digital conversion can begin. The restart signal, Restart, is used to restart the
counter after each conversion sequence. When either the Restart signal or EXT Reset
signal are low, the internal reset signal, INT Reset, will also be low and the counter will
be restarted.
The conversion sequence of the SA ADC begins with the sample signal which sets all
output bits to a logic one, followed by the hold signal which resets all the output bits to a
logic zero. The internal reset signal then goes low to restart the counter and begin
shifting a “1” through the DFFs for the bit cycling step of the conversion sequence.
The DFF in the upper left of Figure 4.1 which has it’s set input connected to the INT
Reset signal controls the MSB DFF in the bit register below it. When the counter is
restarted, the output NotQ3 will transition from high to low resulting in the SetQ3 signal
pulling low, which in turn causes the output of the associated bit register, B3, to be set to
a logic one. On the rising edge of the next clock cycle the “1” in the counter will be
shifted to the second DFF and the output NotQ2 will then transition from high to low.
This will result in the SetQ2 signal being pulled low and cause the output of that bit
register, B2, to be set to a logic one. The transition of output bit B2 will clock the B3 bit
register and the output of the comparator from the previous clock cycle (namely when the
comparator is determining the setting for the B3 bit) is latched by the B3 bit register. In
this way each bit is sequentially set, the comparator decision is made to determine if the
bit should remain high or low and the bit is then set to that value on the following clock
cycle.
66
The output of the SA ADC bit register is valid once every fifteen clock cycles on the
clock cycle prior to taking a new sample and is indicated by the Result Ready signal in
Figure 4.1. Simulation results for a four bit version of the SAR logic is shown in Figure
4.2.
Figure 4.2: SAR Logic Simulation Results – Four Bit Example
67
68
4.2.
SA ADC Simulation Results
The SA ADC was simulated again to obtain an FFT and evaluate the performance of the
ADC with the modified SAR logic. The FFT results are shown in Figure 4.3 and the
performance of the SA ADC is summarized in Table 4.1. As shown, an ENOB of 11.3
effective bits was achieved after the reduced input amplitude is corrected for. Additional
FFT tests with larger input signals yielded significantly lower performance, indicating
that another potential issue likely exists that will require further investigation in the
future.
ADC time domain output
2000
ADC output code
1500
1000
500
0
-500
-1000
-1500
-2000
normalized output relative to full scale (dB)
0
5
max/min codes = 1366, -1366
10
15
sample number
20
25
ADC output spectrum
20
fs
= 533.333 Hz
fin
= 97.917 Hz
FFT pts = 256
window = rectangular
fund
= -3.525 dB
0
-20
ENOB =
SNDR =
SNR =
SDR =
SFDR =
10.711
66.245 dB
66.619 dB
77.081 dB
80.874 dB
-40
-60
-80
-100
-120
0
50
100
150
frequency (Hz)
200
Figure 4.3: SA ADC FFT Results with new control logic
250
69
Parameter
VDDA
Resolution
ENOB
SNDR
INL
Description
Power Supply
Number of Bits
Effective Number of Bits (Accuracy)
Signal-to-Noise plus Distortion Ratio
Integral Non-Linearity Error
Target
5.0
12.0
11.5
71
+/- 1
DNL
Input
Range
CLK Freq
Differential Non-Linearity Error
+/- 0.5
Analog Input Signal (differential)
Clock Frequency
+/-3.0
8k
Simulated
5.0
Table 4.1: SA ADC Performance Summary
11.3
69.77
Units
Volts
Bits
Bits
dB
LSB
LSB
+/-2.3
8k
Volts
Hz
70
Chapter 5
CONCLUSION
The objective of this project was to debug and redesign as needed an existing but broken
12-bit successive approximation analog-to-digital converter for use in an AFE IC in an
ECG monitoring application. The simulation results obtained during the fault diagnosis
of the ADC identified several design issues which contributed to the SA ADC’s poor
performance. These design issues included the improper reference voltage connections,
improper biasing of the latching comparator, the lack of a ground connection in the top
level schematic and faulty SAR logic. The redesign effort included rectifying the
reference voltage and biasing issues as well as redesigning the SAR logic. The
performance verification of the modifications proposed in this report was obtained
through an FFT of the simulated SA ADC. With these changes, the effective number of
bits achieved improved dramatically, from only 6 effective bits to an ENOB of 11.3 bits.
Unfortunately, these results required the use of a reduced input signal amplitude.
Additional FFT tests with larger input signals yielded significantly lower performance,
indicating that another potential issue likely exists that will require further investigation
in the future. Ultimately, the successful implementation of the SA ADC will be
determined by the test results obtained after fabrication of the AFE.
71
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