STUDY AND DESIGN OF ARCHITECTURE FOR BCH CODE ENCODER AND
DECODER
Anuradha A Gautam
B.E., IIIT College of Engineering, India, 2002
Komal B Tandel
B.E., C. K. Pithawalla College of Engineering, India, 2005
PROJECT
Submitted in partial satisfaction of
the requirements for the degrees of
MASTER OF SCIENCE
in
ELECTRICAL AND ELECTRONIC ENGINEERING
at
CALIFORNIA STATE UNIVERSITY, SACRAMENTO
SPRING
2010
STUDY AND DESIGN OF BCH CODE ARCHITECTURE FOR ENCODER AND
DECODER
A Project
by
Anuradha A Gautam
Komal B Tandel
Approved by:
__________________________________, Committee Chair
John C Balachandra, Ph.D.
__________________________________, Second Reader
Preetham B Kumar, Ph.D.
____________________________
Date
ii
Students:
Anuradha A Gautam
Komal B Tandel
I certify that these students have met the requirements for format contained in the
University format manual, and that this project is suitable for shelving in the Library and
credit is to be awarded for the project.
___________________________, Graduate Coordinator
Preetham B Kumar, Ph.D.
Department of Electrical and Electronic Engineering
iii
___________________
Date
Abstract
of
STUDY AND DESIGN OF BCH CODE ARCHITECTURE FOR ENCODER AND
DECODER
by
Anuradha A Gautam
Komal B Tandel
Data corruption during the transmission and reception of data because of noisy channel
medium is the most common problem faced in digital communication system. Thus, it is
hard to get the reliable communication. Thus, to get the error free communication we
need Error correction code.
BCH codes is an acronym for Bose, Ray – Chaudhuri, Hocquenghem, invented in 1960s
and today they are used as a baseline for many recent Error Correcting Codes. BCH
codes are powerful class of multiple error correction codes with well defined
mathematical properties. BCH code is used to correct multiple random error patterns. The
mathematical properties within which BCH codes are defined are the Galois Field or
Finite Field Theory. The main focus of this project is to design encoder and decoder
architecture for BCH codes. The design of an encoder is based on Liner Feed Back Shift
Register used for polynomial division and the decoder design is based on ibm algorithm
to correct the errors occurred during transmission. Also this project report contains
comparison of BCH codes with other Error Correcting codes and gives the detailed
iv
explanation of salient feature of BCH codes. The combination of BCH codes and LDPC
codes are used for error correction for satellite communication standards.
The BCH codes architecture is described using hardware description language called
Verilog and synthesized using Xilinx Webpack 10.1 ISE. The performance of the whole
model is check in terms of simulation using Xilinx Modelsim.
_______________________, Committee Chair
John C Balachandra, Ph.D.
_______________________
Date
v
ACKNOWLEDGMENTS
By the medium of acknowledgement,we would like to give my special thanks to all those
Who have helped us during the entire process of project preparation. We would like to
Express our gratitude to our project advisor Dr. John Balachandra for his guidance,
Suggestions and patience. We are indebted to him for his inspirations, exposure and the
Opportunity that we have received during our project work. It is with his guidance that
has helped us to understand all the mathematical concept of our codes.
In addition, we would like to thank Dr. Preetham Kumar, graduate coordinator of
Electrical and Electronics department, CSUS, for his valuable guidance in writing a
project report. With the help of his valuable suggestions, cooperation and support we are
able to finish our project.
We would like to pay a word of thanks to my friends who helped us throughout the
Completion of my project.
.
vi
TABLE OF CONTENTS
Page
Acknowledgments....................................................................................................... vi
List of Tables ................................................................................................................ x
List of Figures ............................................................................................................. xi
Chapter
1. INTRODUCTION………………………………………………………………….1
1.1
Overview………………………………………………………………….1
1.1.1
Digital Communication System………………………………………… . 2
1.1.2
Shannon Coding theorem ........................................................................... 3
1.2
Types of Coding Techniques……………………………………………..4
1.2.1
Block Codes………………………………………………………………5
1.2.1.1 BCH Code…………………………………………………………………5
1.2.1.2 Reed Solomon Codes……………………………………………………...6
1.2.2
Convolutional Codes………………………………………………………6
1.3
Comparison between Block codes and Convolutional codes……………...7
2. INTRODUCTION TO GALOIS FIELD AND BCH CODES ................................9
2.1
Block Codes ............................................................................................... 9
2.2
Galois Field ............................................................................................... .9
2.2.1
Roots of Equation………………………………………………………...10
2.2.2
Primitive Polynomials……………………………………………………10
2.2.3
GF (2^4)…………………………………………………………………12
2.3
Construction of binary BCH codes………………………………………13
3. ENCODER_LFSR DESIGN AND ARCHITECTURE FOR BCH CODE………15
3.1
BCH codes…………………………………………………………….15
vii
3.1.1
Encoder_LFSR Design…………………………………………………...15
3.2
Encoder_LFSR Design Architecture…………………………………….17
3.2.1
Parallel to Serial Shift Register…………………………………………..17
3.2.2
Encoder_LFSR Module – Linear Feedback Shift Register(LFSR)..……18
3.2.3
Serial to Parallel Shifter………………………………………………..19
4. ENCODER_LFSR SIMULATION AND SYNTHESIS RESULT……………..22
4.1
Encoder_LFSR Simulation Result…………………………………….22
4.2
Encoder_LFSR Synthesis Result………………………………………23
4.2.1
Encoder_LFSR- Top module………………………………. …………23
4.2.2
Parallel to Series Shifter……………………………………………....25
4.2 .3
Linear Feedback Shift Register………………………………………..27
4.2.4
Series to Parallel Shifter……………………………………………….29
5. DECODER DESIGN AND ARCHITECTURE FOR BCH CODE……………...31
5.1
Types of Decoder Design…………………………………………………31
5.1.1
Syndrome Calculator……………………………………………………...32
5.1.2
Key Equation Solver……………………………………………………..33
5.1.2.1 Berlekamp Massey Algorithm…………………………………………...34
5.1.3
Error Location-Chain’s Search..…………………………………………34
5.1.3.1 Chain Search Algorithm………………………………………………….35
5.1.4
Error Correction…………………………………………………………36
5.2
Decoder Design Architecture…………………………………………...36
5.2.1
Parallel to Serial Shifter………………………………………………...36
5.2.2
Syndrome Block…………………………………………………………37
5.2.3
Inversion-less Berlekamp Block…………………………………………39
5.2.3.1 DC Block…………………………………………………………………40
5.2.3.2 ELU Block……………………………………………………………….42
5.2.4
Chain Search Block……………………………………………………..45
viii
5.2.5
Error Correction Block………………………………………………….47
6. SIMULATION AND SYNTHESIS RESULT OF DECODER………………….51
6.1
Simulation Result of Decoder…………………………………………..51
6.1.1
Syndrome Block………………………………………………………...52
6.1.2
IBM Block………………………………………………………………53
6.1.3
Chain Search Block……………………………………………………..54
6.1.4
Error correction block..………………………………………………….55
6.2
Synthesis Result of Decoder Module.…………………………………...56
6.2.1
Syndrome Block Synthesis………………………………………………56
6.2.2
IBM Block Synthesis Result…………………………………………….58
6.2.3
Chain search block……………………………………………………....60
6.2.4
Error Correction Block…………………………………………………...62
7. PERFORMANCE CHECK OF ENCODER_LFSR DESIGN…………………..64
7.1 Encoder_LFSR Performance…………………………………………………64
7.2 Decoder Performance………………………………………………………...66
7.2.3 Features of XC3S1_IN500 FPGA Board:………………………………..68
8. CONCLUSION……………………………………………………………...........70
Appendix A…………………………………………………………………………..72
Appendix B…..............................................................................................................87
References………………………………….………………………………………..124
ix
LIST OF TABLES
Page
1. Table 2.2.2.1 Field elements of GF (2^4) and Minimal Polynomial …… ………11
2. Table 2.3.1 (15, 5) -Minimal Polynomials…..........................................................14
x
LIST OF FIGURES
Page
1.
Figure 1.1 Block Diagram of the basic communication system…………………2
2.
Figure 3.1.1 BCH Encoder_LFSR and Decoder..................................................15
3.
Figure 3.1.1.1 Encoding circuit for a (n, k) BCH code…....................................16
4.
Figure 3.2.1 Encoder_LFSR block…...................................................................18
5.
Figure 4.1.1 Encoder_LFSR simulation waveform ….........................................22
6.
Figure 4.2.1 High Level block for Encoder_LFSR Top module…………..…....23
7
Figure 4.2.2 Logic Block of Encoder_LFSR Top Module………………..…....24
8
Figure 4.2.3 High-level block of Parallel to Series Shifter………………..…....25
9
Figure 4.2.4 Logic block for Parallel to Series Shifter………………………….26
10 Figure 4.2.5 High level block of LFSR…………………………………………27
11 Figure 4.2.6 Logic block of LFSR………………………………………………28
12 Figure 4.2.7 High level block of Series to Parallel Shifter………………………29
13 Figure 4.2.8 Logic block of series to parallel shifter……………………………30
14 Figure 5.1.1 High level decoder design………………………………………….31
15 Figure 5.1.2 Conventional Syndrome Calculator[4]……………………………...33
16
Figure 5.1.3.1 Chain’s Search architecture – Error Location [12]……………….35
17
Figure 5.2.1 Block diagram of Decoder………………………………………….37
18
Figure 5.2.3.1 Cntrl Unit [11]…………………………………………………….41
19
Figure 5.2.3.2 DC Block [11]…………………………………………………….42
20 Figure 5.2.3.3 PE0 processor [11]…………………………………………………43
xi
21 Figure 5.2.3.4 ELU Block Diagram [11]…………………………………………………43
22 Figure 6.1.1 Decoder simulation waveform………………………………………….…51
23 Figure 6.1.2 Syndrome Simulation Waveform…………………………………………..52
24 Figure 6.1.3 IBM Block simulation waveform…………………………………………..53
25 Figure 6.1.4 Chain search block waveform……………………………………………….54
26 Figure 6.1.5 Error correction block waveform……………………………………………55
27 Figure 6.1.5 Error correction block waveform……………………………………………56
28 Figure 6.2.2 Syndrome Block – Logic block………………………………………………57
29 Figure 6.2.3 block – Top Module IBM ……………………………………………………58
30 Figure 6.2.4 IBM Block – Logic Design…………………………………………..……....59
31 Figure 6.2.5 Chain search block – Top module…………………………………..……….60
32 Figure 6.2.6 Chain search block- Logic block…………………………………………….61
33 Figure 6.2.7 Error correction block – Top Module………………………………………..62
34 Figure 6.2.8 Error correction block – Logic Block………………………………………..63
35 Figure 7.1.1 Design Summary of Encoder_LFSR Design – I……………………………..64
36 Figure 7.1.2 Design Summary of Encoder_LFSR Design – II……………………………65
37 Figure 7.2.1 Design Summary of Decoder – I…………………………………………….66
38 Figure 7.2.2 Design Summary of Decoder – II……………………………………………67
39 Figure 7.2.3 Pin layout of XC3S1_IN500…………………………………………………68
xii
1
Chapter 1
INTRODUCTION
1.1 Overview
In the present Digital Communication systems, it is highly possible that the data or
message get corrupted during transmission and reception through a noisy channel
medium. The environmental interference and the physical defects in the medium are the
main causes of the data or message corruption in the communication medium, which
leads to the injection of random bits into the original message and corrupt the original
message. To have a reliable communication through noisy medium that has an
unacceptable bit error rate (BER) and low signal to noise ratio (SNR), we need to have
Error Correcting Codes (ECC). The error correction is based on mathematical formulas,
which are used by Error correcting codes (ECC). Error correction is taken place by
adding parity bits to the original message bits during transmission of the data. Because of
the addition of parity bits to message bits makes the size of the original message bits
longer. Now this longer message bits is called “Codeword”. This codeword is received
by the receiver at destination, and could be decoded to retrieve the original message bits.
Error correcting codes are used in most of the digital applications, space and satellite
communication and cellular telephone networks. There are many types of error correction
codes are used in present digital communication system are based on the type of error
expected, the communication medium expected error rate, and weather re-transmission is
possible or not. Some of the Error correction codes, which are widely used these days, are
2
BCH, Turbo, Reed Solomon, and LDPC. These codes are different from each other in
their complexity and implementation [1] [5].
1.1.1 Digital Communication System
Fig 1.1 Block Diagram of basic communication system
[1] In the 1st step the message bits are given as input to the Source encoder_LFSR. This is
the module where the density of message bits is increased by compression. This module
use BCH codes or other Error correction code to encode the compressed data by adding
3
the parity bits. The output of the source encoder_LFSR is a longer information bits,
called “codeword”.
[2] This codeword is given as input to the Encrypted module. This module increases the
security of the information bits.
[3] The 3rd module is channel encoder_LFSR, which increases the reliability and the
hardware complexity of the Codeword.
[4] The output of the channel encoder_LFSR is fed to modulator, which transform the
codeword into a signal waveform. This modulated signal is now ready to transmit
through a Channel.
[5] The channel could be a physical medium or a wireless medium. The possibility that
the codeword get corrupted in the channel is high because the channel is subjected to
various noises.
[6] The corrupted signal is received at the Demodulator module at the receiver section. In
this module the signal, get de-modulated to get the corrupted codeword.
[7] The original message bits are retrieved from the corrupted codeword using the
decoding algorithm of Error correction code (ECC), which was initially used to encode
the data at the Encoder_LFSR. Thus, the original information bits are retrieved at the
output of the Source decoder [5] [6].
1.1.2 Shannon Coding theorem
Claude Shannon is credited for one of the most significant contributions about the
information theory Shannon has proposed the theorem of Channel capacity. This theorem
4
states that, “Channel capacity is the maximum rate at which bits can be sent over an
unreliable channel with arbitrarily good reliability” [3]. Shannon has verified that the
effect of transmitted power, bandwidth, and the additive noise can be related to the
channel and can be incorporated into the channel capacity.
The channel coding theory states that the reliable transmission is achievable by
performing proper coding, if the information rate (R) of the source is less than the
channel capacity (C). The major disadvantage of this theory is that, it does not contain
any details about how to make such codes. Shannon has introduced a metric by which the
information could be quantified. This metric is used to find out the minimum possible
numbers of symbols necessary for the error free representation of a given message [3]
[2].
1.2 Types of Coding Techniques
Because of the noise and interface in the channel during the transmission of information
bits, risk of data corruption is considerably high. “Channel Coding” is the technique,
which is used to sustain the originality of the information bits, to avoid the retransmission of information bits as well as to detect and correct any error, has been
occurred during transmission. A channel coding technique is applied for two types of
channel codes listed as under:
[1] Block Codes.
- BCH Code.
- Reed Solomon Code.
5
[2] Convolution Code.
- Viterbi algorithm.
1.2.1
Block Codes
Block codes are one of the types of channel codes. The definition of the block codes is,
these codes add the redundancy bits to the original message bits and transmit the resultant
longer information bits called “codeword” for error correction. Theoretically, it is
possible to decode the received codeword with zero possible error provided the coding
technique is subjected to Shannon’s channel capacity theorem. The block codes are
implemented as (n, k) codes where n indicates the codeword and the k defines the
original information bits. Therefore, the number of redundant bits need to be added in to
the original message bits are given as (n – k). The block codes are fixed channel codes.
The BCH codes and the Reed Solomon codes are the subset of the Block codes, which
are well defined as below. In this project, we had used BCH codes to design
Encoder_LFSR and Decoder [3].
1.2.1.1 BCH Codes
BCH codes are subset of the Block codes. BCH codes are belongs to a power full class of
multiple error correcting codes. BCH codes are based on well-defined mathematical
properties. These mathematical properties are based on the Galois Field or finite fields.
The Finite field has the property that any arithmetic operations on field elements always
have results in the field only. To provide an excellent error correcting capability, the
generator polynomial of the BCH codes has carefully specified roots. With a generator
6
polynomial of g(x), a t- error correcting cyclic codes is the binary BCH codes, with a
condition that g(x) must be the least degree polynomial over Galois Field GF(2). The
block length of the BCH code, constructed over GF (2^m) is given by n = 2^m – 1. BCH
codes are cyclic codes, and the degree r of the generator polynomial of a (n, k) is given
by (n-k). So, the information bits length of the BCH codes is given by k = 2^m – 1r[1][2].
1.2.1.2 Reed Solomon Codes
Reed Solomon Codes are the non- binary form of the Block codes. These codes are
defined as RS (n, k) with s- bit symbols. The RS code encoder_LFSR takes k data
symbols and, parity symbols are added to it to form n symbols codeword. The RS codes
detect and correct the errors in the symbols. These codes are constructed with encoding
and decoding techniques, which follows directly to the BCH code techniques. The major
difference between the binary BCH and non- binary RS codes is, in BCH code the error
magnitude is 1 so it needs to find out only the location of error while in non binary RS
codes the first step is to locate the error position and then correct it. Reed Solomon codes
are also follows the GF mathematics properties for encoding and decoding
techniques[7][10].
1.2.2 Convolutional Codes
Convolution codes are widely used in the error coding technique. In block codes the
output is only depends on the current input while in convolution codes the output depends
on both the present and the past output. So, it is clear that convolution codes contain
7
memory elements to store the input information bits for future use. As name indicates the
convolution codes are based on convolution operation performed on the information bits
which are input to the encoder_LFSR. Convolution codes (n, k, m) indicates n – outputs
from k- inputs and m- previous inputs. The input to the convolution codes could be
anything among continuous data streams or block data. Convolution codes use the Viterbi
algorithm as encoding and decoding algorithm. The Viterbi algorithm is based on
Forward Error Correction technique. The main characteristic of this algorithm is the fixed
decoding time and also it is well suited for hardware decoder implementation[8].
1.3 Comparison between Block codes and Convolutional codes[1][8][2].
The significant difference between block codes and Convolution codes are as followed,
[1] Compared to the Block codes the hardware complexities of the convolution codes is
more. And because of that it is hard to implement the convolution codes compared to
block codes.
[2] Unlike BCH codes, for codeword calculate (the output of encoder_LFSR) the state
transition has to be applied for convolution codes, because the encoder_LFSR output
depends on both present and past input.
[3] The bandwidth requirements of the Convolution codes are much higher than the BCH
codes.
[4] The trellis diagram of the BCH codes always starts at Zero and after n clock cycles
ends on zero as well, while this is not the case for Convolution codes.
8
[5] As we had discussed earlier that convolution codes are embedded with memory
elements, the input bits to the encoder_LFSR are stored in the encoder_LFSR register and
have to pass through those registers. This indicates that the register sequence for state
transition is non-arbitrary.
This chapter covers detailed explanation of the modern digital communication system,
channel capacity theorem and its importance in the error coding as well as different types
of coding techniques. This chapter also gives explanation about the comparison between
block codes and the convolution code. The next chapter of this project report includes the
explanation of Galois field and BCH codes.
9
Chapter 2
INTRODUCTION TO GALOIS FIELD AND BCH CODES
2.1 Block Codes
Block code is a set of words, which is called “Codeword”. In a Block codes the
Codeword is a combination of an information bits and parity bits. The information bits
are those bits which carries the message while parity bits provide security and ensure that
the codeword has a correct structure required for the Block codes. Encoder_LFSR
generates the parity bits as well as concatenates them to the information bits. For k –
information bits and r- parity bits the generated codeword n will be the sum of
information bits and parity bits, given as n= k + r.
This kind of codes is referred to as (n, k) block code. The position of the codeword is not
fixed, it could be placed at the beginning of the codes (MSB) or at the end of the
information bits (LSB). The codeword could be dispersed throughout the codeword.
There are two types of codeword called, systematic codes and non- systematic. The
codeword in which the information bits are kept together is called systematic codeword
while if the information bits are scattered is called non-systematic codeword. In (n, k)
block codes, k-bits give 2^k different codeword, there are therefore 2^k codeword in a (n,
k) code [1] [2].
2.2 Galois Field
The Galois field was invented by Everest Galois. Galois field has finite number of
elements in it. The theory of Finite field was introduced around 18th century, while its
10
importance and the widespread applications were widely recognized in recent years. The
Galois field is widely used in number theory, coding theory and cryptography. The
mathematical properties within which BCH codes are defined is also represents Galois
field. The mathematical operations like Additions, Subtractions, Multiplications and
Divisions are performed using Finite field theory. The most basic axioms of the finite
field are:
[1] All the elements in the field forms an Abelian group with additional operator “+”.
[2] The non-zero elements in the field forms group with multiplication operator “ . ”.
[3] Multiplications by any non –zero elements is an automorphism of the Additive group.
BCH codes architecture use field theory as well as polynomial over finite filed. To detect
any error has occurred during transmission a check polynomial is constructed. The BCH
code with distance δ over the finite field GF (q^m) is constructed by finding polynomial
over GF (q), whose roots include δ consecutive power of y [4] [6].
2.2.1Roots of Equation
The finite field can be calculated using roots of equation α. This is possible because of
one of the property of cyclic codes. The cyclic code has a property that all the codeword
polynomials c(x) has the generator g(x) as a factor. In other words, any root of g(x) = 0,
also give a root of c(x) =0 [4] [6].
2.2.2 Primitive Polynomials
The irreducible polynomials are defined as those polynomials which are divisible of itself
and one and which cannot be factorized. Irreducible polynomials are used to generate GF
11
(2^m). The root of irreducible polynomial is called a primitive polynomial. α is primitive
in GF(2^m) ; primitive is defined as the field element which can generate all non zero
elements of the field. Here, as the primitive element α became the root of the irreducible
polynomials, so polynomials become primitive too. For any positive integer m we can get
at least one irreducible polynomial of the degree m. It can be shown that an irreducible
polynomial of degree m is divides by x^r +1 (where r = 2^m -1), which can be used to
find out whether polynomial is an irreducible or not. To build BCH codes over GF (24),
we need to find out the minimal polynomials of powers of α. The minimal polynomials of
all elements of GF (24) are given in table below [4].
Table 2.2.2.1 Field elements of GF (24) and Minimal Polynomials [4]
12
2.2.3 GF (2^4)
The main reason of constructing a GF (2^m) is that they do not have both 0 and 1 as their
roots. This section is provided with a detailed explanation of Galois field (2^4). Consider
the below equation,
P(x) = x4 + x + 1.
(2.1)
From the above equation, it is clear that, neither 0 nor 1 is the root for of the equation. So,
we can say that the 4th equation lies outside of the GF (2^4) field. By assuming α as one
of the root of the equation, p(α) should be equal to zero. This can be explained by below
equation,
P (α) = α4 + α + 1 = 0
(2.2)
The above equation can be used to generate GF (24). Rearranging the above equation
gives,
α4 = α + 1
(2.3)
But multiplying α to the above equation gives,
α4 = α + 1
α5 = α4. α = α2 + α
(2.4)
α6 = α5. α = α3 + α2.
(2.5)
α7 = α6. α = α4 + α3
(2.6)
α8 = α7. α = α5 + α4 = α2 + 1
(2.7)
α9 = α8. α = α3 + α
(2.8)
α10 = α9. α = α2 + α + 1
(2.9)
α11= α10. α = α3 + α2 + α
(2.10)
13
α12= α11. α = α3 + α2 + α + 1
(2.11)
α13 = α12. α = α3 + α2 + 1
(2.12)
α14 = α13. α = α3 +1
(2.13)
The higher order field elements can be generated similarly by multiplying α to its
previous power. The fifteenth power of α can be calculate as below:
α15 = α14. α = 1.
Here, the simplification of the fifteenth order gives 1, which is an existing element so;
further powers of α will always give the existing elements. Therefore the field GF(24) has
the following 16 elements:
0, 1, α, α2, α3, α4, α5, α6, α7, α8, α9, α10, α11, α12, α13, α14 [4].
2.3 Construction of binary BCH codes
The BCH code has carefully specified roots to give good error correcting capability. A terror correcting code with generator polynomial g(x) is a binary BCH code if and only if
g(x) is the least-degree polynomial over GF (2) that has,
β, β2, β3,… β2t
β is an element of GF(2m). From above it is clear that with this choice of roots, the
resultant codes will be capable of correcting t – error. The generator polynomial g(x) of a
t-error correcting binary BCH code is given by,
g(x) = LCM [ m1(x), m2(x), m3(x), …., m2t(x)]
(2.14)
According to above equation (2.14), the 3-error correcting BCH code for (15, 5) code is
considered. The generator polynomial with,, 2, 3, ... , 6 as the roots is obtained by
multiplying the following minimal polynomials:
14
Roots
minimal polynomial
, 2, 4, 8
f1(x) = (x+) * (x+2) * (x+4) * (x+8) = 1 + x + x4
3, 6, 9, 12
f3(x) = (x+3) * (x+6) * (x+12) * (x+9) = 1 + x + x2 + x3 + x4
5 10
f5(x) = (x+5) * (x+10) = 1 + x + x2
Table 2.3.1 (15, 5) - Minimal Polynomials [4]
The equation for the generator polynomial g(x) is given as below [4];
g(x) = f1(x) * f3(x) * f5(x) = 1 + x + x2 + x4 + x5 + x8 + x10.
(2.15)
This chapter covers the detailed explanation about the Galois field and the Block codes. It
also covers the concept of primitive polynomial associated with the Galois field and also
it explained the construction of (15, 5) three error correcting BCH code. The following
chapter explains the BCH Encoder_LFSR design and architecture.
15
Chapter 3
ENCODER_LFSR DESIGN AND ARCHITECTURE FOR BCH CODE
3.1 BCH codes
Fig 3.1.1 BCH Encoder_LFSR and Decoder
3.1.1 Encoder_LFSR Design
The Encoder_LFSR design used in this project is most commonly used in the modern
digital communication system. This encoder_LFSR design is almost common to all the
BCH code architecture, which uses the linear feedback shift register for polynomial
division.
The format of the codeword is as follows [4]:
c(x) = xn-k * i(x) + b(x)
(3.1)
Where, codeword c(x) = c0 + c1x +...+ cn-1xn-1
information bits i(x)= i0 + i1x +...+ ik-1xk-1
remainder b(x)= b0 + b1x +...+ bm-1xm-1
also, ci, ji, bi are the subsets of Galois field. If b(x) is taken to be the polynomial such
that the k data bits will be presented in the codeword, which is given as follows:
16
xn-k * i(x) = q(x) * g(x) - b(x)
(3.2)
BCH codes are implemented as cyclic code. As a result the logic which implements
encoder_LFSR and decoder is controlled into shift register circuits. With the help of
cyclic code properties the remainder b(x) can be calculated in the linear (n-k) stage shift
register with the feedback connection to the coefficient of generator polynomial.
Fig 3.1.1.1 Encoding circuit for a (n, k) BCH code. [4]
The operation of the encoder_LFSR design of figure 3.3.1.1 is as follows [4]:
[1] For the clock cycle 1 to k,
The original message bits are transmitted without changing its form (during this operation
switch s2_in is in position 2), and the linear feedback shift register calculates the parity
bits (switch s1_in is on now).
[2] For cycle k+1 to n,
The generated parity bits in the linear feedback shift register are transmitted (switch s2_in
is in position 1) and the feedback in the LFSR is switch off (s1_in off).
17
3.2 Encoder_LFSR Design Architecture
Figure 3.2.1 shows block diagram of BCH encoder_LFSR. Basically, encoder_LFSR
module is consists of three modules.
[1] 5 bit Parallel to Serial Shift Register
[2] Encoder_LFSR module - Linear feedback shift register
[3] Serial to Parallel Shift Register
In this project we had designed three (15, 5) error correcting BCH code. The input to the
BCH encoder_LFSR is 5- bit message, which is encoded in a 15-bits codeword by adding
10-bit parity bits. The BCH encoder_LFSR uses the linear feedback shift register (LFSR)
for polynomial division. This division generates redundant parity bits.
3.2.1 Parallel to Serial Shift Register:
The input to the parallel to serial shift register is a 5 bit message bits. During the 1 st clock
cycle all the 5 message bits are given as input to the shift register. At the 1st clock cycle ld
signal is set to high (logic 1), which remains high between 1st and the 2nd clock pulse and
after that it sets to low (logic 0). So, after the 1st clock cycle all the message bits are
stored in the shift register and starting from the 2nd clock pulse the bits will start shifting
serially with each clock cycle. So, at the end of 6th clock pulse all the 5 message bits are
shifted serially at the output of the parallel to series shifter. The output of the parallel to
series shift register is given as input to the next module called encoder_LFSR module –
Linear feedback shift register.
18
The below figure shows the block diagram of Encoder_LFSR module.
Fig 3.2.1 Encoder_LFSR Block
3.2.2 Encoder_LFSR Module – Linear Feedback Shift Register (LFSR)
The Encoder_LFSR module is designed with respect to the generated polynomial given
in the equation no.(2.15). Generator polynomial is divided by the incoming 5-bits
message bits. The division is carried out using linear feedback shift register, the
remainders of this division is added with the original message bits to form a “codeword”.
The (15, 5) code has 10 bits redundant parity bits, and therefore 10 remainder stages are
required. As shown in the figure 3.2.1. These stages are labeled as d0 to d9. The
generator polynomial is represented as follow,
g(x) = f1(x) * f3(x) * f5(x) = 1 + x + x2 + x4 + x5 + x8 + x10.
The generator polynomial has g3= g6= g7= g9 = 0. So there is no feedback to d3, d6, d7
and d9. Thus the equations are:
19
bf = bin + d9.
d0 = bf
d1 = bf + d0
d2 = bf + d1
d3 = d2
d4 = d3 + bf
d5 = bf + d4
d6 = bf
d7 = d6
d8 = bf + d7
d9 = d8
bout = d9
The switch signal of Encoder_LFSR remains high during 1st 5 clock cycle to shift the 5
message bits into encoder_LFSR and then it goes low. This will allows the generation
and shifting of parity bits. After the 5 shifts the message bits enter into codeword stage,
which is also a series to parallel shifter. In codeword stage the information bits are
divided by g(x) to give required parity bits. Now next 10 stages are required to move
parity bits into codeword stage. Thus it required total 15 clock cycles to shift the
codeword in to the series to parallel shifter.
3.2.3 Serial to Parallel Shifter:
The output of the encoder_LFSR module is fed to series to parallel shifter. As its name
indicates this shifter shift the series input to the parallel output at every positive edge of
20
the clock. The hld signal of the series to parallel shifter is remain low initially. At every
clock pulse the shifter shifts the incoming serial bits to parallel output. At the 17th clock
pulse codeword- all 15 bits are shifted at the output and the hld signal is assert high, to
make sure that no extra bit will be added to the message bits. The above waveform shows
the input and output signals used for encoder_LFSR block. The signals used in the
waveform are given as:
Input signals:

5 bits message – ‘msgs’

Clock – ‘clk’

Reset – ‘reset’

Start signal for the encoder_LFSR – ‘active_encoder_LFSR’

Counter – ‘cntrl’

Initialize – ‘init’

Ld signal for Parallel to Serial shifter – ‘ld’

Hld signal for serial to parallel shifter – ‘hld’

Switch signal for encoder_LFSR block – ‘switch’

15 bits codeword – ‘out’
Cntrl Signals:
Output signals:
21
The shown waveform is the simulation result of Encoder_LFSR module, the input to the
encoder_LFSR circuit is 5 bits message bits ”msgs”, and the output is 15 bits codeword
called “out”.
5 bit Message ‘msgs’ – ‘00001’
15 bit Codeword ‘out’ – ‘000010100110111’
22
Chapter 4
ENCODER_LFSR SIMULATION AND SYNTHESIS RESULT
4.1 Encoder_LFSR Simulation Result
Fig 4.1.1 Encoder_LFSR simulation Waveform
23
Fig 4.1.1 shows the flow of signal from input to output through three different stages of
encoder_LFSR. All three blocks has its own cntrl units and signals to check the data flow
of individual block.
Input to encoder_LFSR = 5 bits message = 11110.
Output of encoder_LFSR = 15 bit codeword = 000100110101111.
4.2 Encoder_LFSR Synthesis Result
The following figures shows the synthesis results of the Top module of encoder_LFSR
design as well as the synthesis results of sub modules of encoder_LFSR.
4.2.1 Encoder_LFSR- Top module
Fig 4.2.1 High level block for Encoder_LFSR Top Module
24
Fig 4.2.2 Logic Block of Encoder_LFSR Top Module
25
4.2.2 Parallel to Series Shifter
Fig 4.2.3 High level block of Parallel to Series Shifter
26
Fig 4.2.4 Logic block of Parallel to Series Shifter
27
4.2.3 Linear Feedback Shift Register
Fig 4.2.5 High level block of LFSR
28
Fig 4.2.6 Logic block of LFSR
29
4.2.4 Series to Parallel Shifter
Fig 4.2.7 High level block of Series to Parallel Shifter
30
Fig 4.2.8 Logic block of series to parallel shifter
31
Chapter 5
DECODER DESIGN AND ARCHITECTURE FOR BCH CODE
5.1 Types of Decoder Design:
The high level decoder design is shown in the figure 5.1.1
Fig 5.1.1 High level decoder design
Where, R = Received data, S = Generated Syndromes, Λ = Error locator polynomial.
Fig 5.1.1 High Level Decoder Design
The BCH decoder has four modules as mentioned below:
-
Syndrome Calculator
-
Solving the key equation
-
Error Location
-
Error Correction
The implementation and the algorithms used to design above modules are varies with the
architectures. The 2nd module, Solving the key equation is the most difficult and complex
module as compared to the other modules in respect to the hardware complexity. This
chapter contains the detailed explanation of the different algorithms used to implements
those modules.
32
5.1.1 Syndrome Calculator:
The syndrome calculator is the first module at the decoder also, the design of this module
is almost same for all the BCH code decoder architecture. The input to this module is
corrupted codeword. The equations for the codeword, received bits and the error bits are
given in equations (5.1), (5.2), (5.3)[4].
c(x) = c0 + c1x + c2x2 + ... + cn-1xn-1
(5.1)
Received bits equation
r(x) = r0 + r1x + r2x2 + ... + rn-1xn-1
(5.2)
Error bits equation
e(x) = e0 + e1x + e2x2 + ... + en-1xn-1
(5.3)
Codeword equation
Thus, the final transmitted data polynomial equation is given as below:
r(x) = c(x) + e(x)
(5.4)
The 1st step at the decoding process is to store the transmitted data polynomial in the
buffer register and then to calculate the syndromes sj. The important characteristic of the
syndromes is that depends on only error location not on transmitted information. The
equation of the syndromes are given as follows [4]:
Define the syndromes Sj as
n1
S j   ri i j
for (1  j  2t).
i0
Since rj = cj + ej (j = 0, 1, ...., n-1)
Rewrite the syndrome equation as:
n1
n1
n1
i 0
i 0
i 0
S j   (c i  e i ) i j  c i i j   e i i j
By the definition of BCH codes
33
n1
c 
i 0
i j
for (1  j  2t)
0
i
Thus,
n 1
S j   ei i j
(5.5)
i 0
The above equation (5.5) is indicates the output of the syndrome calculator. From the
equation it can be observed that the syndromes are depends on only error polynomial
e(x), so if there is no error occurs during the transmission then all the generated
syndromes will be zero.
The architecture of the syndrome calculator is shown in the below figure 5.1.2 based on
equation 5.5.
Fig 5.1.2 Conventional Syndrome Calculator[4].
5.1.2 Key Equation Solver
The second stage in the decoding process is to find the co-efficient of the error location
polynomial using the generated syndromes in the previous stage. The error location
polynomial is given as: (x) = 0 + 1x + ... + txt. The relation between the syndromes
and the error location polynomial is given as below [4]:
t
S
j 0
t i j
j 0
(i= 1, ..., t)
34
There are various algorithms used to solve the key equation solver. This project is using
the Inversion less Berlekamp Massey algorithm to solve the key equation.
5.1.2.1 Berlekamp Massey Algorithm [4][13].
The steps of berlekamp Massey algorithm is given as below:
1. First step is to calculate error syndromes Sj.
2. Initialize the k = 0, Λ(0)(x) = 1, L = 0 and T(x) = x
3. Assign k = k + 1 and then the discrepancy Δ(k) is then calculated as follows:
4. If the value of Δ(k), 2L ≥ equals 0, then go-to step 7.
5. Calculate the Λ(k)(x) = Λ(k-1)(x) - Δ(k) T(x)
6. Set the value of L = k – L and T(x) is calculated as
T(x) = Λ(k-1)(x) / Δ(k)
7. Set T(x) = x.T(x).
8. If the value of k< 2t , then go-to step 3
9. Continue for i = 2t – 1 and then End.
The decoder of this project is based on the Inversion-less Berkelamp algorithm (iBM)
for Key Equation Calculation. The architecture for iBM algorithm is explained in
detail in the next chapter.
5.1.3 Error Location – Chain’s Search
To calculate the error location is the next step of decoding process, which can be done
using chain search block.
35
5.1.3.1 Chain Search Algorithm
The roots are calculated as follows [12] [4]:
1. For each power of α for ( j = 0 to n – 1), αj is taken as the test root
2. Calculate the polynomial coefficients, of the current root using, coefficients of the
past iteration, using, Λ i(j) = Λ i(j-1) αi during the jth iteration
3. Calculate the sum of the polynomial coefficients
4. The sum is equal to
5. Continue to Step 1 till j = n-1
Fig 5.1.3.1 Chain’s Search architecture – Error Location [12]
To locate the roots of the polynomial, chain search block is implemented in hardware for
the BCH decoder. The chain search block has a property that the roots going to be a
power of α reduce the evolution of the polynomial for every root. So, the use of the chain
search block provide the computational benefits of the step, Λ
i
(j)
= Λ
property makes the chain search method more superior then other methods.
i
(j-1)
αi. This
36
5.1.4 Error Correction
The output of the chain search block is called roots of equation. The reciprocal of the
roots of equations are added with the corresponding location of the corrupted codeword
received by decoder. The result of this addition is the original codeword that was encoded
by the encoder before transmission.
5.2 Decoder Design Architecture
The Decoder design is consists of 5 blocks. These blocks are:
1. Parallel to Serial Shifter
2. Syndrome Block
3. Inversion-less Berlekam Massey Block
4. Chain Search Block
5. Error Correction Block.
The below block diagram Fig 5.2.1 shows the decoder design. The 15 bits corrupted
codeword is the input to the decoder module. The task of the decoder is to locate and to
correct the errors in the corrupted codeword and retrieve the original message. The
detailed explanation for each block of decoder is given in this chapter.
5.2.1 Parallel to Serial Shifter:
15-bits corrupted codeword is feed to the Parallel to series shifter. During the 1st clock
pulse the hld signal is set to high, and all the message bits are given as input to the shifter.
From the second clock pulse shifter will start shifting the messages bits from parallel
input to series output. The hld signal remains high between the 1st and the 2nd clock pulse,
after that it set to low. At the end of 16th clock cycle all the 15- bits of corrupted
37
codeword is shifted serially at the output of the parallel to series shifter. The output of
this shifter is given as input to the next block of the decoder called Syndrome block.
Fig 5.2.1 Block diagram of Decoder
5.2.2 Syndrome Block
The output of the parallel to series shifter is given as input to the Syndrome block. As a
first step of syndrome block operation the input 1bit is converted to 4-bits. These 4-bits
are given as input to the six parallel syndromes blocks. These syndrome blocks generate
the syndrome S1_IN, S2_IN, S3_IN, S4_IN, S5_IN and S6_IN. The architecture of the
syndrome blocks is given as per the equation (3.7). In the first clock pulse these 4-bits are
38
added with α(i) and this result is stored in the register D. At the next clock pulse the result
stored in register D is multiplied by α(i) and the resultant bits of this multiplication is
added with new incoming expanded 4-bits. The register D is now updated with the new
resultant bits. This cyclic steps repeat in all six parallel syndromes for 15 clock cycles,
until the last bit of the corrupted codeword is enters to the syndrome block. The output
syndromes S(i) is generated at the end of 16th clock cycle. The hld signal for the
syndrome block is set to high at the 18th clock pulse to make sure that the output of the
syndrome block is not changed with every clock cycle. To indicate that syndromes are
generated and to trigger the start of the IBM block the syndrome _comp signal is set to
high. The output of the syndrome block is given as input to the IBM block.
The input, output and cntrl signal for encoder block are given below:
Input signals:

corrupted codeword (15 bits) – ‘data’

Clock – ‘clk’

Reset – ‘reset’

Signal to start the syndrome block – ‘active_syndrome’

Counter – ‘cntr’

Initialize – ‘init’

Ld signal for- Parallel to Serial shifter – ‘ld’

Hld signal for -serial to parallel shifter – ‘hld’
Cntrl Signals:
39

Cntrl signal to- start the 6 parallel blocks – ‘cntrl’.

Syndrome S(i) – ‘S1_IN, S2_IN, S3_IN, S4_IN, S5_IN and
Output signals:
S6_IN’

Syndrome Complete signal – ‘syndrome_comp’
The 15 bit received corrupted bits indicated as ‘data’ is given to the input of Parallel to
shift register and the output is the 4 bit, six syndromes indicated as ‘s1_in, s2_in, s3_in,
s4_in, s5_in, s6_in’.

15 bit received bits ‘data’ – ‘010010100010011’
The six syndromes are given as below.
S1_IN = ‘1111’
S2_IN = ‘1010’
S3_IN = ‘0111’
S4_IN = ‘1000’
S5_IN = ‘0110’
S6_IN = ‘0110’
5.2.3 Inversion-less Berlekamp Block
The input to the Inversion- less Berlekamp is come from the syndrome block. The
Inversion- less Berlekamp is consist of two major block. These blocks are called,

Discrepancy Computation (DC) Block
40

Error Locator Update (ELU) Block.
The algorithm for IBM is given as follows [4] [13]:
1. The first step is to initialize the variables of algorithm : λ0(0) = b0(0) = 1,
λi(0) = bi(0) = 0 where i = 1, 2,...t. k(0) = 0 and γ(0) = 1
2. The next step is to calculate discrepancy δ(r) = S(r). λ0(r) + S(r-1). λ1(r) +….+
S(r-t). λt(r)
Where s(i) is the generated syndromes………………………………….(eq 5.1)
3. Calculate the lambda λi(r+1) = γ(r). λi(r) - δ(r)bi-1(r), for i = 0, 1, …., t……(eq
5.2)
4. The first condition is, if discrepancy δ(r) ≠ 0 and k(r) ≥ 0 then calculate
bi(r+1) = λ1(r), for i = 0, 1, …., t
γ(r+1). = δ(r)
k(r+1) = - k(r) – 1
and if it doesn’t satisfy the above condition then calculate,
bi(r+1) = bi-1(r), for i = 0, 1, …., t
5. Go back to step no. 2 and run in a loop for the condition r = 0 to 2t-1.
6. The output of the IBM block is calculated as λi(2t), where i =0, 1, ….., t.
5.2.3.1 DC Block:
DC block is used to implement the 2nd step in the IBM algorithm. This block has six
latches to store the generated the six syndromes in the previous block. DC block has
architecture to compute the discrepancy as well as cntrl units for the entire IBM block. At
every clock he DC block calculates the discrepancy δ(r) and cntrl signal MC(r). DC block
41
passes these signals with y(r) to the next ELU block. The block diagram of the cntrl unit
and DC block is shown as below [11]:
Fig 5.2.3.1 Cntrl Unit [11]
42
Fig 5.2.3.2 DC Block [11]
5.2.3.2 ELU Block
The ELU block implements the step 3 and 4 of the IBM algorithm. The ELU block is
consists of six latches to store Λ(r, z) and B(r, z). The output of the ELU block is fed
back to the DC block. , δ(r) and MC(r) are the signals input to the ELU block from DC
block. The Block diagram of the ELU block is given as below [11]:
43
Fig 5.2.3.3 PE0 processor [11]
Fig 5.2.3.4 ELU Block Diagram [11]
44
The processor shown in the fig 5.2.3.3 is used to calculate the step 3 and 4 of IBM block
algorithm. The architecture shown in fig 5.2.3.4 is a ELU block which is used to calculate
the signals discrepancy δ(r), γ(r) and MC(r) which are sent over to all PEO processors.
The Output Λ(i) is computed and the hld signal for IBM block is set to high, to ensure
that the output value is not changed with every clock pulse. The betl_comp signal is set to
high to show that the lambda is generated. In addition, the ibm_comp signal indicates the
start signal for the next Chain block search.
The Input, Output and cntrl signal for the IBM block is given as below:
Input signals:

Generated Syndrome S(i) – ‘S1_IN, S2_IN, S3_IN, S4_IN,
S5_IN and S6_IN’

Clock – ‘clk’

Reset – ‘reset’

Signal to indicate the start of IBM block – ‘active_ibm’

Counter – ‘cntr’

Initialize – ‘init’

Ld signal for IBM block – ‘ld’

Hld signal for IBM block – ‘hld’

4 bit output- lambda Λ(i) – ‘Λ0, Λ1, Λ2 and Λ3 ’
Cntrl Signals:
Output signals:
45

IBM block completion signal – ‘ibm_comp’
The syndromes calculated are given as below and syndromes are 4- bits that are given as
input to the IBM block:
S1_IN = ‘1111’
S2_IN = ‘1010’
S3_IN = ‘0111’
S4_IN = ‘1000’
S5_IN = ‘0110’
S6_IN = ‘0110’
The output of the IBM block is 4- bits lambda, which are given as below:
Lambda0 = ‘0001’
Lambda1 = ‘1111’
Lambda2 = ‘0010’
Lambda3 = ‘0110’
5.2.4 Chain Search Block
The input to the Chain search block is the output of the IBM block. The chain search
block is has four parallel blocks. The input is given to these parallel blocks and the output
of these blocks are added together to calculate the output of this block. At the 1st clock
pulse the input is first multiplied α(i) with and this result is stored in the register D. Next
the value in register D is multiplied with α(i) and the resultant bits from all the 4 parallel
block are added together. Now the register D is updated. This is a cyclic step which
repeats in all the 4 parallel block for 15 clock cycles and the results are stored using 15-
46
bits series to parallel register. After 19th clock pulse, the series to parallel shifter has the
root of equations. Also at the 19th clock pulse the hld signal is assert to high to make sure
that output of the chain search block is not changed, as well as the chain_comp signal is
set to high to indicate that roots are calculated. The chain_comp signal is also indicate the
trigger of the next block called the Error correction block. The output of the chain search
block is given as input to the Error correction block.
The input, output and cntrl signal to the chain search block is as given below:
Input signals:

4 bit lambda Λ(i) input – ‘Λ0, Λ1, Λ2 and Λ3 ’

Clock – ‘clk’

Reset – ‘reset’

Signal to start the Chain search block – ‘active_chains’

Counter – ‘cntr’

Initialize – ‘init’

Ld signal for cs block – ‘ld’

Hld signal for cs block – ‘hld’

Cntrl – ‘cntrl’.

15 bit root- output of CS block – ‘out_root’

CS Completion block – ‘chain_comp’
Cntrl Signals:
Output signals:
47
The input to the chain search block is the output of IBM block. Lambda is the input to the
chain search block which is given as:
Lambda0 = ‘0001’
Lambda1 = ‘1111’
Lambda2 = ‘0010’
Lambda3 = ‘0110’
The output of the chain search block is given as follows:
Roots of equation ‘out_root’ = ‘010000000100100’
5.2.5 Error Correction Block:
The output of the chain search block is given as input to the Error correction block and
the received corrupted 15-bit codeword is input to this block. These two 15 bit input
codeword are added together to retrieve a correct codeword. The block diagram of this
block is shown in the figure 4.2.2. In addition, the simulation result of this block is shown
in fig4.2.5.1. The input and output of the error correction block is given as below:
Input signals:
Output signals:

15 bit received corrupted codeword – ‘data’

15 bit root- output from CS block – ‘out_root’

Clock – ‘clk’

Reset – ‘reset’

Signal to start the Error correction block – ‘active_error’
48

15 bit codeword– ‘codword’
The two inputs to this block is follows:
Original received bits ‘data’ = ‘010010100010011’
Roots of equation ‘out_root’ = ‘010000000100100’
The output is calculated by adding the two inputs.
‘Codeword’ = ‘000010100110111’
‘Errors’ = ’11’
The complete Data Flow of input and output of the encoder and the decoder design is as
follows:
Encoder Module:
Input signals:

5 bits input Message - ‘00001’

Active_Enc – ‘1’

Reset – ‘0’

15 bit Codeword output of encoder – ‘000010100110111’
Output signal:
Decoder Module:
Input signals:

15 bit Corrupted Received codeword - ‘010010100010011’

Active_Decoder – ‘1’

Reset – ‘0’
49
Output signal:

15 bit original Codeword – ‘000010100110111’

Numbers of errors corrected – ‘11’
Intermediate stages Outputs:
Syndrome Block output:
S1_IN = ‘1111’
S2_IN = ‘1010’
S3_IN = ‘0111’
S4_IN = ‘1000’
S5_IN = ‘0110’
S6_IN = ‘0110’
Key Equation Solver Block output:
Λ(0) = ‘0001’
Λ(1) = ‘1111’
Λ(2) = ‘0010’
Λ(3) = ‘0110’
Chain Search Block output:
Roots of equation e(x) = ‘010000000100100’
Error Correction Block output:
Codeword = r(x) ^ e(x) = ‘000010100110111’
50
So, the codeword is generated by adding the message bits with parity bits and transmitted
over to the decoder. The data get corrupted during the transmission. The decoder will
decode the corrupted data and retrieve the original codeword.
51
Chapter 6
SIMULATION AND SYNTHESIS RESULT OF DECODER
6.1 Simulation Result of Decoder
Fig 6.1.1 Decoder simulation waveform
52
6.1.1 Syndrome Block
Fig 6.1.2 Syndrome Simulation Waveform
53
6.1.2 IBM Block
Fig 6.1.3 IBM Block simulation waveform
54
6.1.3 Chain Search Block
Fig 6.1.4 Chain search block waveform
55
6.1.4 Error correction block
Fig 6.1.5 Error correction block waveform
56
6.2 Synthesis Result of Decoder Module
6.2.1 Syndrome Block Synthesis
The below figure 6.2.1 and 6.2.2 shows the top level module and logic block of syndrome
block.
Fig 6.2.1 Syndrome block – Top module
57
Fig 6.2.2 Syndrome Block – Logic block
58
6.2.2 IBM Block Synthesis result
The below figure 6.2.3 and 6.2.4 shows the top level module and logic block of iBM
block.
Fig 6.2.3 IBM block – Top Module
59
Fig 6.2.4 IBM Block – Logic Design
60
6.2.3 Chain search block
The below figure 6.2.5 and 6.2.6 shows the top level module and logic block of Chain
search block.
Fig 6.2.5 Chain search block – Top module
61
Fig 6.2.6 Chain search block- Logic block
62
6.2.4 Error Correction Block
The below figure 6.2.7 and 6.2.8 shows the top level module and logic block of Error
Correction block.
Fig 6.2.7 Error correction block – Top Module
63
Fig 6.2.8 Error correction block – Logic Block
64
Chapter 7
PERFORMANCE CHECK OF ENCODER_LFSR DESIGN
7.1 Encoder_LFSR Performance
This chapter covers the performance analysis of encoder_LFSR design with respect to the
design summary generated by the Xilinx ISE 10.1 tool. Also, the encoder_LFSR design is
synthesized using Xilinx webpack. The performance of the encoder_LFSR design is
based on various parameters such as, Design summary, IOB properties, Timing
constraints, Pin out and clock report, Synthesis report, Translation report, Map report,
Place and route report and Static timing analysis report.
Fig 7.1.1 Design Summary of Encoder_LFSR Design – I
65
Fig 7.1.2 Design Summary of Encoder_LFSR Design – II
Figure 7.1.1 and 7.1.2 shows the usage of the flip flops, logic blocks and IOBs for the
encoder_LFSR design. From the summary table it can be seen that the there are totally
26,624 flip flops are available in the FPGA board, out of which only 39 flip flops are
being used. So, the utilization percentage of the flip flops is only 1%. Also, the available
LUT are 26,624 out of which only 32 are being used, hence the utilization percentage of
the LUT is also almost equal to 1%. There are 221 IOBs are available in FPGA out of
which only 23 IOBs are used for encoder_LFSR design. So, the utilization percentage is
10%. Thus, it could be seen that the percentage of the various components used for the
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encoder_LFSR design are very less as compared to the available quantity. So, it could be
concluded that the encoder_LFSR design of this project is optimized and also has good
performance.
7.2 Decoder Performance
Fig 7.2.1 Design Summary of Decoder – I
67
Fig 7.2.2 Design Summary of Decoder – II
Figure 7.2.1 and 7.2.2 shows the usage of the flip flops, logic blocks and IOBs for the
BCH_Decoder design. From the summary table it can be seen that the there are totally
1,320 flip flops are available in the FPGA board, out of which only 213 flip flops are
being used. So, the utilization percentage of the flip flops is only 11%. Also, the available
LUT are 1,320 out of which only 560 are being used, hence the utilization percentage of
the LUT is also almost equal to 23%. There are 66 IOBs are available in FPGA out of
which only 35 IOBs are used for decoder design. So, the utilization percentage is 53%.
Thus, it could be seen that the percentage of the various components used for the
68
BCH_Decoder design are very less as compared to the available quantity. So, it could be
concluded that the BCH_Decoder design of this project is optimized and also has good
performance.
7.2.1 Features of XC3S1_IN500 FPGA Board:
Fig 7.2.3 Pin layout of XC3S1_IN500
The FPGA is one of the Spartan 3e family devices. XC3S1_IN500 FPGA board is the
target FPGA board for this project. Low cost and the high performance logic solution are
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the main reasons of choosing this board for project. With respect to the availability of
logic blocks, the XC3S1_IN500 has 26,624 flip flops and 2160 equivalent logic cells.
The frequency of operation of the Spartan 3e FPGA family ranges from 18 MHz to 280
MHz.
70
Chapter 8
CONCLUSION
This project covers the detailed explanation about the necessity of Error correcting code
along with the comparison of various error correcting codes and high speed (15, 5) BCH
code Encode and Decoder design. The previous chapters discuss the design technique of
encoder and decoder, and the behavior of the designs are described using Verilog. The
simulation of the code is done in Xilinx Modelsim. Also, the encoder and decoder design
is synthesized in Xilinx ISC 10.1 wabepack to generate the gate level netlist. The design
steps, input signals and output signals along with the simulation results of design and
synthesis result are discussed in detail in pervious chapters.
71
APPENDICES
72
APPENDIX A
1 Encoder_LFSR Design
Top Module – Encoder_LFSR
Here BCH_ Encoder_LFSR is called the top module. There are three sub modules in it,
which are described as follows. The sub modules are instantiated in the top module.
[1] 5 bit Parallel to Serial Shift Register - “para_seri_5’
[2] Encoder_LFSR module – “encoder_LFSR”
[3] 15 bit Serial to Parallel Shift Register – “seri_paral_15”
Here, top module BCH_Encoder_LFSR generates the cntrl signals to cntrl the flow of the
data. The input and output signals of the Encoder_LFSR module are as shown below:
Inputs- message, clock, reset, and active_en.
Output – Codeword.
73
4.1.1 BCH Encoder_LFSR verilog HDL Code:
module BCH_Encoder_LFSR (out, msgs, clk, reset, active_encoder_LFSR);
output[0:14] out;
input[4:0] msgs;
input clk, reset,active_encoder_LFSR;
wire en_out,ps_out;
reg [4:0] cntrl;
reg init, hld, ld, switch;
initial cntrl = 5'b0;
always@ (posedge clk)
begin
if(active_encoder_LFSR)
cntrl <= cntrl + 1;
else
cntrl<= 5'b0;
end
always@ (posedge clk)
begin
if(reset)
begin
init = 0;
ld = 0;
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hld = 0;
switch = 0;
end
else if(cntrl==0)
begin
init = 1;
ld = 1;
hld = 0;
switch =0;
end
else if(cntrl == 1)
begin
init = 0;
ld = 1;
hld = 0;
end
else if(cntrl == 2)
begin
init = 0;
ld = 0;
hld = 0;
switch = 1;
75
end
else if(cntrl == 7)
begin
init = 0;
ld = 0;
hld = 0;
switch = 0;
end
else if(cntrl == 17)
begin
init = 0;
ld = 0;
hld = 1;
end
end
para_seri_5 ps(pss_out, msgs, clk, reset, ld);
encoder_LFSR b(enc_out, pss_out, clk, reset, switch, init);
seri_paral_15 sp(out, enc_out, clk, reset, hld);
endmodule
// Parallel to Series Shift Register
module para_seri_5(pss_out, pss_in, clk, reset, ld);
input[4:0] pss_in;
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input clk, reset, ld;
output pss_out;
reg [4:0] temp_in;
assign pss_out = temp_in[4];
always @(posedge clk)
begin
if (reset)
begin
temp_in <= 5'b0;
end
else
begin
if (ld)
temp_in <= ps_in;
else
begin
temp_in[4] <= temp_in[3];
temp_in[3] <= temp_in[2];
temp_in[2] <= temp_in[1];
temp_in[1] <= temp_in[0];
temp_in[0] <= 1'b0;
end
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end
end
endmodule
// Encoder_LFSR module- Linear Feedback shift register
module encoder_LFSR(bout,bin, clk, reset, switch, init);
output bout;
input bin, clk, reset, switch, init;
reg d0, d1, d2, d3, d4, d5, d6, d7, d8, d9;
reg bf, bout;
always@(posedge clk)
begin
if(reset)
begin
d0<= 1'b0;
d1<= 1'b0;
d2<= 1'b0;
d3<= 1'b0;
d4<= 1'b0;
d5<= 1'b0;
d6<= 1'b0;
d7<= 1'b0;
d8<= 1'b0;
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d9<= 1'b0;
end
else if(init)
begin
d0<= 1'b0;
d1<= 1'b0;
d2<= 1'b0;
d3<= 1'b0;
d4<= 1'b0;
d5<= 1'b0;
d6<= 1'b0;
d7<= 1'b0;
d8<= 1'b0;
d9<= 1'b0;
end
else
begin
d0<= bf;
d1<= bf^d0;
d2<= bf^d1;
d3<= d2;
d4<= bf^d3;
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d5<= bf^d4;
d6<= d5;
d7<= d6;
d8<= bf^d7;
d9<= d8;
end
end
always@(switch,bin,d9)
begin
if(switch)
begin
bf<= bin^d9;
bout<=bin;
end
else
begin
bf<=1'b0;
bout<= d9;
end
end
endmodule
// Series to parallel Shift register
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module seri_paral_15(sps_out, sps_in, clk, reset, hld);
input sps_in, clk, reset, hld;
output [0:14] sps_out;
reg[14:0] r;
assign sps_out = r;
always @(posedge clk)
begin
if (reset)
r<= 15'b000_0000_0000_0000;
else if(hld)
r<= r;
else
r<= {sps_in,r[14:1]};
end
endmodule
4.1.2 Test bench
******************************
// top module test bench//
*****************************
module Encoder_LFSR_Fixture;
// inputs
reg [4:0] msgs;
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reg clk;
reg reset;
reg active_encoder_LFSR;
// outputs
wire [0:14] out;
// instantiate the DUT
BCH_Encoder_LFSR av ( .out(out), . msgs(msgs), .clk(clk), .reset(reset),
.active_encoder_LFSR(active_encoder_LFSR));
initial
begin
clk = 1'b0;
forever # 5 clk =~ clk;
end
initial
begin
# 10 reset = 1'b0;
#10 active_encoder_LFSR= 1'b1;
#10 msgs= 5'b00001;
#1000 $finish ;
end
initial
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begin
$monitor ( $time, "OUT= %b MSGS=%b ACTIVE_ENCODER_LFSR=%b ", out, msgs,
active_encoder_LFSR);
end
endmodule
**********************************
// test bench of parallel to series shifter//
**********************************
module para_seri_5Fixture;
// inputs
reg [4:0] pss_in;
reg clk;
reg reset;
reg ld;
// outputs
wire pss_out;
// instantiate the DUT
para_seri_5 av ( .pss_out(pss_out), . pss_in(pss_in), .clk(clk), .reset(reset), .ld(ld));
initial
begin
clk = 1'b0;
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forever # 5 clk =~ clk;
end
initial
begin
# 10 reset = 1'b0;
#10 pss_in = 5'b00001;
#1000 $finish ;
end
initial
begin
$monitor ( $time, "PSS_OUT= %b PSS_IN=%b LD=%b ", pss_out, pss_in, ld);
end
endmodule
*********************************
// test bench of linear feedback shifter//
**********************************
module Encder_Fixture;
// inputs
reg bin;
reg clk;
reg reset;
reg switch;
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reg init;
// outputs
wire bout;
// instantiate the DUT
encoder_LFSR av ( .bout(bout), .bin(bin), .clk(clk), .reset(reset), .switch(switch),
.init(init));
initial
begin
clk = 1'b0;
forever # 5 clk =~ clk;
end
initial
begin
# 10 reset = 1'b0;
#10 bin = 5'b00001;
#1000 $finish ;
end
initial
begin
$monitor ( $time, "BOUT= %b BIN=%b SWITCH=%b INIT=%b ", bout, bin, switch,
init);
end
85
endmodule
*****************************
//test bench of series to parallel//
******************************
module seri_paral_15 Fixture;
// inputs
reg sps_in;
reg clk;
reg reset;
reg hld;
// outputs
wire [0:14] sps_out;
// instantiate the DUT
seri_paral_15 av ( .sps_out(sps_out), .sps_in(sps_in), .clk(clk), .reset(reset), .hld(hld));
initial
begin
clk = 1'b0;
forever # 5 clk =~ clk;
end
initial
begin
# 10 reset = 1'b0;
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#10 sps_in= 5'b00001;
#1000 $finish ;
end
initial
begin
$monitor ( $time, "SPS_OUT= %b SPS_IN=%b HLD=%b ", sps_out,sps_in, hld);
end
endmodule
87
APPENDIX B
Top module of Decoder design
Top module- Decoder
The Top module of decoder design is called “BCH_DECODER”. There are five sub
modules in the decoder. These modules are as follows;
[1] Syndrome block – syndrome_block
[2] iBM block – ibm_block
[3] Chain search block – chain_block
[4]Error correction block- errorcorr_block
7.2 Verilog code for Decoder
module BCH_DECODER(codword, error, data, clk, reset, active_decoder);
// output signals
output[14:0] dword;
output[1:0] error;
// Input signals
input [14:0] data;
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input clk, reset, active_decoder;
// Wire connection
wire [3:0] s1_in_in, s2_in_in, s3_in_in, s4_in_in, s5_in_in, s6_in_in, lambda0,
lambda1, lambda2, lambda3;
wire [0:14] out_root;
wire syndrome_comp, ibm_comp, chain_comp;
// Instantiation of modules
syndrome_block sb(s1_in_in, s2_in_in, s3_in_in, s4_in_in, s5_in_in, s6_in_in,
syndrome_comp, data, clk, reset, active_decoder);
ibm_block bb(lambda0, lambda1, lambda2, lambda3,lambda_degree,
ibm_comp, s1_in_in, s2_in_in, s3_in_in, s4_in_in, s5_in_in, s6_in_in, clk,
reset, syndrome_comp);
chain_block cb(out_root, chain_comp, lambda0, lambda1, lambda2, lambda3,
clk, reset, ibm_comp);
errorcorr_block eb(codword, out_root, data, clk, reset, chain_comp);
endmodule
//Syndrome Block//
module syndrome_block(s1_in_in, s2_in_in, s3_in_in, s4_in_in, s5_in_in, s6_in_in,
syndrome_comp, data, clk, reset, active_syndrome);
output [3:0] s1_in_in, s2_in_in, s3_in_in, s4_in_in, s5_in_in, s6_in_in;
output syndrome_comp;
89
input [14:0] data;
input clk, reset, active_syndrome;
reg [3:0] s1_in_in, s2_in_in, s3_in_in, s4_in_in, s5_in_in, s6_in_in;
wire [3:0] s1_in_in_out, s2_in_in_out, s3_in_in_out, s4_in_in_out, s5_in_in_out,
s6_in_in_out;
wire ps_out;
reg [3:0] syn_in;
reg ld, cntr, hld, init, syndrome_comp;
reg [4:0] cntr;
initial cntr = 5'b0;
always@ (posedge clk)
begin
if(active_syndrome)
if (cntr >= 20)
cntr <= cntr;
else
cntr <= cntr + 1;
else
cntr<= 5'b0;
end
always@ (posedge clk)
begin
90
if(reset)
begin
init = 0;
ld = 0;
hld = 0;
cntr = 0;
syndrome_comp = 0;
end
else if(cntr==0)
begin
init = 1;
ld = 1;
hld = 0;
cntr = 0;
syndrome_comp = 0;
end
else if(cntr == 1)
begin
init = 0;
ld = 1;
hld = 0;
cntr = 0;
91
end
else if(cntr == 2)
begin
init = 0;
ld = 0;
hld = 0;
cntr = 1;
end
else if(cntr == 18)
begin
init = 0;
ld = 0;
hld = 1;
cntr = 0;
syndrome_comp = 1;
end
end
//Parallel to Series Block
ps_15 ps(ps_out, data, clk, reset, ld);
always@(ps_out)
begin
syn_in[0] = ps_out;
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syn_in[1] = 1'b0;
syn_in[2] = 1'b0;
syn_in[3] = 1'b0;
end
// Six Parallel syndrome Blocks
syndromemult_1 mult1 (s1_in_in_out, s1_in_in);
syndromemult_2 mult2 (s2_in_in_out, s2_in_in);
syndromemult_3 mult3 (s3_in_in_out, s3_in_in);
syndromemult_4 mult4 (s4_in_in_out, s4_in_in);
syndromemult_5 mult5 (s5_in_in_out, s5_in_in);
syndromemult_6 mult6 (s6_in_in_out, s6_in_in);
always @(posedge clk)
begin
if(reset)
begin
s1_in_in = 0;
s2_in_in = 0;
s3_in_in = 0;
s4_in_in = 0;
s5_in_in = 0;
s6_in_in = 0;
end
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else if(init)
begin
s1_in_in = 0;
s2_in_in = 0;
s3_in_in = 0;
s4_in_in = 0;
s5_in_in = 0;
s6_in_in = 0;
end
else if (cntr)
begin
s1_in_in = s1_in_in_out ^ syn_in;
s2_in_in = s2_in_in_out ^ syn_in;
s3_in_in = s3_in_in_out ^ syn_in;
s4_in_in = s4_in_in_out ^ syn_in;
s5_in_in = s5_in_in_out ^ syn_in;
s6_in_in = s6_in_in_out ^ syn_in;
end
else if(hld)
begin
s1_in_in = s1_in_in;
s2_in_in = s2_in_in;
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s3_in_in = s3_in_in;
s4_in_in = s4_in_in;
s5_in_in = s5_in_in;
s6_in_in = s6_in_in;
end
end
endmodule
module syndromemult_1 (s_out, s_in);
output [3:0] s_out;
input [3:0] s_in;
reg [3:0] s_out;
always@ (s_in)
begin
s_out[0] = s_in[3];
s_out[1] = s_in[0] ^ s_in[3];
s_out[2] = s_in[1];
s_out[3] = s_in[2];
end
endmodule
module syndromemult_2 (s_out, s_in);
output [3:0] s_out;
input [3:0] s_in;
95
reg [3:0] s_out;
always@ (s_in)
begin
s_out[0] = s_in[2];
s_out[1] = s_in[2] ^ s_in[3];
s_out[2] = s_in[0] ^ s_in[3];
s_out[3] = s_in[1];
end
endmodule
module syndromemult_3 (s_out, s_in);
output [3:0] s_out;
input [3:0] s_in;
reg [3:0] s_out;
always@ (s_in)
begin
s_out[0] = s_in[1];
s_out[1] = s_in[1] ^ s_in[2];
s_out[2] = s_in[2] ^ s_in[3];
s_out[3] = s_in[0] ^ s_in[3];
end
endmodule
module syndromemult_4 (s_out, s_in);
96
output [3:0] s_out;
input [3:0] s_in;
reg [3:0] s_out;
always@ (s_in)
begin
s_out[0] = s_in[0] ^ s_in[3];
s_out[1] = s_in[0] ^ s_in[1] ^ s_in[3];
s_out[2] = s_in[1] ^ s_in[2];
s_out[3] = s_in[2] ^ s_in[3];
end
endmodule
module syndromemult_5 (s_out, s_in);
output [3:0] s_out;
input [3:0] s_in;
reg [3:0] s_out;
always@ (s_in)
begin
s_out[0] = s_in[2] ^ s_in[3];
s_out[1] = s_in[0] ^ s_in[2];
s_out[2] = s_in[0] ^ s_in[1] ^ s_in[3];
s_out[3] = s_in[1] ^ s_in[2];
end
97
endmodule
module syndromemult_6 (s_out, s_in);
output [3:0] s_out;
input [3:0] s_in;
reg [3:0] s_out;
always@ (s_in)
begin
s_out[0] = s_in[1] ^ s_in[2];
s_out[1] = s_in[1] ^ s_in[3];
s_out[2] = s_in[0] ^ s_in[2];
s_out[3] = s_in[0] ^ s_in[1] ^ s_in[3];
end
endmodule
// Paralle to Series Block
module ps_15(ps_out, ps_in, clk, reset, ld);
input[14:0] ps_in;
input clk, reset, ld;
output ps_out;
reg [14:0] temp_in;
assign ps_out = temp_in[14];
always @(posedge clk)
begin
98
if (reset)
begin
temp_in <= 14'b0;
end
else
begin
if (ld)
temp_in <= ps_in;
else
begin
temp_in[14] <= temp_in[13];
temp_in[13] <= temp_in[12];
temp_in[12] <= temp_in[11];
temp_in[11] <= temp_in[10];
temp_in[10] <= temp_in[9];
temp_in[9] <= temp_in[8];
temp_in[8] <= temp_in[7];
temp_in[7] <= temp_in[6];
temp_in[6] <= temp_in[5];
temp_in[5] <= temp_in[4];
temp_in[4] <= temp_in[3];
temp_in[3] <= temp_in[2];
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temp_in[2] <= temp_in[1];
temp_in[1] <= temp_in[0];
temp_in[0] <= 1'b0;
end
end
end
endmodule
//BERLEKAMP ALGORITHM - KEY EQUATION SOLVER//
module ibm_block(lambda0, lambda1, lambda2, lambda3,lambda_degree,
ibm_comp, s1_in_in, s2_in_in, s3_in_in, s4_in_in, s5_in_in, s6_in_in, clk,
reset, active_ibm);
input active_ibm, clk, reset;
input [3:0] s1_in_in, s2_in_in, s3_in_in, s4_in_in, s5_in_in, s6_in_in;
output [3:0] lambda0, lambda1, lambda2, lambda3;
output [1:0] lambda_degree;
output ibm_comp;
wire ld,init,hld,iter_cntr;
wire [3:0] delta0, delta1, delta2, delta3, delta4, delta5, delta6,
delta7, delta8, delta9;
wire [3:0] gamma, delta;
wire deg1, deg2, deg3;
100
PRIORITY_ENCDOER PRIORITY_ENCDOER0(delta0, delta1, s1_in_in, gamma,
delta, clk, ld, init, hld, iter_cntr);
PRIORITY_ENCDOER PRIORITY_ENCDOER1(delta1, delta2, s2_in_in, gamma,
delta, clk, ld, init, hld, iter_cntr);
PRIORITY_ENCDOER PRIORITY_ENCDOER2(delta2, delta3, s3_in_in, gamma,
delta, clk, ld, init, hld, iter_cntr);
PRIORITY_ENCDOER PRIORITY_ENCDOER3(delta3, delta4, s4_in_in, gamma,
delta, clk, ld, init, hld, iter_cntr);
PRIORITY_ENCDOER PRIORITY_ENCDOER4(delta4, delta5, s5_in_in, gamma,
delta, clk, ld, init, hld, iter_cntr);
PRIORITY_ENCDOER PRIORITY_ENCDOER5(delta5, delta6, s6_in_in, gamma,
delta, clk, ld, init, hld, iter_cntr);
PRIORITY_ENCDOER_6 PRIORITY_ENCDOER6(delta6, delta7,gamma, delta,
clk, ld, init, hld, iter_cntr);
PRIORITY_ENCDOER_6 PRIORITY_ENCDOER7(delta7, delta8,gamma, delta, clk,
ld, init, hld, iter_cntr);
PRIORITY_ENCDOER_6 PRIORITY_ENCDOER8(delta8, delta9,gamma, delta, clk,
ld, init, hld, iter_cntr);
PRIORITY_ENCDOER_9 PRIORITY_ENCDOER9(delta9, delta, clk, ld, init,hld,
iter_cntr);
cntr mcntr(delta0, gamma, active_ibm, reset, delta, iter_cntr,ld, init, hld, clk);
assign lambda0 = delta3;
101
assign lambda1 = delta4;
assign lambda2 = delta5;
assign lambda3 = delta6;
//to count the degree of error location polynomail(lambda)//
assign deg1 = (lambda1[0] | lambda1[1]) | (lambda1[2] | lambda1[3]);
assign deg2 = (lambda2[0] | lambda2[1]) | (lambda2[2] | lambda2[3]);
assign deg3 = (lambda3[0] | lambda3[1]) | (lambda3[2] | lambda3[3]);
assign ibm_comp = hld;
priority_en Priority_Encdoerncoder(deg1, deg2, deg3, lambda_degree);
endmodule
//***************************************************************//
module cntr(delta0_in, gamma, active_ibm, reset, delta_out, iter_cntr, ld,
init, hld, clk);
input [3:0] delta0_in;
input clk, active_ibm, reset;
output [3:0] delta_out, gamma;
output iter_cntr, ld, hld, init;
reg [3:0] cntr;
reg ld, hld, init;
wire [3:0] kr, inv_kr, outadd;
wire [3:0] outmux1, outmux2;
wire zerodet, negdet;
102
wire [3:0] incr;
wire carrybit;
initial cntr = 4'b0;
always@ (posedge clk)
begin
if(active_ibm)
if (cntr >= 10)
cntr <= cntr;
else
cntr <= cntr + 1;
else
cntr<= 4'b0;
end
always@ (posedge clk)
begin
if(reset)
begin
init = 0;
ld = 0;
hld = 0;
end
else if(cntr==0)
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begin
init = 1;
ld = 0;
hld = 0;
end
else if(cntr == 1)
begin
init = 0;
ld = 1;
hld = 0;
end
else if(cntr == 7)
begin
init = 0;
ld = 0;
hld = 1;
end
end
assign incr = 1;
assign carrybit = 0;
assign zerodet = (delta0_in[0] | delta0_in[1])|(delta0_in[2]|delta0_in[3]);
assign negdet = ~kr[3];
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assign iter_cntr = zerodet & negdet;
assign inv_kr = ~kr;
assign delta_out = delta0_in;
mux2_to_1 mux1(outmux1,gamma, delta0_in,iter_cntr);
mux2_to_1 mux2(outmux2,outadd, inv_kr,iter_cntr);
fulladd add(kr, incr, carrybit, outadd);
regama reggama(gamma,outmux1, ld, init, clk);
regkr regkr(kr,outmux2,ld, init, clk);
endmodule
//*****************************************//
//Full Add 4 bit
//
//*****************************************//
module fulladd(in1, in2, carryin, out);
input [3:0] in1, in2;
input carryin;
output [3:0] out;
wire carry0, carry1, carry2, carry3;
assign carry0 = ((in1[0] ^ in2[0])&carryin) | (in1[0]&in2[0]);
assign carry1 = ((in1[1] ^ in2[1])&carry0) | (in1[1]&in2[1]);
assign carry2 = ((in1[2] ^ in2[2])&carry1) | (in1[2]&in2[2]);
assign out[0] = in1[0] ^ in2[0] ^ carryin;
assign out[1] = in1[1] ^ in2[1] ^ carry0;
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assign out[2] = in1[2] ^ in2[2] ^ carry1;
assign out[3] = in1[3] ^ in2[3] ^ carry2;
endmodule
//*********************************************//
// register for storing gamma with synchronous //
// ld and initialize
//
//*********************************************//
module regama(dataout,datain, ld, initialize, clk);
input [3:0] datain;
input ld, initialize;
input clk;
output [3:0] dataout;
reg [3:0] out;
always @(posedge clk)
begin
if(initialize)
out <= 4'b0001;
else if(ld)
out <= datain;
else
out <= 4'b0;
end
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assign dataout = out;
endmodule
//********************************************//
// register for storing k(r) with synchronous //
// ld and initialize
//
//********************************************//
module regkr(dataout,datain,ld, initialize, clk);
input [3:0] datain;
input ld, initialize;
input clk;
output [3:0] dataout;
reg [3:0] out;
always @(posedge clk)
begin
if(initialize)
out <= 4'b0;
else if(ld)
out <= datain;
else
out <= 4'b0;
end
assign dataout = out;
107
endmodule
//*************************//
// Multiplexer 2 to 1 4bit //
//*************************//
module mux2_to_1(out, in1, in2, sel);
input [3:0] in1, in2;
input sel;
output [3:0] out;
reg [3:0] out;
always@(sel or in1 or in2)
begin
case(sel)
0 : out = in1;
1 : out = in2;
default: out = in1;
endcase
end
endmodule
//******************//
// Priority Encoder //
//******************//
module priority_en(in_1,in_2,in_3,out);
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input in_1, in_2, in_3;
output [1:0] out;
reg [1:0] out;
always@(in_3,in_2,in_1)
begin
if (in_3==1)
out = 3;
else if(in_2==1) out = 2;
else if(in_1==1) out = 1;
else out = 2'b0;
end
endmodule
//****************************************************************//
module PRIORITY_ENCDOER(delta_cflex_out, delta_cflex_in, syndval, gamma, delta,
clk, ld, init, hld, iter_cntr);
input [3:0] delta_cflex_in, syndval;
input [3:0] gamma;
input [3:0] delta;
input clk, ld, hld, iter_cntr, init;
output [3:0] delta_cflex_out;
wire [3:0] outmult1, outmult2, outreg1, outreg2, outmux, outadd;
lcpmult multiplier1(outmult1, delta_cflex_in, gamma);
lcpmult multiplier2(outmult2,delta, outreg1);
109
register_Priority_Encdoer reg1(outreg2, outadd, syndval, ld, init, hld, clk);
register_Priority_Encdoer reg2(outreg1, outmux, syndval, ld, init, hld, clk);
mux2_to_1 multiplexer(outmux,outreg1, delta_cflex_in, iter_cntr);
assign outadd[3] = outmult2[3] ^ outmult1[3];
assign outadd[2] = outmult2[2] ^ outmult1[2];
assign outadd[1] = outmult2[1] ^ outmult1[1];
assign outadd[0] = outmult2[0] ^ outmult1[0];
assign delta_cflex_out = outreg2;
endmodule
//***********************************************************//
module PRIORITY_ENCDOER_6(delta_cflex_out, delta_cflex_in, gamma, delta, clk, ld,
init, hld, iter_cntr);
input [3:0] delta_cflex_in;
input [3:0] gamma;
input [3:0] delta;
input clk, ld, hld, iter_cntr, init;
output [3:0] delta_cflex_out;
wire [3:0] outmult1, outmult2, outreg1, outreg2, outmux, outadd;
wire [3:0] initdata;
assign initdata = 4'b0;
lcpmult multiplier1(outmult1, delta_cflex_in, gamma);
110
lcpmult multiplier2(outmult2, delta, outreg1);
register_Priority_Encdoer reg1(outreg2, outadd, initdata, ld, init, hld, clk);
register_Priority_Encdoer reg2(outreg1, outmux, initdata,ld, init, hld, clk);
mux2_to_1 multiplexer(outmux, outreg1, delta_cflex_in, iter_cntr);
assign outadd[3] = outmult2[3] ^ outmult1[3];
assign outadd[2] = outmult2[2] ^ outmult1[2];
assign outadd[1] = outmult2[1] ^ outmult1[1];
assign outadd[0] = outmult2[0] ^ outmult1[0];
assign delta_cflex_out = outreg2;
endmodule
//******************************************************//
module PRIORITY_ENCDOER_9(delta_cflex_out, delta, clk, ld, init, hld, iter_cntr);
input [3:0] delta;
input clk, ld, init, hld, iter_cntr;
output [3:0] delta_cflex_out;
wire [3:0] outmult, outreg1, outreg2, outmux;
wire [3:0] initdata;
wire [3:0] delta_cflex_10;
assign initdata = 4'b0001;
assign delta_cflex_10 = 4'b0;
lcpmult multiplier(outmult, delta, outreg1);
register_Priority_Encdoer reg1(outreg2, outmult, initdata, ld, init, hld, clk);
111
register_Priority_Encdoer reg2(outreg1, outmux, initdata, ld, init, hld, clk);
mux2_to_1 multiplexer(outmux, outreg1, delta_cflex_10, iter_cntr);
assign delta_cflex_out = outreg2;
endmodule
//*****************************************************//
//PRIORITY_ENCDOER Register with synchronous ld, intialize, hld //
module register_Priority_Encdoer(dataout, datain, initdata, ld, initialize, hld, clk);
input [3:0] datain, initdata;
input ld, hld, initialize;
input clk;
output [3:0] dataout;
reg [3:0] out;
always @(posedge clk)
begin
if(initialize)
out <= initdata;
else if(ld)
out <= datain;
else if(hld)
out <= out;
else
out <= 4'b0;
112
end
assign dataout = out;
endmodule
//*********************************************//
// GF(2^4) parallel multiplier
//
module lcpmult(out, in1, in2);
output [3:0] out;
input [3:0] in1, in2;
assign out[0] = (in1[0] & in2[0]) ^ (in1[3] & in2[1]) ^ (in1[2] & in2[2]) ^ (in1[1] &
in2[3]);
assign out[1] = ((in1[1] & in2[0]) ^ (in1[0] & in2[1]) ^ (in1[3] & in2[1]) ^ (in1[2] &
in2[2])) ^ ((in1[1] & in2[3])^ (in1[3] & in2[2]) ^ (in1[2] & in2[3]));
assign out[2] = (in1[2] & in2[0]) ^ (in1[1] & in2[1]) ^ (in1[0] & in2[2]) ^ (in1[2] &
in2[3]) ^ (in1[3] & in2[2]) ^ (in1[3] & in2[3]);
assign out[3] = (in1[3] & in2[0]) ^ (in1[2] & in2[1]) ^ (in1[1] & in2[2]) ^ (in1[0] &
in2[3]) ^ (in1[3] & in2[3]);
endmodule
//CHAIN- SEARCH ALGORITHM//
module chain_block (out_root, chain_comp, lambda0, lambda1, lambda2, lambda3,
clk, reset, active_chains);
output [0:14] out_root;
output chain_comp;
113
input [3:0] lambda0, lambda1, lambda2, lambda3;
input active_chains, reset, clk;
wire [3:0] cs0_out, cs1_in_in_out, cs2_in_in_out, cs3_in_in_out;
wire [3:0] lambdaval;
wire errordetect;
//wire [4:0] cntr;
//wire init, ld, hld;
reg init, ld, hld, cntr, chain_comp;
reg [5:0] cntr;
initial cntr = 5'b0;
always@ (posedge clk)
begin
if(active_chains)
if (cntr >= 20)
cntr <= cntr;
else
cntr <= cntr + 1;
else
cntr<= 5'b0;
end
always@ (posedge clk)
begin
114
if(reset)
begin
init = 0;
ld = 0;
hld = 0;
cntr = 0;
chain_comp = 0;
end
else if(cntr==0)
begin
init = 0;
ld = 0;
hld = 0;
cntr = 0;
chain_comp = 0;
end
else if(cntr == 1)
begin
init = 0;
ld = 1;
hld = 0;
cntr = 0;
115
end
else if(cntr == 2)
begin
init = 1;
ld = 1;
hld = 0;
cntr = 1;
end
else if(cntr == 19)
begin
init = 1;
ld = 0;
hld = 1;
cntr = 0;
chain_comp = 1;
end
end
//*******************//
// Chain Search block //
//*******************//
degree0_block cs0_block (cs0_out, lambda0, clk, init, ld, hld);
degree1_block cs1_in_in_block(cs1_in_in_out, lambda1, clk, init, ld, hld);
116
degree2_block cs2_in_in_block(cs2_in_in_out, lambda2, clk, init, ld, hld);
degree3_block cs3_in_in_block(cs3_in_in_out, lambda3, clk, init, ld, hld);
sipo_15 sp(out_root, errordetect, clk, cntr, hld, reset);
assign lambdaval = (cs0_out ^ cs1_in_in_out) ^ (cs2_in_in_out ^ cs3_in_in_out);
assign errordetect = ~((lambdaval[0]|lambdaval[1]) |
(lambdaval[2]|lambdaval[3]));
endmodule
//***********************************************//
// Module for terms whose degree is zero
//
//***********************************************//
module degree0_block(out, in, clk, init, ld, hld);
input [3:0] in;
output [3:0] out;
input clk, init, ld, hld;
wire [3:0] outmux, outreg;
register4_wl register(outreg, outmux, clk, ld, hld);
mux2_to_1 multiplex(outmux, in, outreg, init);
assign out = outreg;
endmodule
//********************************************************//
// Module that computes term with degree one.
117
//********************************************************//
module degree1_block(out, in, clk,init, ld, hld);
input [3:0] in;
output [3:0] out;
input clk, ld, init, hld;
wire [3:0] outmux, outmult, outreg;
register4_wl register(outreg, outmux, clk, ld, hld);
mux2_to_1 multiplexer(outmux, in, outmult, init);
//Multipy variable-alpha^1
assign outmult[0] = outreg[3];
assign outmult[1] = outreg[0] ^ outreg[3];
assign outmult[2] = outreg[1];
assign outmult[3] = outreg[2];
assign out = outreg;
endmodule
//********************************************************//
// Module that computes term with degree two.
//********************************************************//
module degree2_block(out, in, clk, init, ld, hld);
input [3:0] in;
output [3:0] out;
input clk, ld, init, hld;
118
wire [3:0] outmux, outmult, outreg;
register4_wl register(outreg, outmux, clk, ld, hld);
mux2_to_1 multiplexer(outmux, in, outmult, init);
//Multipy variable-alpha^2
assign outmult[0] = outreg[2];
assign outmult[1] = outreg[2] ^ outreg[3];
assign outmult[2] = outreg[0] ^ outreg[3];
assign outmult[3] = outreg[1];
assign out = outreg;
endmodule
//********************************************************//
// Module that computes term with degree three.
//********************************************************//
module degree3_block(out, in, clk, init, ld, hld);
input [3:0] in;
output [3:0] out;
input clk, ld, init, hld;
wire [3:0] outmux, outmult, outreg;
register4_wl register(outreg, outmux, clk, ld, hld);
mux2_to_1 multiplexer(outmux, in, outmult, init);
//Multipy variable-alpha^3
assign outmult[0] = outreg[1];
119
assign outmult[1] = outreg[1] ^ outreg[2];
assign outmult[2] = outreg[2] ^ outreg[3];
assign outmult[3] = outreg[0] ^ outreg[3];
assign out = outreg;
endmodule
//*************************//
// Multiplexer 2 to 1 4bit //
//*************************//
/*module mux2_to_1(out, in1, in2, sel);
input [3:0] in1, in2;
input sel;
output [3:0] out;
reg [3:0] out;
always@(sel or in1 or in2)
begin
case(sel)
0 : out = in1;
1 : out = in2;
default: out = in1;
endcase
end
endmodule*/
120
//**************************************//
// Register 4 bit with synchronous ld and hld //
//**************************************//
module register4_wl(dataout, datain, clk, ld, hld);
input [3:0] datain;
output [3:0] dataout;
input clk, ld, hld;
reg [3:0] dataout;
always@(posedge clk)
begin
if(ld)
dataout <= datain;
else if(hld)
dataout <= dataout;
else
dataout <= 4'b0;
end
endmodule
//**************************************//
// 15 bit Serial in Parallel out shift //
// register
//**************************************//
121
module sipo_15(sp_out, sp_in, clk, cntr, hld, reset);
input sp_in, clk, hld, reset, cntr;
output [0:14] sp_out;
reg[14:0] r;
assign sp_out = r;
always @(posedge clk)
begin
if (reset)
r<= 15'b000_0000_0000_0000;
else if (cntr)
r<= {sp_in,r[14:1]};
else if (hld)
r<= r;
else
r<= 15'b000_0000_0000_0000;
end
endmodule
//ERROR CORRECTION BLOCK//
module errorcorr_block (codword, out_root, data, clk, reset, active_error);
output [14:0] codword;
input [14:0] data;
input [0:14] out_root;
122
input clk, reset, active_error;
reg [14:0] cd;
assign codword = cd;
always @(posedge clk)
begin
if (reset)
cd<= 15'b000_0000_0000_0000;
else if(active_error)
begin
cd[0] <= out_root[0] ^ data[0];
cd[1] <= out_root[1] ^ data[1];
cd[2] <= out_root[2] ^ data[2];
cd[3] <= out_root[3] ^ data[3];
cd[4] <= out_root[4] ^ data[4];
cd[5] <= out_root[5] ^ data[5];
cd[6] <= out_root[6] ^ data[6];
cd[7] <= out_root[7] ^ data[7];
cd[8] <= out_root[8] ^ data[8];
cd[9] <= out_root[9] ^ data[9];
cd[10] <= out_root[10] ^ data[10];
cd[11] <= out_root[11] ^ data[11];
cd[12] <= out_root[12] ^ data[12];
123
cd[13] <= out_root[13] ^ data[13];
cd[14] <= out_root[14] ^ data[14];
end
else
cd<= 15'b000_0000_0000_0000;
end
endmodule
124
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codes”, Inf. Cntrl, 3, pp. 68-79, March 1960.
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17, (4), pp. 464-466.
[3] C. E. Shannon, ``A mathematical theory of communication,'' Bell System Technical
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university of Huddersfiel, September 1997.
[5] W.W. Peterson, E.J. Weldon, “Error correcting codes”, MIT Press, Cambridge, MA,
1972.
[6] W.W. Peterson, “Encoding and error-correction procedures for the Bose-Chaudhuri
Codes”, IRE Trans. Inf. Theory, IT-6, pp. 459-470, September 1960.
[7] Joel Sylvester “Reed Solomon Codes”, Elekrobit., January 2001.
[8] G. D. Farney, lr., "The Viterbi algorithm", Proc. IEEE, vol. 61, pp. 268-278, Mar.
1973.
[9] Softjin technology, “Data sheet for BCH encoder_LFSR core’, India, Dec 2000,
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[10] Hanho Lee, “An area-efficient Euclidean Algorithm block for Reed-Solomon
Decoder”, Dept. of ECE, University of Conecticut, Srorrs, CT 0 6269, USA.
[11] Dilip V. Sarwate, Naresh R. Shanbhag, “High-Speed Architectures for ReedSolomon Decoders,” IEEE Trans. On VLSI Systems, vol.9 No.5, Oct. 2001.
125
[12] Yanni Chen, Keshab K. Parhi, “Area Efficient Parallel Decoder Architecture for
Long BCH Codes”, Dept. of ECE, University of Minneapolis, MN 55455 USA
[13] Clifford Kraft, “Closed Solution of Berlekamp’s Algorithm for Fast Decoding of
BCH Codes”, IEEE Transactions on Communications, Vol. 39, No. 12, December1991.