SEMICONDUCTOR DEFECT IDENTIFICATION, ANALYSIS, AND REDUCTION
THROUGH MACHINE VISION
James C. Patton
B.S., California State University, Sacramento, 2000
PROJECT
Submitted in partial satisfaction of
the requirements for the degree of
MASTER OF SCIENCE
in
MECHANICAL ENGINEERING
at
CALIFORNIA STATE UNIVERSITY, SACRAMENTO
SPRING
2010
SEMICONDUCTOR DEFECT IDENTIFICATION, ANALYSIS, AND REDUCTION
THROUGH MACHINE VISION
A Project
by
James C. Patton
Approved by:
__________________________________, Committee Chair
Susan L. Holl, Ph.D.
__________________________________, Second Reader
Tien I. Liu, Ph.D.
____________________________
Date
ii
Student: James C. Patton
I certify that this student has met the requirements for format contained in the University format
manual, and that this project is suitable for shelving in the Library and credit is to be awarded for
the Project.
__________________________, Graduate Coordinator
Kenneth S. Sprott, Ph.D.
Department of Mechanical Engineering
iii
________________
Date
Abstract
of
SEMICONDUCTOR DEFECT IDENTIFICATION, ANALYSIS, AND REDUCTION
THROUGH MACHINE VISION
by
James C. Patton
Defect monitoring is a necessity in the semiconductor manufacturing industry. It is a
process characterized by the regular inspection of its product during the significant portions of
assembly. Defect monitoring is accomplished using automated inspection equipment capable of
machine-vision. Machine-vision allows for the regular collection of defect data used to quantify
and objectionably judge the quality of the processes and equipment responsible for the
semiconductor manufacturing. NEC Electronics in Roseville, California employs such a system.
Their defect monitoring process uses machine vision to collect defect data. This data affords their
Defect Detection Engineering department the opportunity to understand how to control and
reduce the typical and atypical defects observed.
This project centers on a critical, atypical defect discovered during the metallization
portion of process assembly. The defect was named, “Gouged SiO2.” This project will reveal how
machine vision was able to detect Gouged SiO2 using template-matching processes. It will detail
how engineering was able to investigate for its root cause using a machine-vision function called,
iv
“Defect-Source Analysis.” Finally, it will reveal how the defect was resolved and its
countermeasure validated using feature-extraction analysis; another machine-vision capability.
All of these techniques used to characterize and solve Gouged SiO2 are functions of the
machine-vision defect detection device called the “KLA2367.” The KLA2367 was the keystone
equipment to understanding and solving the Gouged SiO2 defect, resulting in an improved quality
process validated through higher wafer test-yield results.
_______________________, Committee Chair
Susan L. Holl, Ph.D.
_______________________
Date
v
TABLE OF CONTENTS
Page
List of Tables ........................................................................................................................ viii
List of Figures .......................................................................................................................... ix
Chapter
1. INTRODUCTION ………………..……………………………………………………… 1
1.1
Purpose and Problem ..................................................................................... 1
2. BACKGROUND OF THE STUDY ................................................................................... 3
2.1
IC Manufacturing Background ...................................................................... 3
2.2
IC Metallization Background………………………………………………. 5
2.3
Metallization Process (Step-by-Step) ............................................................. 7
2.4
Distributed Inspection at Metallization ……………………………………. 8
2.5
Machine Vision…………………………………………………………….. 9
2.5.1
Image Acquisition and Digitization……………………………. 10
2.5.2
Image Processing and Analysis……………………………….... 11
2.5.3
Interpretation………………………………………………….... 13
3. OBSERVATION AND ANALYSIS OF THE DATA………………………………….. 18
3.1
Gouged SiO2 Defect Observation…………………………………………. .18
3.2
Defect Source Analysis (DSA)……………………………………………. .21
3.3
Coordinate Subtraction……………….…………………………………… .21
4. FINDINGS AND INTERPRETATIONS………………………………………………. .24
5.
4.1
DSA Summary and Results........................................................................... 24
4.2
Gouged SiO2 Defect Progression………………………………………...... 27
4.3
Conclusions………………………………………………………………... 27
GOUGED SiO2 COUNTERMEASURE………………………………………………. 28
5.1
Analysis and Engineering Evaluation………………………………………28
5.2
Countermeasure Results…………………………………………………… 33
5.3
Countermeasure Conclusions……………………………………………… 33
5.4
Countermeasure Implementation (Mass Production)………………………34
5.5
Monitoring of Gouged SiO2 Through Feature Extraction…………………. 35
5.6
Gouged SiO2 Feature Extraction Monitor Conclusions…………………… 37
vi
Appendix A ............................................................................................................................. 38
Bibliography ........................................................................................................................... 48
vii
LIST OF TABLES
Page
1.
Table 1: Metallization Process Flow (Step-by-Step).…………………………. 24
2.
Table 2: DSA Inspection Insertion……………………………………………. 25
3.
Table 3: Metallization Process Flow (1st Al Layer through 2ndAl Layer).……. 30
4.
Table 4: Metallization Process Flow (With Engineering Evaluations)……..... 32
5.
Table 5: Evaluation Results for Wet Back Etch Experiment............................ 33
6.
Table 6: Metallization Process Flow (With Added Inspection Checkpoints)... 35
7.
Table 7: Defect Table with Feature Extraction Data (Example)……………... 36
viii
LIST OF FIGURES
Page
1.
Figure 1: Illustration of IC (Integrated Circuit) Process Flow…………………. 3
2.
Figure 2: Illustration of Process Flow With/Without Checkpoint Inspections…4
3.
Figure 3: Illustration of Wafer Fabrication, Metallization, and Electrical Test... 5
4.
Figure 4: Cross-Section of Die Featuring Metallization Layers.………………..6
5.
Figure 5: Illustration of Metallization Process (Step-by-Step)………………... 7
6.
Figure 6: Illustration of Metallization with Inspection Checkpoints………….. 8
7.
Figure 7: Illustration of Machine Vision Components………………………... 9
8.
Figure 8: Gray-Scale Spectrum………………………………………………..10
9.
Figure 9: Illustration of Analog-to-Digital Conversion……………………….10
10.
Figure 10: Illustration of Segmentation………………………………………..11
11.
Figure 11: Illustration of Pixelated Feature Extraction………………………..12
12.
Figure 12: Illustration of Template-Matching Technique……………………..13
13.
Figure 13: Illustration of Difference Detection………………………………..14
14.
Figure 14: Illustration of Candidate and Reference Die……………………….15
15.
Figure 15: Difference Detection of Candidate Die and Reference Dies……....15
16.
Figure 16: Defective and Non-Defective Image Examples…………………...16
17.
Figure 17: Illustration of Defective and Non-Defective Image Validation…. .16
18.
Figure 18: Illustration of Wafer Scan and Defect Map Results…………….... 17
19.
Figure 19: Illustration of Metallization with Checkpoint Inspections………..18
20.
Figure 20: Electron Microscope Images of Gouged SiO2…………………….18
ix
21.
Figure 21: Images of Non-Critical Defect Types…………………………..... 19
22.
Figure 22: The 2Ti-TiN Defect Trends (Inspection Checkpoint Monitor)….. 20
23.
Figure 23: Illustration of Coordinate Subtraction……………………………. 23
24.
Figure 24: DSA Breakdown of Defect Adders………………………………. 26
25.
Figure 25: Illustration of Anisotropic Etch With/Without Inhibitor……….... 28
26.
Figure 26: Images of Particulates Observed After Metal-Etch…………….... 29
27.
Figure 27: Illustration of Gouged SiO2 Mechanism………………………..... 31
x
1
Chapter 1
INTRODUCTION
1.1
Purpose and Problem
In the IC (integrated circuit) semiconductor manufacturing industry there are generally
three principles that guide engineers responsible for the process. These three principles are:
1.
Providing the highest quality products for customers.
2.
Manufacturing at the lowest possible cost to retain profitability.
3.
Ensuring on-time delivery to the customer.
At NEC Electronics Roseville, the Defect Detection department is continuously aware of
these three principles. The Defect Detection Engineer has to understand and appreciate the
consequences of a process or equipment tool that has become defective. In an assembly line of
over 600 process steps, if a defective process or equipment tool were to go unnoticed, all three
principles would drastically become compromised. Therefore, when critical defects are detected
through regular process checkpoint inspections, it is necessary for the engineer to determine the
root-cause and provide a solution.
Such is the case for the Gouged SiO2 defect observed in the metallization portion of the
process flow. An investigation was launched upon observation of this new and critical defect.
There were no metrics at the time of discovery to determine how frequently (or infrequently) the
defect was occurring. Yet, electrical tests and failure-analysis would reveal Gouged SiO2 to be a
critical-defect type in need of a solution and prevention.
2
The critical Gouged SiO2 defect was identified using an automated inspection device
capable of machine vision. Its root-cause was determined and its solution and prevention was
tested and validated with the assistance of machine vision equipment. This project contains the
detailed plan, analysis, results and conclusions from these investigations. Successful
countermeasures were implemented and the Gouged SiO2 defect is no longer a threat to IC device
quality at NEC Electronics Roseville.
3
Chapter 2
BACKGROUND OF THE STUDY
2.1
IC (Integrated Circuit) Manufacturing Background
Integrated circuit manufacturing is performed through a wafer fabrication process. The
wafer fabrication process is an assembly line, which begins with a bare silicon wafer of a fixed
diameter and finishes as an electrically tested array of imprinted IC devices, all contained within
the wafer’s area. The assembly line or process flow varies according to the IC function (e.g. logic
devices, memory devices, power devices, etc). However, regardless of function, all process flows
from start to finish require several hundred steps of processing; some of which are greater than
600 process steps. As a result, a wafer’s process start time to its finish time can take more than 3months lead-time (Please see Figure #1 below).
Figure 1: Illustration of IC (Integrated Circuit) Process Flow
4
As a process engineer, it is very important to protect and maximize yield for electrically
tested wafers. Yield is a metric that is only available after electrical testing is complete. Yield is
defined as:
Yield = ( # of tested PASSING die / # of tested available die)
A higher yield gives evidence to a higher quality product and additionally will translate to a lower
overall process and product cost.
To protect yield, it is important to perform distributed inspections throughout the process
flow. These distributed inspections take place along the critical steps of the process and provide a
faster response to a potential quality issue. The goal of distributed inspection is to prevent further
cost from being added to defective products. Please see the Figure #2 below comparing
distributed and non-distributed inspection cases.[1]
Figure 2: Illustration of Process Flow With/Without Checkpoint Inspections
All NEC Electronics distributed inspections use machine vision. Machine vision is a
technology that allows for image data acquisition, processing and interpretation via computer for
application. In this case, machine vision inspections at NEC Electronics are used to detect
5
optically recognizable defects on 6-inch and 8-inch wafers. NEC Electronics uses a twodimensional (top-down view) machine vision equipment tool called a “KLA2367” for performing
these distributed inspections.
2.2
IC Metallization Background
Distributed inspections are performed at the critical portions of the process flow. An
extremely critical portion of the process flow includes the metallization process. The
metallization process is the portion of the flow that creates the metal interconnectivities among all
the transistors available to the device and is the focus area of this investigation. The metallization
process represents the final part of wafer fabrication just prior to electrical testing and shipment to
the customer.[2] Figure #3 illustrates where the metallization process occurs in wafer fabrication.
Metallization: Deposition, Pattering
and Etching of Aluminum layers for
interconnectivity among transistors
METALLIZATION Portion
of Process Flow
Electrical Test: Testing performed on
all available die of the wafer.
Wafer Electrical Testing
Wafer Fabrication (FAB)
Step 1: Receiving Bare Silicon
Wafer into NEC Roseville.
Final FAB step: Completed Wafer
Wafer
SENT TO
CUSTOMER
Figure 3: Illustration of Wafer Fabrication, Metallization, and Electrical Test
IC metallization requires three components: [2]
1. A metal layer (for conductivity)
2. A dielectric material (e.g. glass) as insulation to buffer subsequent metal layers
3. An electrical conduit within the dielectric connecting one metal layer to the next (called vias).
6
Shown below in Figure #4 is the metallization cross-section of an IC device revealing six
separate metal layers and six sets of vias.[7] Please note the dielectric material buffering the six
metal layers has been etched away in this cross-section.
Metal Layer #6 (Al or Cu)
VIA Layer #6
(Usually Tungsten-filled)
Metal Layer #5 (Al or Cu)
VIA Layer #3
(Usually Tungsten-filled)
Metal Layer #2 (Al or Cu)
VIA Layer #1
(Usually Tungsten-filled)
Figure 4: Cross-Section of Die Featuring Metallization Layers
7
2.3
Metallization Process (Step-by-Step)
The metallization process steps are shown below in Figure #5.
Step I (Given): A group of transistors settled
onto the silicon substrate.
Step II: Glass is deposited onto the wafer,
through a glass-deposition process known as
CVD (Chemical Vapor Deposition).
Step III: Glass planarization is performed to
create a smooth, planar surface of glass.
Step IV: A hard malleable plastic called
“photoresist” is patterned onto the wafer to
protect desired areas from subsequent
etching.
Step V: The wafer receives an anisotropic
dry-etching process, which removes the
material NOT protected by the photoresist at
a very controlled rate.
Step VI: After etching is complete, the
remaining photoresist is stripped away.
Afterwards, a very thin layer of titanium is
deposited, to improve via conductivity.
Step VII: Tungsten is then generously
deposited (CVD) onto the wafer.
Step VIII: Another planarization is performed
to remove all tungsten, except within the
vias.
Step IX: A uniform metal layer is deposited
onto the wafer through a sputter process.
Film resistance (on test wafers) is measured
to ensure target thickness is achieved.
Figure 5: Illustration of Metallization Process (Step-by-Step)
Step X: Steps II – VII are repeated as needed
to create multiple aluminum layers. The
number of required aluminum layers is a
function of transistor amount and device
function.
8
2.4
Distributed Inspection at Metallization
At metallization, distributed inspections are performed after metal-layer dry etch and via-
layer dry etch. However, not all metal and via layers will receive distributed inspection because
too many inspections would compromise the assembly-line speed. Therefore, only a limited
amount of inspections at metallization is performed. These inspections usually take place after the
first and second metal and via formations, and after the final metal layer is formed. Figure #6
illustrates when the metallization checkpoints take place.
Figure 6: Illustration of Metallization with Inspection Checkpoints
Metallization inspections at the steps shown above are regularly performed at NEC
Electronics. This project deals with the detection, root-cause analysis, prevention solution,
validation, and future monitoring methods regarding a particular critical defect (Gouged SiO2)
observed at the metallization inspection.
9
2.5
Machine Vision
The KLA2367 is an optical defect detection device that uses machine vision techniques
to detect image irregularities. If these irregularities exceed a preset threshold value assigned by
the user, then the KLA2367 flags the irregularity as a “defect.” The machine vision employed by
the KLA2367 has three components: [1]
1. Image Acquisition and Digitization
2. Image Processing and Analysis
3. Interpretation
Figure #7 (below) illustrates the role of each machine vision component.
Figure 7: Illustration of Machine Vision Components
10
2.5.1
Image Acquisition and Digitization
A high-resolution camera collects images of the feature for comparison. Digitization is
performed by dividing a viewing area into an array of discrete gray-scale picture elements known
as pixels. The gray-scale spectrum consists of values ranging from 0 to 255, where a value of “0”
represents pitch black intensity and a value of “255” represents bright white intensity. Please see
the Figure #8 directly below: [6]
Figure 8: Gray-Scale Spectrum
Each pixel in the pixel-array has a value that is proportional to the light intensity of that
portion of the feature. A digitized image is the result of an Analog-to-Digital conversion and
allows values to be assigned to each pixel (See Figure #9 directly below): [5]
Figure 9: Illustration of Analog-to-Digital Conversion
11
2.5.2
Image Processing and Analysis
Image acquisition and digitization yield significant amounts of data, which must be
quickly processed in order to allow continuous scanning of images without bottleneck. There are
several computing methods for the processing and analysis of the collected data. The techniques
employed by the KLA2367 are called Segmentation and Feature Extraction.[3]
Segmentation is an analysis technique that breaks the 0 – 255 gray level spectrum into
arbitrary groups of smaller spectra and allows the user to prescribe rules and threshold values for
each segment. This affords the user more flexibility because he may now prescribe multiple
thresholds over the 0 – 255 gray scale versus just one threshold for the entire spectrum.
For example, Figure #10 below displays a frame of and IC (Integrated Circuit) pattern
under machine vision. Without segmentation, only one rule (or threshold value) can be applied to
all pixels contained within the frame. However, by creating groups of spectra within the 0 – 255
gray-scale (Note: In this example four groups were created) the user can prescribe a unique
threshold for each spectra. This makes a machine vision inspection more robust and improves a
signal to noise ratio for defect capture rates, thus improving the quality of defect detection.
• The gray-scale spectrum for this image has values
ranging from 10 – 220.
• Without segmentation only ONE set of rules can be
prescribed to this spectrum (Rule1)
• The result is an inspection with a relatively lower
signal : noise ratio
• The same gray-scale spectrum for this image has
values ranging from 10 – 220.
• With segmentation, the user could break the spectrum
into 4 parts, with a unique rule for each spectrum:
= Spectrum values 10 – 60 (Rule1)
= Spectrum values 61 – 100 (Rule2)
= Spectrum values 101 – 180 (Rule3)
Figure 10: Illustration of Segmentation
= Spectrum values 181 – 220 (Rule4)
12
Feature extraction is another analysis technique performed through machine vision that
allows quantitative data collection for all features within a pixelated area. Data such as defect
length, area, position, etc. can all be acquired with a robust analysis model capable of feature
extraction. This defect data can be used to monitor for DOI (Defects of Interest).
For example, Figure #11 shown below is of a detected defect contained within the
pixelated frame. Metrics for this defect, such as its size, area, and location are collected during the
inspection since the dimensions of each pixel and the frame are known. This data is used to help
distinguish minor defects from major or critical types and is a prime example of the feature
extraction application.
Figure 11: Illustration of Pixelated Feature Extraction
Note:
With each detected defect, metrics such as a
defect’s size, area, location, etc. are collected
during inspection to assist with investigation.
13
2.5.3
Interpretation
The objective of this function is to identify objects in an image by comparing it to
predefined models or standard values. The interpretation technique used by the KLA2367 is
called template-matching. Template matching compares pixel-by-pixel images of a candidate
versus a reference image or images. It then performs a subtraction to determine if the difference
between corresponding pixel values from candidate and reference exceed a set threshold amount.
The three cases shown below along with Figure #12 illustrate a given pixel under comparison.[1]
Case 1 shows the difference between candidate and reference pixels to be “0.” Therefore, the
candidate pixel is deemed a “Non-Defective” pixel.
Case 2 shows the difference between candidate and reference pixels exceeding the prescribed
threshold value of “40.” Therefore, the candidate pixel is deemed as a “Defective” pixel.
Case 3 shows the difference between candidate and reference pixels to be less than the threshold
set value of “40.” Therefore, the candidate pixel is deemed a “Non-Defective” pixel.
Figure 12: Illustration of Interpretation Using Template-Matching Technique
14
The KLA2367 uses this template-matching function to detect visible defects on the
semiconductor wafers it inspects. Shown below in Figure #13 are the pixelated candidate and
reference images of a portion of an integrated circuit. Subtraction of corresponding pixels will
yield a gray-scale difference frame. Assuming corresponding pixels are identical in gray-scale
value, their difference will be “0,” thus a black color will fill the pixel. Assuming corresponding
pixels are significantly different in their gray-scale values (due to the presence of a defect on the
pixel), a grayish-white color will fill the pixel. If this gray-scale difference exceeds the preset
threshold value, then the pixel is flagged as defective.[3]
Figure 13: Illustration of Difference Detection
15
The KLA2367 is designed to continuously perform these three machine vision functions.
The tool scans each wafer individually and compares corresponding features of the “candidate”
die to its neighboring adjacent dies, called “reference” dies. Figures #14 and #15 below illustrates
this die-comparison process.
Figure 14: Illustration of Candidate and Reference Die
Figure 15: Difference Detection of
Candidate Die and Reference Dies
16
All candidate images are compared against multiple reference images (as many as eight
reference images). This provides the user two advantages. First, by having multiple reference
images the KLA2367 can truly determine which pixel(s) are defective. To illustrate, consider
Figure #16 below. [3]
Two pictures are given below, but which is “defective?”
In order to determine which picture is “defective” another picture (reference) is necessary.
Note: A third picture is needed
to determine which of these
pictures is truly “defective.”
Therefore, a true defect is only detected when a candidate image shows a significant gray-level
value difference versus both of its adjacent reference die. Otherwise, it is not a defect.
Figure 16: Defective and Non-Defective Image Examples
Figure #17 shown below depicts the gray-level subtraction of the example above.
Figure 17: Illustration of Defective and
Non-Defective Image Validation
17
The second advantage of using multiple reference die means a more robust and accurate
reference value. The KLA2367 is able to take the weighted average over several reference
candidates allowing a more accurate value of the true reference signal.
The KLA2367 performs inspection by physically swathing the entire wafer area under
high intensity laser light (Please see Figure #18 below). All images are acquired by the highresolution camera where they are digitized, processed, analyzed, and interpreted for defects.
Figure 18: Illustration of Wafer Scan and Defect Map Results
The result of a KLA2367 wafer scan is a called a .klrf defect map, with all defect
locations marked by coordinates which can be revisited using defect review tool equipment
(optical microscope, electron-microscope, Focused Ion-Beam, etc). Examples of a defect wafer
map and defect coordinate locations are shown in Figure #18.
18
Chapter 3
OBSERVATION AND ANALYSIS OF THE DATA
3.1
Gouged SiO2 Defect Observation
At a normal metallization inspection checkpoint (#2 Via-layer), Engineering began to
observe a unique and critical defect type. Figure #19 displays where the #2 Via-layer checkpoint
inspection takes place, where the Gouged SiO2 defect was first observed.
Figure 19: Illustration of Metallization with Checkpoint Inspections
This unique and critical defect type at the #2 Via-layer inspection checkpoint was
characterized as large pieces of missing dielectric material (e.g. missing glass). This defect was
immediately placed under investigation by Engineering and was given the name, “Gouged SiO2.”
Shown below in Figure #20 are electron microscope pictures of the DOI (Defect of Interest)
Gouged SiO2.
Figure 20: Electron Microscope Images of Gouged SiO2
These large pieces of missing glass significantly compromised device functionality and
were deemed critical defects because the vias contained within the missing dielectric material
were misshapen or missing. Misshapen or missing vias lead to irregular tungsten-plug amounts,
19
which translate into varying electrical resistances among aluminum circuits. These varying metal
resistances from the compromised vias fail spec for their resistance values, or for creating
open/short circuits.
As a comparison, some regularly observed non-critical defects at this inspection step are
shown in Figure #21 below to provide contrast to the critical Gouged SiO2 defect. These minor
defects types are regularly monitored and trended without cause for immediate wafer scrap or
process-line stoppage.
These via-layer inspection defects
are non-critical because they do not
significantly affect via patterning,
or tungsten plug amount.
However, defects like these are
trended regularly to monitor both
wafer-fab process and equipment,
but are not immediate cause for
wafer scrap.
Figure 21: Images of Non-Critical Defect Types
20
Unfortunately with this new defect type, there were no current metrics for quantifying
how frequently (or infrequently) the Gouged SiO2 was occurring. Attempting to use the regularly
monitored defect trends was not specific enough to determine Gouged SiO2 frequency, examples
of which are shown below in Figure #22.
Figure 22: The 2Ti-TiN Defect Trends (Inspection Checkpoint Monitor)
An investigation into Gouged SiO2 was launched because inspection checkpoint results at
the Via-layer were confirming the presence of Gouged SiO2, yet no metric existed to determine
how frequently the critical defect was occurring. The investigation contained three parts:
1.
Identify and determine the cause of Gouged SiO2.
2.
Prescribe the countermeasure to decrease/prevent Gouged SiO2.
3.
Determine if feature extraction methods exist for Gouged SiO2 monitoring.
21
3.2
Defect Source Analysis
To determine the cause of this critical defect, four machine-vision inspections were
inserted between the normal 1st Aluminum layer checkpoint inspection and the #2 Via layer
checkpoint inspection. These additional inspections were used to specifically determine when
Gouged SiO2 began and how it progressed accordingly through the process flow. Use of
additional machine-vision inspections to investigate the source of a defect of interest is known as
a “DSA” (Defect Source Analysis).
DSA allows the user to determine if a defect of interest (in this case, Gouged SiO2) at a
normal inspection checkpoint had been previously detected in a prior inspection. This function is
performed through KLA2367 coordinate subtraction. Four additional DSA inspections were
prescribed for a multiple-wafer batch prior to receiving its normal #2-Via inspection for
investigation.
3.3
Coordinate Subtraction
The feature extraction abilities of the KLA2367 afford the user an important capability
when performing a DSA. Assuming the same wafers are inspected at each inspection checkpoint,
the KLA2367 is able to determine which defects are newly added, versus those originally
detected at a prior inspection checkpoint. Newly detected defects at a checkpoint inspection are
called, “adders” while redetected defects are called, “carryovers.” Since every detected defect is
assigned a coordinate location (with respect to the wafer center), the KLA2367 is able to
determine adders from carryovers using a function called “coordinate subtraction.” Coordinate
subtraction uses a Cartesian coordinate system to subtract the horizontal and vertical components
of a defect’s location against all previously detected defects from prior inspection checkpoints. If
the corresponding coordinate difference exceeds a preset threshold distance, the defect is
22
considered an “adder.” If the difference is contained within the threshold distance, then the defect
is considered a “carryover.”
For example, please see the Figure #23. The four inspection checkpoints in this example
are chronologically labeled “I” through “IV.” The first inspection resulted in two total defects,
each with its own unique Cartesian coordinate location. The second inspection resulted in four
total defects. However, because the KLA2367 performs “coordinate subtraction,” it reveals to the
user that two of the four defects were previously detected at the first inspection checkpoint.
Likewise, with the fourth inspection checkpoint; it has six total defects. However, the coordinate
subtraction function allows the tool to reveal that five of the six detected defects are carryovers
from previous inspections. Thus, the KLA2367 uses this coordinate subtraction function to
determine which defects are adders and which are carryovers. [3]
23
Figure 23: Illustration of Coordinate Subtraction
24
Chapter 4
FINDINGS AND INTERPRETATIONS
4.1
DSA Summary and Results
Shown below in Table #1 is a portion of the metallization process flow. The portion
begins with step #512 (#1 Aluminum Checkpoint Inspection) and ends at step #541 (#2 Via
Checkpoint Inspection), when Gouged SiO2 is observed. Shown below to the right is where the
additional DSA inspections were inserted in order to determine the root cause of the defect and
observe its progression through the process flow. A total of five checkpoint inspections
(highlighted below) were used for Gouged SiO2 DSA investigation.
Table 1: Normal Metallization process flow (Left) and the
investigative process flow, with added DSA inspections (right).
PROCESS STEP #
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
MAJORSTEPCODE
1 Aluminum Layer
1 Plasma SiO2 CVD
1 Plasma SiO2 CVD
1st O3 TEOS SiO CVD
1st O3 TEOS SiO CVD
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
(1) H2 Alloy
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
2 Ti-TiN Sputter
2 Ti-TiN Sputter
2 Ti-TiN Sputter
#2 VIA Layer
MINORSTEPCODE
Checkpoint Inspection
1 Plasma SiO2 CVD
T SiO2
1 O3 TEOS SiO CVD
T Ox
2 Plasma SiO2 CVD
T SiO2
O2 Plasma Etch
Interfab Transfer
T Ox 1
SiO2 CMP
Remaining Tox
Interfab Transfer
Scrub
(1) H2 Alloy
Posi PR Spin
Align/Expose
Posi Develop
On-Line Registration Chk
Develop Inspection
Through Hole Plasma Etch
Plasma PR Strip
Post Etch Strip
Jet Scrub
Strip Inspection
UV Cure
2 Ti-TiN Sputter
Sheet Resistance
Jet Scrub
Checkpoint Inspection
Modified
Gouged SiO2 here!
PROCESS STEP #
512
513
514
515
516
517
518
EVALUATION
519
520
521
EVALUATION
522
EVALUATION
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
MAJORSTEPCODE
1 Aluminum Layer
1 Plasma SiO2 CVD
1 Plasma SiO2 CVD
1st O3 TEOS SiO CVD
1st O3 TEOS SiO CVD
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
Engineer Evaluation
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
Engineer Evaluation
2 Plasma SiO2 CVD
Engineer Evaluation
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
(1) H2 Alloy
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
Through Hole (Cu) MASK
2 Ti-TiN Sputter
2 Ti-TiN Sputter
2 Ti-TiN Sputter
#2 VIA Layer
MINORSTEPCODE
Checkpoint Inspection
1 Plasma SiO2 CVD
T SiO2
1 O3 TEOS SiO CVD
T Ox
2 Plasma SiO2 CVD
T SiO2
Automatic Inspect
O2 Plasma Etch
Interfab Transfer
T Ox 1
Automatic Inspect
SiO2 CMP
Automatic Inspect
Remaining Tox
Interfab Transfer
Scrub
(1) H2 Alloy
Posi PR Spin
Align/Expose
Posi Develop
On-Line Registration Chk
Develop Inspection
Through Hole Plasma Etch
Plasma PR Strip
Post Etch Strip
Jet Scrub
Strip Inspection
UV Cure
2 Ti-TiN Sputter
Sheet Resistance
Jet Scrub
Automatic Inspect
Note: At the VIA-layer inspection, the critical defect was present. Therefore, data was collected BEFORE this inspection step to determine how the defect was taking place.
• All defects at each inspection checkpoint are either “Adders” or “Carryovers.” This calculation is performed by the KLA system.
• Electron microscope analysis is performed at each checkpoint to record “Adder” defects and monitor “Carryover” defect changes as they move through process flow.
25
A seven-wafer batch was used to perform the five-checkpoint inspection DSA. The five
checkpoint inspection locations (in process flow/chronological order) were:
Inspection No.
Inspection Name:
Description
1
1st Aluminum Layer
Standard 1st Al Layer inspection checkpoint
2
Inspection After SiO2 deposition
Inspection after dielectric material is deposited
3
Inspection After O2 Ashing
Ashing pretreats the SiO2 prior to planarization
4
Inspection After SiO2 CMP
Inspection after Chemcial Mechanical Planarization
5
#2 Via-Layer
Standard #2 Via-Layer inspection checkpoint
Table 2: DSA Inspection Insertion
26
Results of the DSA summary are shown in Figure #24 below with each inspection
checkpoint revealing the amount of defect adders observed.
Defect Amounts (Adders & Carryovers for Each Checkpoint Inspection)
7-Wafer Evaluation
700
Non-Critical Via Layer Defects
600
500
400
Current Layer Particles
501
300
200
58
139
100
96
158
54
58
59
60
59
After SiO2 CVD
After O2 Ashing
After SiO2 CMP
0
1Al Inspection
1Al Layer Defs
SiO2 CVD Defs
O2 Ashing Defs
GOUGED SiO 2
24
After #2-Via Mask
& Etch Inspection
Via Mask & Etch Defs
Figure 24: DSA Breakdown of Defect Adders
Note: How to read this stacked-column chart:
• The abscissa represents the inspection checkpoint (in process flow/chronological order).
• The ordinate represents the defect count of all 7 wafers (summed) at the inspection checkpoint of interest.
• Each color on the bar chart represents the defect amount as a function of:
Blue = Defects originally caught at 1st Aluminum Layer
Pink = Defects originally caught at after SiO2 CVD (Chemical Vapor Depositioning)
Red = Defects originally caught after O2 Ashing.
Green = Defects originally caught after #2-Via processing (Masking & Etching)
27
4.2
Gouged SiO2 Defect Progression
Additionally, electron microscopic images of defects of interest were recorded to monitor
their progression throughout the process flow. The results give visual evidence regarding the rootcause of Gouged SiO2, its progression through the process, and how critical the defect is to
metallization. These images revealing Gouged SiO2 progression are contained within the
“Appendix: Gouged SiO2 Defect Progression (1) and (2)” of this project.
4.3
Conclusions
Gouged SiO2 is the result of large particles buried beneath or within the SiO2 prior to
CMP (Chemical Mechanical Planarization). The CMP process dislodges the defect, resulting in a
patch of missing dielectric material.
Additionally, the large current layer particles detected at the 1st Al inspection checkpoint
result in Gouged SiO2 at the subsequent via inspection step. The added particles caught at the 2nd
inspection checkpoint (after SiO2 CVD) also result in Gouged SiO2 at the same subsequent via
inspection step. Current layer particles added by the O2 Ashing just prior to CMP do not result in
Gouged SiO2. Finally, the CMP process by itself is not a root cause of Gouged SiO2.
28
Chapter 5
GOUGED SIO2 COUNTERMEASURE
5.1
Analysis and Engineering Evaluation
After NEC Roseville Engineering determined the origin of the Gouged SiO2 defect, the
information was shared with NEC Japan Headquarters (Defect Division) to assist with providing
a countermeasure. Their assessment was that the majority of the large particulates responsible for
the Gouged SiO2 were deposited onto the wafer after Aluminum dry-etching. Their reasoning was
that if the particulates had been present during the anisotropic dry-etch process of the aluminum
layer, then the particulate itself would have acted as an etch-inhibitor, leaving un-etched
aluminum material directly beneath the defect. Aluminum dry-etching is an anisotropic process,
therefore any inhibitor preventing etch would result in remaining material located directly
underneath. Figure #25 shown below illustrates how a particulate acting as an etch-inhibitor could
potentially leave un-etched material beneath it.
Case 1: An anisotropic-etch will
remove material in one axial
direction only. PhotoResist (PR) is
a hardened plastic patterned over
the areas of aluminum that will
remain after etching is complete.
Case 2: An anisotropic-etch inhibited
by a large particle. The particle
blocks the axial etch. When etching
is complete, the material directly
underneath the inhibitor will remain.
Figure 25: Illustration of Anisotropic Etch With/Without Inhibitor
29
Analysis of the large particles at the 1st Aluminum layer checkpoint inspection reveals
that the aluminum directly underneath is completely etched away, without compromise. If the
material underneath these large particulates is completely etched, then the presence of the
particulates must have occurred after the dry-etching of Aluminum. Figure #28 below displays
the particulates and reveals the aluminum underneath as completely etched.
Figure 26: Images of Particulates Observed After Metal-Etch
This key observation provides a process-window for when this particulate takes place in
the metallization process flow. If the defect initially occurs after metal etching, but before metal
layer inspection (since this is when the defect was first observed in the DSA investigation), then
analysis into the metallization process flow reveals the Aluminum Baking heat process to be
suspect and potentially responsible for particulate deposition onto the wafers.
30
Shown below in Table #3 is the metallization process flow. If the large particulates (DOI)
are being detected at the 2nd Aluminum inspection checkpoint, and the same particulates take
place after 2nd Aluminum Etching, then the 2nd Aluminum Bake heat process is potentially
responsible for the DOI (Defect of Interest).
PROCESS STEP #
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527 - 537
538
539
540
541
542
543
544
545
546
547 - 557
558
559
MAJORSTEPCODE
MINORSTEPCODE
1 Aluminum Layer
Checkpoint Inspection
1 Plasma SiO2 CVD
1 Plasma SiO2 CVD
1 Plasma SiO2 CVD
T SiO2
1st O3 TEOS SiO CVD
1 O3 TEOS SiO CVD
1st O3 TEOS SiO CVD
T Ox
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
T SiO2
2 Plasma SiO2 CVD
O2 Plasma Etch
2 Plasma SiO2 CVD
Interfab Transfer
2 Plasma SiO2 CVD
T Ox 1
2 Plasma SiO2 CVD
SiO2 CMP
2 Plasma SiO2 CVD
Remaining Tox
2 Plasma SiO2 CVD
Interfab Transfer
2 Plasma SiO2 CVD
Scrub
(1) H2 Alloy
(1) H2 Alloy
2 VIA PATTERNING
PATTERNING
2 VIA ETCHING
ETCHING
2 Ti-TiN Sputter
2 Ti-TiN Sputter
2 Ti-TiN Sputter
Sheet Resistance
2 Ti-TiN Sputter
Jet Scrub
#2 VIA Layer
Checkpoint Inspection
2 VIA Tungsten
2 VIA W CVD
2 VIA Tungsten
2 VIA W CMP
2 Aluminum Layer
2 Ti-TiN Sputter
2 Aluminum Layer
Jet Scrub
2 Aluminum Layer
2Al Sputter
2 Aluminum Layer PATTERNING
PATTERNING
2 Aluminum Layer Etching
ETCHING
2 Aluminum Bake
2 Al Baking
2 Aluminum Layer
Checkpoint Inspection
Table 3: Metallization Process Flow (1st Al Layer
through 2nd Al Layer)
Patterning & Etching are exonerated.
Baking is causing particulates to fall onto the wafers.
DOI (Defect of Interest) detected here.
31
The theory from NEC Japan’s Defect Division was that SiO2 was remaining after Viaetching on the wafer’s backside. This remaining SiO2 flakes off during subsequent baking, which
later results in Gouged SiO2. Because the defects are on the surface at the metal inspection step,
NEC Japan’s Defect Division believed an upstream pre-treatment would be able to prevent these
particulates. Their belief was that the defect could be prevented by ensuring complete removal of
any residual SiO2 from the wafer backside. Please see the Figure #27 below for an illustration of
the defect mechanism.
Figure 27: Illustration of Gouged SiO2 Mechanism
32
CVD (Chemical Vapor Deposition) is the only process responsible for SiO2 deposition
during metallization. The NEC Japan Defect Division suggested an insertion of a short WBE
(Wet Backside-Etch) step immediately following SiO2 deposition as an engineering evaluation.
This wet-etch bath step would isotropically etch SiO2. Moreover, because SiO2 thickness is
significantly greater on the frontside of the wafer versus its backside, there is enough process
margin to easily accommodate an SiO2 WBE step. This WBE step will ensure a complete
backside SiO2 removal without compromise to the frontside SiO2, or its function. Please see
Table #4 to determine when the WBE evaluation would be inserted into the process flow.
For evaluation purposes, four batches each containing three wafers received the
experimental WBE (Wet Back Etch) directly after SiO2 CVD deposition. The purpose of these
four batches was to validate backside SiO2 removal, thus preventing Gouged SiO2. This
evaluation was repeated for the #3-Via layer as well. Twelve wafers (over the four different
evaluation batches) were used to validate the experiment.

Apply WBE after SiO2 CVD (Evaluation Step).
Then prescribe a Wet Back Etch step (upstream)
to remove any residual SiO2, which may become
Gouged SiO2; The defect of interest!
PROCESS STEP #
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527 - 537

Normal Inspection Checkpoint (2 Aluminum Layer)
If this is where the large particulates are being
observed, which lead to Gouged SiO2 defects…
538
539
540
541
542
543
544
545
546
547 - 557
558
559
MAJORSTEPCODE
MINORSTEPCODE
1 Aluminum Layer
Checkpoint Inspection
1 Plasma SiO2 CVD
1 Plasma SiO2 CVD
1 Plasma SiO2 CVD
T SiO2
1st O3 TEOS SiO CVD
1 O3 TEOS SiO CVD
1st O3 TEOS SiO CVD
T Ox
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
T SiO2
WET BACK ETCH (WBE Evaluation)
2 Plasma SiO2 CVD
O2 Plasma Etch
2 Plasma SiO2 CVD
Interfab Transfer
2 Plasma SiO2 CVD
T Ox 1
2 Plasma SiO2 CVD
SiO2 CMP
2 Plasma SiO2 CVD
Remaining Tox
2 Plasma SiO2 CVD
Interfab Transfer
2 Plasma SiO2 CVD
Scrub
(1) H2 Alloy
(1) H2 Alloy
2 VIA PATTERNING
PATTERNING
2 VIA ETCHING
ETCHING
2 Ti-TiN Sputter
2 Ti-TiN Sputter
2 Ti-TiN Sputter
Sheet Resistance
2 Ti-TiN Sputter
Jet Scrub
#2 VIA Layer
Checkpoint Inspection
2 VIA Tungsten
2 VIA W CVD
2 VIA Tungsten
2 VIA W CMP
2 Aluminum Layer
2 Ti-TiN Sputter
2 Aluminum Layer
Jet Scrub
2 Aluminum Layer
2Al Sputter
2 Aluminum Layer PATTERNING
PATTERNING
2 Aluminum Layer Etching
ETCHING
2 Aluminum Bake
2 Al Baking
2 Aluminum Layer
Checkpoint Inspection
Table 4: Metallization Process Flow (With Engineering Evaluations)
33
5.2
Countermeasure Results
Shown below in Table #5 are the evaluation results for the four batches consisting of
twelve wafers receiving the experimental WBE pre-treatment.
Table 5: Evaluation Results for Wet Back Etch Experiment
No suspect particulates were observed for any of the WBE evaluation wafers.
5.3
Countermeasure Conclusions
At aluminum checkpoint inspection, the aluminum directly underneath the defect of
interest is completely etched. Therefore, the defect must be a function of heat-treatment (e.g.
Aluminum Baking).
By inserting an upstream WBE (Wet Back-Etch) step directly after SiO2 CVD processes,
residual backside SiO2 is removed from the wafers. This prevents any backside SiO2 from
depositing onto the wafer’s frontside at subsequent baking steps.
The WBE upstream step is successful at preventing the DOI (Defect of Interest).
Note: The remaining backside SiO2 and WBE countermeasure were conceived by NEC Japan.
34
5.4
Countermeasure Implementation (Mass Production)
With NEC Japan permission, NEC Roseville implemented WBE (Wet Back Etch)
countermeasure. In late December 2008, when WBE was implemented on a limited-production
basis, a noticeable reduction in the amount of Open/Short failures was realized. Please see
“Appendix: Gouged SiO2 Countermeasure Limited Production Yield Results (1)” of this project.
This reduction in failure helped improve EFT (Easy Function Testing) of available die, translating
into higher device yield. Additionally, as the WBE process was slowly globalized for all metal
layers in the metallization process, the yield graphs revealed the more WBE treatments a batch
received, the higher its yield improvement. Please see “Appendix: Gouged SiO2 Countermeasure
Limited Production Yield Results (2)” of this project.
35
5.5
Monitoring of Gouged SiO2 Through Feature Extraction
Feature extraction is a machine-vision analysis technique that allows quantitative data
collection for all features within a pixelated area. Data such as defect length, area, position, etc.
can all be acquired with a robust analysis model capable of feature extraction. This defect data
can be used to monitor for defects of interest (DOI).
When choosing to create a new feature extraction monitoring-metric for a DOI, the layer
when inspection takes place is of primary concern. The successful identification, root-cause
analysis, and countermeasure of Gouged SiO2 have resulted in the permanent insertion of a WBE
(Wet-Etch Back) step in the metallization process flow, located after SiO2 deposition. An updated
metallization process flow is shown on Table #6 below.
PROCESS STEP #
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527 - 537
538
539
540
541
542
543
544
545
546
547 - 557
558
559
MAJORSTEPCODE
MINORSTEPCODE
1 Aluminum Layer
Checkpoint Inspection
1 Plasma SiO2 CVD
1 Plasma SiO2 CVD
1 Plasma SiO2 CVD
T SiO2
1st O3 TEOS SiO CVD
1 O3 TEOS SiO CVD
1st O3 TEOS SiO CVD
T Ox
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
2 Plasma SiO2 CVD
T SiO2
WET BACK ETCH (WBE Evaluation)
2 Plasma SiO2 CVD
O2 Plasma Etch
2 Plasma SiO2 CVD
Interfab Transfer
2 Plasma SiO2 CVD
T Ox 1
2 Plasma SiO2 CVD
SiO2 CMP
2 Plasma SiO2 CVD
Remaining Tox
2 Plasma SiO2 CVD
Interfab Transfer
2 Plasma SiO2 CVD
Scrub
(1) H2 Alloy
(1) H2 Alloy
2 VIA PATTERNING
PATTERNING
2 VIA ETCHING
ETCHING
2 Ti-TiN Sputter
2 Ti-TiN Sputter
2 Ti-TiN Sputter
Sheet Resistance
2 Ti-TiN Sputter
Jet Scrub
#2 VIA Layer
Checkpoint Inspection
2 VIA Tungsten
2 VIA W CVD
2 VIA Tungsten
2 VIA W CMP
2 Aluminum Layer
2 Ti-TiN Sputter
2 Aluminum Layer
Jet Scrub
2 Aluminum Layer
2Al Sputter
2 Aluminum Layer PATTERNING
PATTERNING
2 Aluminum Layer Etching
ETCHING
2 Aluminum Bake
2 Al Baking
2 Aluminum Layer
Checkpoint Inspection
If there is a failure at WBE to remove the residual SiO2,
the #2 VIA Checkpoint Inspection would serve as a
better monitoring step versus the 2 Aluminum
checkpoint inspection (+18 steps later in the flow).
If there is potential FAILURE at this step (e.g. Incomplete Etching)
This checkpoint inspection will catch the defect (Gouged SiO2) SOONER.
CANDIDATE #1
This checkpoint inspection will also catch the defect (Gouged SiO2) LATER
CANDIDATE #2
Table 6: Metallization Process Flow (With Added Inspection Checkpoints)
36
Should a breakdown or failure of the WBE step occur, it is always better to detect the
deficiency earlier instead of later in the process line. NEC Electronics already performs its
metallization inspections at the metal and via layers. Analysis of the metallization flow reveals
that the via-layer inspection would provide quicker feedback against a potential WBE-related
failure versus an inspection at a subsequent metal layer further downstream in the flow.
Therefore, a new Gouged SiO2 monitoring metric using feature extraction data should come from
the via-layer inspection checkpoint for faster response times in the case of a failure at WBE.
To create a feature extraction metric at the Via-layer, a generous amount of defect data
was collected to characterize defects of both Gouged SiO2 defect types and non-Gouged SiO2
defect types. The KLA2367 is able to collect numerous metrics of every detected defect for a
given inspection layer, including the via-layer inspections. Shown below in Table #7 is some of
the feature extraction data regarding an inspected wafer at the #2-Via inspection step:[3]
Lot ID
Step ID
Lot #2854 2 VIA
Lot #2854 2 VIA
Lot #2854 2 VIA
Lot #2854 2 VIA
Lot #2854 2 VIA
Lot #2854 2 VIA
Lot #2854 2 VIA
Lot #2854 2 VIA
Lot #2854 2 VIA
Lot #2854 2 VIA
Lot #2854 2 VIA
Lot #2854 2 VIA
Lot #2854 2 VIA
Lot #2854 2 VIA
Lot #2854 2 VIA
Device ID
ENGREVAL
ENGREVAL
ENGREVAL
ENGREVAL
ENGREVAL
ENGREVAL
ENGREVAL
ENGREVAL
ENGREVAL
ENGREVAL
ENGREVAL
ENGREVAL
ENGREVAL
ENGREVAL
ENGREVAL
Wafer ID Slot ID Defect ID
12
15
64
12
15
65
12
15
66
12
15
67
12
15
68
12
15
69
12
15
70
12
15
71
12
15
72
12
15
73
12
15
74
12
15
75
12
15
76
12
15
77
12
15
78
Class ID (Manual)
Particle ON Layer
Particle ON Layer
Particle ON Layer
Particle ON Layer
Particle ON Layer
Particle ON Layer
Particle ON Layer
Particle ON Layer
Particle ON Layer
Particle ON Layer
Particle ON Layer
Particle ON Layer
Particle ON Layer
Particle ON Layer
Particle ON Layer
Test ID
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Area
0.773
0.011
0.065
0.027
4.915
0.111
0.096
0.143
0.028
0.016
0.965
0.077
0.051
0.106
0.014
Size Size-X Size-Y
1.919 1.76
1.919
0.16
0.16
0.159
0.639 0.48
0.639
0.319 0.16
0.319
4.319
4
4.319
0.799 0.64
0.799
1.12
1.12
0.639
0.799 0.64
0.799
0.32
0.32
0.319
0.32
0.32
0.159
2.239 1.44
2.239
0.64
0.64
0.639
0.64
0.64
0.479
0.8
0.8
0.639
0.319 0.16
0.319
Loc-X
5778.489
5769.049
5690.49
5678.49
5647.45
5614.57
5831.609
5805.129
5569.93
5336.33
33142.597
31869.72
32164.119
33530.597
34121.635
Loc-Y
16403.463
16341.945
16393.383
16401.703
16523.06
16450.102
16331.185
14747.554
14741.074
14826.112
32712.8
32240.85
32285.089
32233.97
31747.564
where,
Lot ID
Step ID
Device ID
Wafer ID
Slot ID
Defect ID
Class ID
Test ID
Area
Size
Size-X
Size-Y
Loc-X
Loc-Y
ClusNum
Loc-X in Die
Loc-Y in Die
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
Identification of Batch in Process Flow
Inspection Layer Step
Production or Engineering Level Test
Identification of Specific Wafer in Lot
Positition of Wafer in Cassette Containing Lot
The row data pertains to this defect number
Manual Classification Code from User
Which Test is Being Used (1, 2, or 3)
Area of Defect by KLA2367 assessment
Diameter of KLA defect (Algorithm)
X-coordinate length by KLA assessment
Y-coordinate length by KLA assessment
X-coordinate location (with respect to Wafer Center)
Y-coordinate location (with respect to Wafer Center)
Is the defect part of a cluster? If so, which numbered cluster?
X-coordinate location (with respect to Die Origin)
Y-coordinate location (with respect to Die Origin)
Table 7: Defect Table with Feature Extraction Data (Example)
ClusNum
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
Loc-X in Die
5705.952
5696.512
5617.953
5605.953
5574.913
5542.033
5759.072
5732.592
5497.393
5263.793
1870.76
597.883
892.282
2258.76
2849.798
Loc-Y in Die
5777.739
5716.221
5767.659
5775.979
5897.336
5824.378
5705.461
4121.83
4115.35
4200.388
6907.322
6435.372
6479.611
6428.492
5942.086
37
An analysis was performed on the seven-wafer DSA lot at the #2 Via-layer checkpoint
inspection to determine which feature extraction metrics were best suited for Gouged SiO2
monitoring. The Appendix contains the manually reviewed and classified defects of the sevenwafer DSA lot along with their feature extraction data. According to the defect data, Gouged SiO2
has some of the largest KLA-sizing (KLA-length, KLA-area, X-coordinate length, and Ycoordinate length) defect range values versus non-Gouged SiO2 defect types. Therefore, to
effectively monitor for potential Gouged SiO2 at Via-layer inspection checkpoints, a reasonable
sample of the largest defects for an inspected batch should be regularly reviewed.
Unfortunately, it is not possible to manually review every defect detected by the
KLA2367 at every via-inspection layer. Manual defect review for all detected defects in an
inspected batch is unreasonable simply due to the amount of total detected defects in an average
batch. It would exhaust Production resources and result in an unnecessary accrual of TAT (TurnAround-Time) for a batch.[4] From a Production personnel standpoint, a 50-defect review per
batch is manageable, and would not compromise the batch’s line-speed or Production resources.
5.6
Gouged SiO2 Feature Extraction Monitor Conclusions
Gouged SiO2 has some of the largest KLA-sizing (KLA-length, KLA-area, X-coordinate
length, and Y-coordinate length) defect range values. Therefore, to effectively monitor for
potential Gouged SiO2 at Via-layer inspection checkpoints, a reasonable sample of the largest
defects for an inspected batch should be regularly reviewed. A favorable sampling approach for
monitoring Gouged SiO2 is to review the largest 50 defects over a batch’s total defect amount.
Application of this method for the DSA revealed more than half of the sampled defects to be
Gouged SiO2. The feature extraction data “Appendix: Gouged SiO2 Feature Extraction Metrics”
suggests Gouged SiO2 to be more of a function of defect size versus defect location.
38
APPENDIX A
Gouged SiO2 Defect Progression (1):
Gouged SiO2 Defect Progression (2):
39
Gouged SiO2 Countermeasure Limited Production Yield Results (1):
Gouged SiO2 Countermeasure Limited Production Yield Results (2):
40
Gouged SiO2 Feature Extraction Metrics:
KLA Defect Area vs. Defect Classification
200
180
160
KLA Defect Area [um 2 ]
140
120
False Defect
Particle On Layer
100
Pattern Defect On Layer
80
Unclassified
Gouged SiO2
60
40
20
0
0
1
2
3
4
5
6
Classifcation (See Legend)
KLA Defect Size vs. Defect Classification
100
90
80
KLA Defect Size [um]
70
60
False Defect
Particle On Layer
50
Pattern Defect On Layer
40
Unclassified
Gouged SiO2
30
20
10
0
0
1
2
3
Classifcation (See Legend)
4
5
6
41
Gouged SiO2 Feature Extraction Metrics:
KLA Size X vs. Defect Classification
80
70
KLA Defect Size X [um]
60
50
False Defect
Particle On Layer
40
Pattern Defect On Layer
Unclassified
30
Gouged SiO2
20
10
0
0
1
2
3
4
5
6
Classifcation (See Legend)
KLA Size Y vs. Defect Classification
50
45
40
KLA Defect Size Y [um]
35
30
False Defect
Particle On Layer
25
Pattern Defect On Layer
20
Unclassified
Gouged SiO2
15
10
5
0
0
1
2
3
Classifcation (See Legend)
4
5
6
42
Gouged SiO2 Feature Extraction Metrics:
Location -X- vs. Defect Classification
150000
X Coordinate w/respect to Wfr CNT [um]
100000
50000
False Defect
Particle On Layer
0
0
1
2
3
4
5
6
Pattern Defect On Layer
Unclassified
Gouged SiO2
-50000
-100000
-150000
Gouged SiO2 is NOT a function
of -X- coordinate (with respect
to the wafer center).
Classifcation (See Legend)
Location -Y- vs. Defect Classification
150000
Gouged SiO2 is NOT a function
of -Y- coordinate (with respect
to the wafer center).
Y Coordinate w/respect to Wfr CNT [um]
100000
50000
False Defect
Particle On Layer
Pattern Defect On Layer
Unclassified
0
0
1
2
3
-50000
-100000
Classifcation (See Legend)
4
5
6
Gouged SiO2
43
Gouged SiO2 Feature Extraction Metrics:
Location -X- (Die Origin) vs. Defect Classification
9000
X Coordinate w/respect to Die Origin [um]
8000
7000
6000
False Defect
5000
Particle On Layer
Pattern Defect On Layer
4000
Unclassified
Gouged SiO2
3000
2000
1000
0
0
1
2
3
4
5
Classifcation (See Legend)
Gouged SiO2 is NOT a
function of -X- coordinate
(with respect
to the die origin
6
containing the defect).
Location -Y- (Die Origin) vs. Defect Classification
8000
Y Coordinate w/respect to Die Origin [um]
7000
6000
5000
False Defect
Particle On Layer
4000
Pattern Defect On Layer
Unclassified
3000
Gouged SiO2
2000
1000
0
0
1
2
3
Classifcation (See Legend)
4
5
Gouged SiO2 is NOT a
function of -Y- coordinate
(with respect
to the die origin
6
containing the defect).
44
Gouged SiO2 Feature Extraction Metrics:
For the largest 50 defects:
Gouged Defects  31 defects
Non-Gouged Defects  19 defect
Ratio = 31 / 50  62.0%
45
Gouged SiO2 Feature Extraction Metrics:
For the largest 50 defects:
Gouged Defects  26 defects
Non-Gouged Defects  24 defects
Ratio = 26 / 50  52.0%
46
Gouged SiO2 Feature Extraction Metrics:
For the largest 50 defects:
Gouged Defects  27 defects
Non-Gouged Defects  23 defects
Ratio = 27 / 50  54.0%
47
Gouged SiO2 Feature Extraction Metrics:
For the largest 50 defects:
Gouged Defects  26 defects
Non-Gouged Defects  24 defects
Ratio = 26 / 50  52.0%
48
BIBLIOGRAPHY
1. Groover, Michael P., Automation, Production Systems, and Computer-Integrated
Manufacturing. Upper Saddle River, NJ: Prentice Hall 2001
2. PTI Seminars, Inc., Three Metal Layer CMOS Device. Fenton, MO. PTI Seminars Inc.,
1992
3. Whitton, S., KLA21XX Operations Training Manual. Milpitas, CA. KLA-Tencor, 2006.
4.
Priest, John W., Engineering Design for Producibility and Reliability. New York, NY:
Marcel Dekker Inc. 1988
Image References
5. Obama Analog to Digital Conversion;
http://cache.gizmodo.com/assets/images/4/2009/01/analog-digital-barack2.jpg
6. Gray-Scale Spectrum;
http://edndoc.esri.com/arcobjects/9.2/java/java/library_reference/Display/bitmaps/GreySc
aleColorModelResize.png
7. Metal Layer Cross-Section;
http://www.tms.org/pubs/journals/JOM/0509/fig1.large.gif