Symbolic Boolean Manipulation
with
Ordered
Binary Decision Diagrams
Randal E. Bryant
Carnegie Mellon University
http://www.cs.cmu.edu/~bryant
Example Analysis Task
Logic Circuit Comparison

Do circuits compute identical function?
 Basic task of formal hardware verification
 Compare new design to “known good” design
A
T1
O1
C
B
–2–
T2
A
B
C
T3
O2
Solution by Combinatorial Search
Satisfiability Formulation

Search for input assignment
giving different outputs
Branch & Bound



Assign input(s)
Propagate forced values
Backtrack when cannot
succeed
Challenge

A
B
C
A
C
B
1
0
1
0
0
1
1
0
0 T3
1
0
1
Diff
0
1
0
T1
01
0
0
1
0
1
O1
0
1
T2
c
0
Must prove all assignments
fail
0
 Co-NP complete problem

–3–

Typically explore significant
fraction of inputs
Exponential time complexity
O2
0
b
1
1
a
1
1
00
Alternate Approach
Generate Complete Representation of Circuit Function

Compact, canonical form
A
T1
a
b
O1
C
B
T2
A
B
C
T3
c
0
a
O2
b
c
0


–4–

1
1
Functions equal if and only if representations identical
Never enumerate explicit function values
Exploit structure & regularity of circuit functions
Decision Structures
Truth Table
x1 x2 x3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Decision Tree
f
x1
0
0
0
1
0
1
0
1
x2
x3
0




–5–
x2
x3
0
0
x3
1
0
Vertex represents decision
Follow green (dashed) line for value 0
Follow red (solid) line for value 1
Function value determined by leaf value.
x3
1
0
1
Variable Ordering

Assign arbitrary total ordering to variables
 e.g., x1 < x2 < x3

Variables must appear in ascending order along all
paths
OK
x1
Not OK
x1
x1
x2
x2
x3
x3
x3
x1
x1
Properties


–6–
No conflicting variable assignments along path
Simplifies manipulation
Reduction Rule #1
Merge equivalent leaves
a
a
a
x1
x1
x2
x3
0
–7–
x2
x3
0
0
x2
x3
1
0
x3
1
0
x3
1
x2
x3
0
x3
x3
1
Reduction Rule #2
Merge isomorphic nodes
x
x
x
x
x
x
y
z
y
z
y
z
x1
x1
x2
x3
x2
x3
0
–8–
x3
x3
1
x2
x2
x3
x3
0
1
Reduction Rule #3
Eliminate Redundant Tests
x
y
y
x1
–9–
x1
x2
x2
x3
x3
0
1
x2
x3
0
1
Example OBDD
Initial Graph
Reduced Graph
x1
x1
x2
x3
0
0
0
x2
x2
x3
x3
1
0
x3
x3
1
(x1+x2)· x3
0
1
0
1
Canonical representation of Boolean function


For given variable ordering
Two functions equivalent if and only if graphs isomorphic
 Can be tested in linear time

– 10 –
Desirable property: simplest form is canonical.
Example Functions
Constants
Variable
0
Unique unsatisfiable function
1
Unique tautology
Typical Function
x1
x2

(x1  x2 )  x4

No vertex labeled x3


x4
0
– 11 –
1
x
0
Treat variable
as function
1
Odd Parity
x1
x2
x2
x3
x3
x4
x4
0
1
independent of x3
Many subgraphs shared
Linear
representation
Representing Circuit Functions
Functions


S3
Cout
All outputs of 4-bit adder
Functions of data inputs
a3
a3
b3 b 3
b3 b 3
a2
a2
a2
b2 b 2
b2 b 2
b2 b 2
a1
a1
a1
b1 b 1
b1 b 1
b1 b 1
a0
a0
a0
S2
A
B
A
D
D
Cout
S
S1
S0
Shared Representation
Graph with multiple roots
 31 nodes for 4-bit adder
 571 nodes for 64-bit adder
 Linear growth

– 12 –
b0
0
b0
1
Effect of Variable Ordering
(a1  b1)  (a2  b2 )  (a3  b3 )
Good Ordering
Bad Ordering
a1
a1
b1
a2
a2
a3
a2
a3
a3
b2
b1 b1 b1 b1
a3
b2 b2
b3
0
b3
1
Linear Growth
– 13 –
a3
0
1
Exponential Growth
Bit Serial Computer Analogy
K-Bit
Memory
xn … x2 x1
0 … 0 0
Bit-Serial
Processor
0
or
1
Operation


Read inputs in sequence; produce 0 or 1 as function value.
Store information about previous inputs to correctly deduce
function value from remaining inputs.
Relation to OBDD Size


– 14 –
Processor requires K bits of memory at step i.
OBDD has ~ 2K branches crossing level i.
Analysis of Ordering Examples
(a1  b1)  (a2  b2 )  (a3  b3 )
a1
a1
b1
a2
K=2
a2
a3
a2
a3
b2
b1 b1 b1 b1
a3
b2 b2
b3
0
– 15 –
a3 K = n
a3
b3
1
0
1
Selecting Good Variable Ordering
Intractable Problem

Even when problem represented as OBDD
 I.e., to find optimum improvement to current ordering
Application-Based Heuristics


Exploit characteristics of application
E.g., Ordering for functions of combinational circuit
 Traverse circuit graph depth-first from outputs to inputs
 Assign variables to primary inputs in order encountered
– 16 –
Dynamic Variable Reordering

Richard Rudell, Synopsys
Periodically Attempt to Improve Ordering for All BDDs


Part of garbage collection
Move each variable through ordering to find its best location
Has Proved Very Successful


– 17 –
Time consuming but effective
Especially for sequential circuit analysis
Dynamic Reordering By Sifting


Choose candidate variable
Try all positions in variable ordering
Best
Choices
 Repeatedly swap with adjacent variable

Move to best position found
a1
a1
a1
a1
b1
a2 a2
a2 a2
a2 a2
b1
a1
a3 a3 a3 a3
a3 a3 a3 a3
b1 b1
a2
a2
b2 b2 b2 b2
b2 b2 b2 b2
a3 a3
a3 a3
a3 a3
b1 b1
b3 b3
b2 b2
b2 b2
b2 b2
b3
b1
b3
b3
b3
0
– 18 –
1
0
1
•••
0
1
0
1
0
1
Swapping Adjacent Variables
Localized Effect


Add / delete / alter only nodes labeled by swapping variables
Do not change any incoming pointers
g
h
i
j
b1 b1 b1 b1
e
f
b2 b2
– 19 –
e
f
b2 b2
g
h
b2 b2
i
j
b1 b1
Sample Function Classes
Function Class
Best
Worst
Ordering Sensitivity
ALU (Add/Sub)
linear
exponential
High
Symmetric
linear
quadratic
None
Multiplication
exponential
exponential
Low
General Experience



– 20 –
Many tasks have reasonable OBDD representations
Algorithms remain practical for up to 100,000 node OBDDs
Heuristic ordering methods generally satisfactory
Lower Bound for Multiplication

Bryant, 1991
Integer Multiplier Circuit


n-bit input words A and B
2n-bit output word P
bn-1
b0
an-1
a0
•
•
•
•
•
•
•
•
•
Multn
•
•
•
p2n-1
pn
pn-1
Intractable
Function
p0
Boolean function

Middle bit (n-1) of product
Complexity

Exponential OBDD for all
possible variable
orderings
Actual Numbers


– 21 –
40,563,945 BDD nodes to
represent all outputs of
16-bit multiplier
Grows 2.86x per bit of
word size
Symbolic Manipulation with OBDDs
Strategy

Represent data as set of OBDDs
 Identical variable orderings


Express solution method as sequence of symbolic
operations
Implement each operation by OBDD manipulation
Algorithmic Properties



Arguments are OBDDs with identical variable orderings.
Result is OBDD with same ordering.
“Closure Property”
Contrast to Traditional Approaches

Apply search algorithm directly to problem representation
 E.g., search for satisfying truth assignment to Boolean expression.
– 22 –
If-Then-Else Operation
Concept

Basic technique for building OBDD from logic network or
formula.
I  T, E
I
X
T
0


1
MUX
E
Arguments I, T, E
Result

Implementation


– 23 –
Functions over variables X
Represented as OBDDs

OBDD representing
composite function
(I T)  (I  E)
Combination of depth-first traversal and dynamic
programming.
Worst case complexity product of argument graph sizes.
If-Then-Else Execution Example
Argument I
A1 a
Argument T
Argument E
A2,B2
c A6
1 A5
Optimizations

– 24 –
Dynamic programming
Early termination rules
A6,B2 A6,B5
c B5
B2 d
A3 d

A1,B1
a B1
1
A2 b
A4 0
Recursive Calls
B3 0
A3,B2
A5,B2 A3,B4
1 B4 A4,B3 A5,B4
If-Then-Else Result Generation
Recursive Calls
Without Reduction
A1,B1
C5 b
b
A6,B2 A6,B5

d
0
c
1
1
C4
c
1
C3 d
C1 0
1 C2
Recursive calling structure implicitly defines unreduced BDD
Apply reduction rules bottom-up as return from recursive calls
 Generates reduced graph
– 25 –
c
A5,B2 A3,B4
A4,B3 A5,B4

a C6
a
A2,B2
A3,B2
With Reduction
Restriction Operation
Concept


Effect of setting function argument xi to constant k (0 or 1).
Also called Cofactor operation (UCB)
Fx equivalent to F [x = 1]
Fx equivalent to F [x = 0]
x1
k
xi –1
F
F [xi =k]
xi +1
xn
Implementation


– 26 –
Depth-first traversal.
Complexity near-linear in argument graph size
Derived Operations


Express as combination of If-Then-Else and Restrict
Preserve closure property
 Result is an OBDD with the right variable ordering

Polynomial complexity
 Although can sometimes improve with special implementations
– 27 –
Derived Algebraic Operations

Other operations can be expressed in terms of If-Then-Else
If-Then-Else(F, G, 0)
And(F, G)
F  G, 0
F
F
X
X
G
1
MUX
G
0
0
If-Then-Else(F, 1, G)
Or(F, G)
F  1, G
F
F
X
X
1
1
MUX
G
G
– 28 –
0
Functional Composition
x1
x1
xi –1
1
x1
x1
xn
G
xi –1
xi +1
xn
F
xi +1
F
xn
x1
F [xi =G]
xi –1
0
xn
G
1
MUX
0
F
xi +1
xn


– 29 –
Create new function by composing functions F and G.
Useful for composing hierarchical modules.
Variable Quantification
x1
x1

xi –1
xi +1
1
F
xi –1
F
xi +1
xi F
xn
x1
xn
0
xi –1
F
xi +1
xn


– 30 –
Eliminate dependency on some argument through
quantification
Combine with AND for universal quantification.
Digital Applications of BDDs
Verification




Combinational equivalence (UCB, Fujitsu, Synopsys, …)
FSM equivalence (Bull, UCB, MCC, Siemens, Colorado,
Torino, …)
Symbolic Simulation (CMU, Utah)
Symbolic Model Checking (CMU, Bull, Motorola, …)
Synthesis



Don’t care set representation (UCB, Fujitsu, …)
State minimization (UCB)
Sum-of-Products minimization (UCB, Synopsys, NTT)
Test

– 31 –
False path identification (TI)
Generating OBDD from Network
Task:
Represent output functions of gate network as OBDDs.
Network
A
Evaluation
A  new_var ("a");
B  new_var ("b");
C  new_var ("c");
T1  And (A, 0, B);
T2  And (B, C);
Out  Or (T1, T2);
T1
B
Out
C
T2
Out
Resulting Graphs
T1
0
– 32 –
A
B
C
a
b
c
1
0
1
0
T2
a
b
b
1
0
a
b
c
1
0
b
c
1
0
1
Checking Network Equivalence
Task: Do two networks compute same Boolean function?
Method: Compute OBDDs for both networks and compare
Alternate Network
A
Evaluation
T1  Or (A, C);
O2  And (T1, B);
if (O2 == Out)
then Equivalent
else Different
T1
C
O2
B
O2
Resulting Graphs
a
T1
0
– 33 –
A
B
C
a
b
c
1
0
1
0
a
b
c
1
0
b
c
1
0
1
Finite State System Analysis
Systems Represented as Finite State Machines



Sequential circuits
Communication protocols
Synchronization programs
Analysis Tasks



State reachability
State machine comparison
Temporal logic model checking
Traditional Methods Impractical for Large Machines



– 34 –
Polynomial in number of states
Number of states exponential in number of state variables.
Example: single 32-bit register has 4,294,967,296 states!
Characteristic Functions
Concept

A  {0,1}n
 Set of bit vectors of length n

Represent set A as Boolean
function A of n variables
A
0 /1
 X  A if and only if A(X ) = 1
Set Operations
Union
– 35 –
Intersection
A
A
B
B
Symbolic FSM Representation
Nondeterministic FSM
Symbolic Representation
n1
00
n2
01
o1
10

11
o2
o2
0
1
o1 ,o2 encoded
old state
n1 , n2 encoded
new state
Represent set of transitions as function (Old, New)
 Yields 1 if can have transition from state Old to state New

– 36 –
Represent as Boolean function
 Over variables encoding states
Reachability Analysis
Task



Compute set of states reachable from initial state Q0
Represent as Boolean function R(S)
Never enumerate states explicitly
Given
old state
Compute

state
0/1
new state
Initial
R0
=
Q0
– 37 –
R
0/1
Breadth-First Reachability Analysis
00
01
R0
10


11
01
R2 R3
10
Ri – set of states that can be reached in i transitions
Reach fixed point when Rn = Rn+1
 Guaranteed since finite state
– 38 –
00
00
R1
Iterative Computation
Ri

old
new
Ri +1

Ri

Ri +1 – set of states that can be reached i +1 transitions
 Either in Ri
 or single transition away from some element of Ri
– 39 –
Example: Computing R1 from R0
n1
n1
R0
n2
n2
o1
00
1
o2
o2
0
1
0
0
 Old [R0(Old)  (Old, New)]
R1
n1
n1
n2
1
1
– 40 –
0
0
0
00
01
Symbolic FSM Analysis Example

K. McMillan, E. Clarke (CMU) J. Schwalbe (Encore Computer)
Encore Gigamax Cache System



Distributed memory multiprocessor
Cache system to improve access time
Complex hardware and synchronization protocol.
Verification


Create “simplified” finite state model of system (109 states!)
Verify properties about set of reachable states
Bug Detected


– 41 – 
Sequence of 13 bus events leading to deadlock
With random simulations, would require 2 years to generate
failing case.
In real system, would yield MTBF < 1 day.
What’s Good about OBDDs
Powerful Operations


Creating, manipulating, testing
Each step polynomial complexity
 Graceful degradation

Maintain “closure” property
 Each operation produces form suitable for further operations
Generally Stay Small Enough


Especially for digital circuit applications
Given good choice of variable ordering
Weak Competition


– 42 –
No other method comes close in overall strength
Especially with quantification operations
What’s Not Good about OBDDs
Doesn’t Solve All Problems



Can’t do much with multipliers
Some problems just too big
Weak for search problems
Must be Careful

Choose good variable ordering
 Critical effect on efficiency
 Must have insights into problem characteristics
 Dynamic reordering most promising workaround

Some operations too hard
 Must work around limitations
– 43 –
Relaxing Ordering Requirement
Challenge

Ordering is key to important properties of OBDDs
 Canonical form
 Efficient algorithms for operating on functions

Some classes of functions have no good BDD orderings
 Graphs grow exponentially in all cases

Would like to relax requirement
 but still preserve (most of) the algorithmic properties
Free Ordering


– 44 –
Gergov & Meinel, Sieling & Wegener
Slight relaxation of ordering requirement
Intractable OBDD Function Example
Rotator


Circular shift of data
Shift amount set by
control
0
Rotations 1
Control
Data
Rotate
Difficult Function

2
3
C
A
B
– 45 –
Rotate & compare
Rotate
=
OBDDs for Specific Rotations
1
– 46 –
R0
R1
R2
R3
b0
b0
b0
b0
a0 a0
a1 a1
a2 a2
a3 a3
b1
b1
b1
b1
a1 a1
a2 a2
a3 a3
a0 a0
b2
b2
b2
b2
a2 a2
a3 a3
a0 a0
a1 a1
b3
b3
b3
b3
a3
a0
a1
a2
0

1
0
1
0
1
Can choose good ordering for any fixed rotation
0
Forcing Single Ordering
R2
R0
b0
b0
a 2 a2
a2
b1
a2
b1
b1
b1
a 3 a3
a3
a3
a3
a3
a3
a3
a3
a3
b2
b2 b2
b 2 b2
b2 b2
b2 b 2
b 2 b2
b 2 b2
b2 b2
b2 b2
a0
a0
a0
b3
b3
a 0 a0
a0
b3
a0
a0
b3
b3
a1
1


– 47 –
b1
a0
a0
a1
0
1
0
Good ordering for one rotation terrible for another
For any ordering, some rotation will have exponential OBDD
Free BDDs
Rules


Variables may appear in any order
Only allowed to test variable once along any path
Not OK
OK
x1
x1
x2
x3
– 48 –
x3
x1
x2
x3
x1
x1
x2
x1
x1
Extraneous
path
Rotation Function Example
Advantage


Can select separate ordering for
each rotation
Good when different settings of
control call for different orderings of
data variables
Still Has Limitations

Representing output functions of
multiplier
 Exponential for all possible Free BDDs
 Ponzio, ‘95
– 49 –
c1
c0
c0
b0
b0
b0
b0
a 0 a0
a1 a1
a2 a 2
a3 a3
b1
b1
b1
b1
a 1 a1
a2 a2
a3 a 3
a0 a0
b2
b2
b2
b2
a 2 a2
a3 a3
a0 a 0
a1 a1
b3
b3
b3
b3
a3
a0
a1
a2
0
1
Making Free BDDs Canonical
Modified Ordering Requirement


For any given variable assignment, variables must occur in
fixed order
But can vary from one assignment to another
Algorithmic Properties Similar to OBDDs



Reduce to canonical form
Apply Boolean operation to functions
Test for equivalence, satisfiability, etc.
Some Operations Harder


– 50 –
Variable quantification and composition
But can restrict relevant variables to be totally ordered
Representing Free Ordering
Ordering Graph

Encodes assignment-dependent
variable ordering
Similar to BDD

Follow path according to assignment
OBDD is Special Case

Linear chain
Ordering Requirement

– 51 –
c1
All functions must be compatible with
single ordering graph
c0
c0
b0
b0
b0
b0
a0
a1
a2
a3
b1
b1
b1
b1
a1
a2
a3
a0
b2
b2
b2
b2
a2
a3
a0
a1
b3
b3
b3
b3
a3
a0
a1
a2
*
Practical Aspects of Free BDDs
Make Sense in Some Application Domain


Usage of bits varies with context
E.g., instruction set encodings
Must Determine Good Ordering Graph


Some success with heuristic methods
Ideally should be done dynamically
 Overwhelming degrees of freedom
Need to Demonstrate Utility on Real-Life Examples
– 52 –