4/28/05
By
Sudheer Vemula
Vemula: ELEC7250 1

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4/28/05
To perform delay test, two vectors, V1 and V2, have to be applied in sequence
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V1 – For initializing the output of a particular path under test
V2 – To observe the transition at the output
The problem is, if we want to apply two independent vectors to the scan chain of flip-flops, we will loose the initialization of the circuit.
This problem can be solved by inserting hold latches, with an additional HOLD signal, to each scan flip-flop.
 Area over head and delay in the signal path are increased.
Problem to be solved:- We need hold latches which have less area overhead and time delay.
Vemula: ELEC7250 2

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Two widely used delay test techniques are
Launch from Capture
 V2 is obtained from the response of V1
Launch from Shift
 V2 is one bit shift of V1
The vector V2 can’t be arbitrary in both the techniques.
PI
Operation of Enhanced Scan Hold Flip-Flop:
Scan
Out
HL
HL
Combinational
Circuit
CLK TC
SFF
SFF
CLK TC
Scan In
PO
Hold
4/28/05 Vemula: ELEC7250 3

D Q
HOLD/TC
HL
CLK
Q
HOLD
D
HOLD
Q
CLK
D Q
Q
M
U
X
MUX based Latch
CLK Q
Enhanced Scan Flip-Flop
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Both designs of hold latches add delay, which will affect the performance.
The area overhead is also present.
4/28/05 Vemula: ELEC7250 4

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This scheme is applied to the combinational logic present after the flip-flop (First Level Hold). TC
 The state of the combinational logic is held in response to the first pattern by gating the VDD and GND of the first level logic gates.
IN
 Disadvantage:-
 There might be leakage of charge due to the next level of logic gates
4/28/05 Vemula: ELEC7250
TC
V
DD
PMOS
Network
NMOS
Network
GND
OUT
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The output should be pulled to either VDD or
GND.
Add a latch.
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4/28/05
Another Disadvantage:-
Power dissipation during the normal operation.
Solution – Block the operation of the latch during the normal operation of the circuit.
TC
For Normal Operation TC = 1
For Hold Mode TC = 0
Vemula: ELEC7250
TC
6

ISCAS
89
Area Overhead
CKTs Percentage Percentage improvement over mux (flipflops/fanout ratio) improvement over enhanced scan
S298 -1.93(14/2.5) 7.28
S344 13.02(15/2.1) 20.88
S641 59.23(19/1.0) 62.91
S838 -22.31(32/3.0) -11.27
S1196 47.90(18/1.3) 52.61
S1423 11.85(74/2.2) 19.81
S5378 36.22(179/1.6) 41.98
S9234 14.01(211/2.1) 21.78
S13207 53.41(638/1.14) 57.62
S15850 36.09(534/1.57) 41.87
S35932 36.48(1728/1.6) 42.22
4/28/05
Delay Overhead
Percentage improvement over mux
77.01
65.15
68.54
71.25
81.75
72.74
73.65
82.70
86.27
80.64
81.19
Vemula: ELEC7250
50.92
63.52
71.26
55.83
65.21
68.39
78.18
Percentage improvement over enhanced scan
66.54
52.67
76.47
71.49
Decrease in Power
Dissipation
Percentage improvement over mux
Percentage improvement over enhanced scan
68.69
79.90
76.92
86.05
86.94
60.06
94.78
95.83
90.83
83.56
106.05
86.06
91.75
90.34
70.80
95.96
96.68
93.45
88.87
104.35
89.73
94.44
7

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The additional transistors in both PMOS and NMOS networks will increase the load at the output of the flip-flop, which will cause some additional delay compared to normal operation of the circuit without hold latch.
If fan outs are present at the output of the flip-flops, this will cause an increase the area and delay overhead.
 For smaller circuits with more fan outs, MUX based latch may give better results for some cases.
There is an average reduction of 33% in area overhead with an average improvement of 71% in delay overhead and 90% in power overhead during normal mode of operation compared to enhanced scan implementation.
4/28/05 Vemula: ELEC7250 8

[1] S. Bhunia, H. Mahmoodi, A. Raychowdhury, and K. Roy, ‘‘A Novel Low-overhead
Delay Testing Technique for Arbitrary Two-Pattern Test Application,’’ Proc.
Design, Automation and Test in Europe , pp. 1136-1141, 2005
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