Statistical Leakage and Timing
Optimization for Submicron
Process Variation
Yuanlin Lu and Vishwani D. Agrawal
ECE Dept. Auburn University
Auburn, AL 36849, USA
20th International Conference on VLSI Design
Bangalore, January 9, 2006
Jan. 2007
VLSI Design '07
1
Previous Work and Problem
Statement

Previous Work: Mixed integer linear program (MILP) for
optimum Dual-Vth and delay buffer assignment for





Minimum leakage
Glitch elimination
Overall delay specification
Lu and Agrawal, “Leakage and Glitch Minimization for PowerPerformance Tradeoff,” JOLPE, vol. 2, no. 3, pp. 1-10,
December 2006.
Problem Statement: to minimize the leakage and glitch
power (not included in this paper) considering process
variation.

Overall nominal delay, process variability and statistical timing
yield are specified.
Jan. 2007
VLSI Design '07
2
Motivation

Present trends in semiconductor technology:



Jan. 2007
Shrinking device dimensions.
Leakage power is a dominant contributor to the
total power consumption.
Large variations in process parameters can cause
a significant increase in leakage current because
of an exponential relation between the leakage
current and some key process parameters.
VLSI Design '07
3
Effects of Process Variation on
Leakage and Performance
S. Borkar, et al.,
Parameter variations
and impact on circuits
and microarchitecture,
DAC 2003.
too leaky
too slow
 0.18µ CMOS process
 20X leakage variation
30% clock frequency variation
 low leakage chips with too low frequency must be discarded
 high frequency chips with too high leakage must also be discarded
Jan. 2007
VLSI Design '07
4
Leakage in C432 Due to Global Process Variation
(3
σ = 15%, Spice simulation)
Probability
0.250
G lobalLeff+Tox+V th
G lobalLeff
G lobalTox
G lobalV th
0.200
0.150
0.100
0.050
0.
00
0.
40
0.
80
1.
20
1.
60
2.
00
2.
40
2.
80
3.
20
3.
60
4.
00
4.
40
4.
80
5.
20
5.
60
6.
00
0.000
Normalized Leakage Power
• Subthreshold is most sensitive to the variation in the effective gate length.
Jan. 2007
VLSI Design '07
5
Leakage in C432 Due to Local Process Variation
(3
σ = 15%)
P robability
1.000
LocalLeff+Tox+V th
LocalLeff
LocalTox
LocalV th
0.800
0.600
0.400
0.200
2.
40
2.
20
2.
00
1.
80
1.
60
1.
40
1.
20
1.
00
0.
80
0.
60
0.
40
0.
20
0.
00
0.000
N orm alized Leakage P ow er
• Subthreshold is most sensitive to the variation in the effective gate length.
Jan. 2007
VLSI Design '07
6
Leakage Distribution of C432 Due to the
Variation of Leff and Vth (3σ = 15%)
G lobalLeff
LocalLeff
0.400
0.300
0.200
0.100
G lobalVth
LocalVth
4.80
4.50
4.20
0.600
3.90
3.30
3.00
2.li70
P robabi
ty
2.40
2.10
1.80
1.50
1.20
0.90
0.60
0.30
N orm alized
Leakage P ow er
0.800
3.60
1.000
0.000
0.00
0.400
0.200
Jan. 2007
2.
20
2.
00
1.
80
1.
60
1.
40
1.
20
1.
00
0.
80
0.
60
0.
40
• Global variation has a
stronger effect on the
leakage distribution.
0.
20
0.000
0.
00
P robability
0.500
N orm alized Leakage P ow er
VLSI Design '07
7
Comparison of Leakage Distribution of C432
Due to Process Parameter Variations
nominal
(nW)
mean
(nW)
standard
dev. (nW)
std. dev.
/ mean
(meannominal)
/ nominal
max dev.
from nominal
(nW)
max dev.
/ nominal
local
906.9
1059.0
103.6
9.8%
16.8%
611.6
67.4%
global
906.9
1089.0
599.1
55.0%
20.1%
4652.0
513.0%
local
906.9
939.6
33.7
3.6%
3.6%
136.9
15.1%
global
906.9
938.6
199.9
21.3%
3.5%
795.8
87.7%
local
906.9
956.7
36.4
3.8%
5.5%
171.0
18.9%
global
906.9
964.4
219.8
22.8%
6.3%
1028.0
113.4%
local
906.9
1155.0
140.8
12.2%
27.4%
1044.0
115.1%
global
906.9
1164.0
719.4
61.8%
28.3%
5040.0
555.7%
process parameter
(3σ=15%)
Leff
Tox
Vth
Leff + Tox +
Vth
Jan. 2007
VLSI Design '07
8
Statistical Leakage Modeling
R. Rao, et al. “Parametric
Yield Estimation
Considering Leakage
Variability,” DAC 2004.
Jan. 2007
VLSI Design '07
9
Statistical Delay Modeling
Statistical – normal distribution
Deterministic




L

N
CV

T
eff
d
dd
ox


D

D

D
1

c

c

c
i
nom
,
i
i
1
i
2
i
3


L
T
N


V

V
eff
0
ox
0
d
0
dd
th


Vth  Vth0    X i
i
X i0  X i
X i0
Let

L

N

T
eff
d
ox
r

c

c

c
i
i
1
i
2
i
3
L
T
N
eff
0
ox
0
d
0
Mean
 D  Dnom,i
i
Standard Deviation
Diri Di
A. Davoodi and A. Srivastava, “Probabilistic Dual-Vth Optimization Under Variability,”
Proc. ISLPED, 2005.
Jan. 2007
VLSI Design '07
10
MILP Formulation (Basic)
(Deterministic vs. Statistical)
Deterministic Approach
Statistical Approach
Delay and subthreshold current of every
gate are assumed to be fixed and without
any effect of the process variation.
Treat delay, timing and leakage as
random variables with normal
distributions.
Basic MILP
Minimize the total leakage, keeping
the circuit performance unchanged.
Minimize
I

"
subnom
,i
i
i  gate number

T
Subject to T
" k  PO
POk
max
Jan. 2007
Basic MILP
Minimize the total nominal leakage,
keeping a certain timing yield (η).
Minimize E  I subnom,i " i  gate number
i
Subject to Pr TPOk  Tmax    " k  PO
VLSI Design '07
11
Real Variables of MILP



Delay of gate i, Di , is a Gaussian
random variable N(µDi , σDi)
Maximum signal arrival time at the
output of gate i, Ti , is a Gaussian
random variable N(µTi , σTi)
For gate i with input from gate j,
Ti ≥ Tj + Di , µTi ≥ µTj + µDi
A linear approximation used for σTi
Jan. 2007
VLSI Design '07
12
Integer Variables of MILP

For gate i, Xi = [0, 1]



Ileakage, i = ILi Xi + IHi (1 – Xi)
Di = DLi Xi + DHi (1 – Xi)
Where ILi , IHi , DLi , and DHi are
determined by Spice simulation of gate i
Jan. 2007
VLSI Design '07
13
Leakage Power Saving Due to Statistical
Modeling with Different Timing Yields (η)
Deterministic
Opti. (η = 100%)
Circuit
Statistical Optimization
(η = 99%)
Statistical Optimization
(η = 95%)
Optimize
d
Leakage
Power
(μW)
Run
Time
(s)
Optimized
Leakage
Power
(μW)
Extra
Power
Saving
Run
Time
(s)
Optimized
Leakage
Power
(μW)
Extra
Power
Saving
Run
Time
(s)
Circuit
Name
#
gates
Un-opt.
Leakage
Power
(μW)
C432
160
2.620
1.003
0.00
0.662
33.9%
0.44
0.589
41.3%
0.32
C499
182
4.293
3.396
0.02
3.396
0.0%
0.22
2.323
31.6%
1.47
C880
328
4.406
0.526
0.02
0.367
30.2%
0.18
0.340
35.4%
0.18
C1355
214
4.388
3.153
0.00
3.044
3.5%
0.17
2.158
31.6%
0.48
C1908
319
6.023
1.179
0.03
1.392
21.7%
11.21
1.169
34.3%
17.45
C2670
362
5.925
0.565
0.03
0.298
47.2%
0.35
0.283
49.8%
0.43
C3540
1097
15.622
0.957
0.13
0.475
50.4%
0.24
0.435
54.5%
1.17
C5315
1165
19.332
2.716
1.88
1.194
56.0%
67.63
0.956
64.8%
19.7
C7552
1045
22.043
0.938
0.44
0.751
20.0%
0.88
0.677
27.9%
0.58
29.2%
9.04
41.3%
4.64
14.07%
36.79
14.07%
36.44
Average of ISCAS’85 benchmarks
ARM7
15.5k
Jan. 2007
686.56
495.12
0.24
15.69
425.44
VLSI Design '07
425.44
14
Power-Delay Curves of Statistical and
Deterministic Approaches for C432
When performance is kept
unchanged:




Leakage power reduced
by deterministic approach
normalized to 1 unit.
0.65 unit and 0.59 unit
leakage power achieved
by statistical approach
with 99% and 95% timing
yields, respectively.
Lower the timing yield,
higher is power saving.
With a further relaxed Tmax ,
all three curves will give
more reduction in leakage
power.
Jan. 2007
1
0.9
Normalized Leakage Power

0.8
Deterministic LP
0.7
Statistical LP ( 99% Timing Yield)
0.6
Statistical LP ( 95% Timing Yield)
0.5
0.4
0.3
0.2
0.1
0
1
1.05
1.1
VLSI Design '07
1.15
1.2
1.25
1.3
Normalized Timing
1.35
1.4
1.45
1.5
15
Leakage Power Distribution with
Different Timing Yields (η)
Circuit
Deterministic Optimization
(η =100%)
Statistical Optimization
(η = 99%)
Statistical Optimization
(η = 95%)
Name
#
gates
Nominal
Leakage
(uW)
Mean
Leakage
(uW)
Standard
Deviation
(uw)
Nominal
Leakage
(uW)
Mean
Leakage
(uW)
Standard
Deviation
(uW)
Nominal
Leakage
(uW)
Mean
Leakage
(uW)
Standard
Deviation
(uW)
C432
160
0.907
1.059
0.104
0.603
0.709
0.074
0.522
0.614
0.069
C499
182
3.592
4.283
0.255
3.592
4.283
0.255
2.464
2.905
0.197
C880
328
0.551
0.645
0.086
0.430
0.509
0.080
0.415
0.491
0.079
C1355
214
3.198
3.744
0.200
3.090
3.606
0.202
2.199
2.610
0.175
C1908
319
1.803
2.123
0.170
1.356
1.601
0.116
1.140
1.341
0.127
C2670
362
0.635
0.750
0.078
0.405
0.473
0.046
0.395
0.461
0.043
C3540
1097
1.055
1.243
0.119
0.527
0.611
0.032
0.493
0.575
0.031
C5315
1165
2.688
3.128
0.165
1.229
1.420
0.088
1.034
1.188
0.067
C7552
1045
0.924
1.073
0.069
0.774
0.903
0.049
0.701
0.823
0.045
Average of ISCAS’85 benchmarks
Jan. 2007
0.138
0.105
VLSI Design '07
0.085
16
1.
00 0
E
2 . -0 7
00
E
3 . -0 7
00
E
4 . -0 7
00
E
5 . -0 7
00
E
6 . -0 7
00
E
7 . -0 7
00
E
8 . -0 7
00
E
9 . -0 7
00
E
1 . -0 7
00
E
1 . -0 6
10
E
1 . -0 6
20
E
1 . -0 6
30
E
1 . -0 6
40
E06
P robability
Leakage Power Distribution of
Optimized Dual-Vth C7552
0.250
0.200
Jan. 2007
C 7552_d
C 7552_p99
C 7552_p95
0.150
0.100
0.050
0.000
Leakage P ow er (m icro W )
VLSI Design '07
17
Conclusion



A mixed integer linear programming method
statistically minimizes leakage power and
eliminates glitch power in a dual-Vth design
under process variations.
Experimental results show 30% more leakage
power reduction by this statistical approach
compared with the deterministic approach.
Impacts of process variation on leakage power
and circuit performance are simultaneously
reduced when a small yield loss is allowed.
Jan. 2007
VLSI Design '07
18