Total Power Minimization in Glitch-Free
CMOS Circuits Considering Process
Variation
Yuanlin Lu
Intel Corporation, Folsom, CA 95630
Vishwani D. Agrawal
Department of ECE, Auburn University, Auburn, AL 36849
Jan 4-8, 2008
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Outline
Motivation
Problem Statement
Background
Proposed Technique

Statistical reduction of leakage and glitch
power under process variation
Results
Conclusion
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Motivation
Leakage power has become a dominant contributor to
the total power consumption

65nm, leakage is ~ 50% of total power consumption
Glitches consume 20%-70% of dynamic power
Variation of process parameters increases with
technology scaling



both average and standard deviation of leakage power increase
Glitch elimination technique of path balancing becomes
ineffective
Power yield and timing yield are degraded
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One Example: Process Variation
Effect on Leakage and Performance

 0.18um CMOS process
 20X leakage variation
 30% frequency
variation
 high frequency but too
leaky chips must be
discarded
 low leakage chips with
too low frequency must
also be discarded
too leaky
too slow
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[Ref] S. Borkar, et. al.,
DAC 2003.
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Comparison of Dynamic and Leakage Power
Variation of Un-Optimized C432 (1,000 Samples)
0.50
10% delay variation
20% delay variation
30% delay variation
0.45
0.40
Probability
0.35
0.30
Delay
variation
(meannominal)/
nominal
STD /
mean
10%
-0.05%
0.65%
20%
-0.07%
1.12%
30%
-0.16%
1.50%
Leff
variation
(meannominal)/
nominal
STD /
mean
10%
3.10%
6.1%
20%
8.75%
30.7%
30%
25.17%
112.9%
0.25
0.20
0.15
0.10
0.05
0.00
Probability
07
1.
05
1.
04
1.
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
03
1.
01
1.
00
1.
98
0.
97
0.
95
0.
94
0.
Normalized Dynamic Power
Nominal
10% Leff variation
20% Leff variation
30% Leff variation
0. 1. 1. 1. 1. 1. 2. 2. 2. 2. 3. 3. 3. 3. 4. 4. 4.
77 00 23 46 69 93 16 39 62 85 08 31 54 77 01 24 47
Normalized Leakage Power
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Process Variation and Dynamic Power
10% delay variation
20% delay variation
30% delay variation
0.40
0.30
0.20
0.10
Nominal
1.
07
1.
05
1.
04
1.
03
1.
01
1.
00
0.
98
0.
97
0.
95
0.00
0.
94
Dynamic power is normally much
less sensitive to the process
variation due to its approximately
linear relation to process
parameters.
Probability
0.50
Normalized Dynamic Power
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
1.
48
1.
44
1.
40
1.
36
1.
32
1.
28
1.
24
1.
20
1.
16
1.
12
1.
08
1.
04
10% delay variation
20% delay variation
30% delay variation
1.
00
Deterministic path balancing
becomes ineffective under
process variation because the
perfect hazard filtering conditions
can easily be corrupted with a
very slight variation in process
parameters.
Probability
C432 unoptimized for glitches
Normalized Dyanmic Power
C432 optimized by path balancing
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Previous Work and Problem Statement
Previous Work: Mixed integer linear program (MILP)
for optimum Dual-Vth and delay buffer assignment
for





Minimum leakage
Glitch elimination
Overall delay specification
Lu and Agrawal, “CMOS Leakage and Glitch Minimization
for Power-Performance Tradeoff,” JOLPE, vol. 2, no. 3,
pp. 1-10, December 2006.
Lu and Agrawal, “Statistical Leakage and Timing
Optimization for Submicron Process Variation,” Proc. 20th
Int. Conf. VLSI Design, Jan. 2007, pp. 439-444.
Problem Statement: Minimize leakage and glitch
power considering process variation.
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Techniques to Eliminate Glitches
?
path delay difference < gate inertial delay [1]
Hazard Filtering
(Gate/Transistor Sizing)


Increase gate inertial delay
Sizing gate to change gate delay
Path Balancing


1 →3
2
2
1.5
Decrease path delay difference
Insert delay elements on the
shorter delay signal path
2
1
2 →0.5
[1] V. D. Agrawal, International Conference on VLSI Design, 1997
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Glitch Elimination
For every gate i:
Without process variation: | Ti – ti | ≤ Di
With process variation: Prob{ | Ti – ti | ≤ Di } ≥ η
Inertial delay
Di
Signal arrival time window
[ ti, Ti]
Di = Xi Di(low Vth) + (1 – Xi) Di(high Vth), Xi = [0,1]
Leakage(i) = Xi Leajage(low Vth) + (1 – Xi) Leakage (high Vth)
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A Mixed Integer Linear Program
for Leakage and Glitch Power Reduction
Objective function (linear approximation):
Minimize {C1·Total leakage + C2·Total glitch
suppressing delays}
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MILP Formulation
(Deterministic vs. Statistical)
Deterministic Approach
Statistical Approach
The delay and subthreshold current of
every gate are assumed to be fixed and
without any effect of the process
variation.
Treat delay and timing intervals as random
variables with normal distributions;
leakage as random variable with
lognormal distribution
Basic MILP
Basic MILP
– Minimize total leakage while keeping
the circuit performance unchanged.
Minimize
I

i
Subject to
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" i  gate number
subnom
,i
" k  PO
T

T
POk
max
– Minimize total nominal leakage while
keeping a certain timing yield (η).
Minimize
I

" i  gate number
subnom
,i
i
Subject to PT  T    " k  PO
POk
max
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Delay Distribution without Considering
Process Variation
di = Ti-ti
Timing
window
Ti - ti
di <= Ti-ti
with glitch
di = Ti-ti
Timing
window
Ti - ti
di >= Ti-ti
glitch free
di >= Ti-ti
glitch free
Gate delay di
Gate delay di
Circuits unoptimized for glitch
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di <= Ti-ti
with glitch
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Circuits optimized for glitch
by path balancing
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Delay Distribution under Process Variation
di = Ti-ti
Timing
window
Ti - ti
di <= Ti-ti
with glitch
di = Ti-ti
Timing
window
Ti - ti
di >= Ti-ti
glitch free
di <= Ti-ti
with glitch
di >= Ti-ti
glitch free
Gate delay di
Gate delay di
Circuits unoptimized for glitch
Circuits optimized for glitch
by path balancing
Glitch power of unoptimized circuits is not sensitive to process variation;
Glitch power of circuits optimized by path balancing is sensitive to process variation.
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Technique of Enhancing the Resistance
of Glitch Power to Process Variations
di =Ti-ti
di <= Ti-ti
with glitch
Timing
window
Ti - ti
di >= Ti-ti
glitch free
Gate delay di
Leave a relaxed margin for process variation resistance in advance
Di  Ti  t i
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 D  3 D  ( T  3 T )  ( t  3 t )
i
i
i
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i
i
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Results for C432
Monte Carlo Simulation (15% local
process variation)
statistical µ=1.04 3σ/µ=2.82% (µ-N)/N=3.63%
determistic µ=1.14 3σ/µ=5.13% (µ-N)/N=13.53%
C432 optimized by the
statistical MILP with greater
emphasis on glitch power to
process variation (blue)
C432 optimized by the
deterministic MILP (Purple)
0.40
0.30
0.20
0.10
1.
23
1.
21
1.
19
Normalized Dynamic Power
statistical
N2=1.94 µ=2.25 σ/µ=10.24% (µ-N1)/N1=16.97%
deterministic N1=1.00 µ=1.17 σ/µ=6.64%
0.15
0.10
0.05
Normalized Leakage
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90
2.
75
2.
60
2.
45
15
00
85
70
55
40
30
2.
2.
2.
1.
1.
1.
1.
25
1.
10
1.
95
65
80
0.
0.
0.
50
0.00
0.
Subthreshold Leakage
(Spice simulation)
0.20
Probability
Dynamic Power
(logic simulation)
(µ-N2)/N2=15.22%
2.
1.
17
1.
15
1.
13
1.
11
1.
09
1.
07
1.
05
1.
03
1.
01
0.
99
0.
97
0.00
0.
95
Probability
0.50
Results of MILP: Leakage Power Distribution
of Optimized Dual-Vth C7552
0.25
0.20
C 7552_d
C 7552_p99
C 7552_p95
Probability
0.15
0.10
0.05
0.
0E
+
1. 00
0E
2. 07
0E
3. 07
0E
4. 07
0E
5. 07
0E
6. 07
0E
7. 07
0E
8. 07
0E
9. 07
0E
1. 07
0E
1. 06
1E
1. 06
2E
1. 06
3E
1. 06
4E
-0
6
0.00
Leakage Power (uW)
Mean and Standard Deviation of leakage power are reduced by the statistical method.
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Conclusion
Circuits optimized of glitch suppression can
be seriously degraded by process variation.
Overdesign (3σ variation) may reduce
sensitivity to process variation.
Statistical design (specified yields) can give
improved tradeoffs between leakage power,
glitch power and timing.
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Future Work
Iterative MILP
for dual-Vth design

Timing violations were found
The interdependency of delays of
gates was neglected for simplicity in
our MILP formulation.
gate delay

= 2
+
2
+
3
8.2ns = 2
+
3
+
3.2
7ns
1
2
FF
dual-Vthdesign
3
FF
8ns
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LVT design
If any timing violation is found, the
new delays for all LVT cells are
extracted from the current dual-Vth
design and the MILP formulation is
updated correspondingly. A different
optimal solution is then given by the
CPLEX solver with fewer timing
violations. We continue iterations until
all timing violations are eliminated.
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Thank You All !
Questions?
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