Algorithms for Estimating Number of
Glitches and Dynamic Power in CMOS
Circuits with Delay Variations
Jins Davis Alexander
Vishwani D. Agrawal
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
Presented at the IEEE Computer Society Annual Symposium on VLSI
Tampa, Florida, May 13-15, 2009
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Components of Power

Dynamic

Signal transitions
Logic activity
 Glitches



Short-circuit
Static

Leakage
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Ptotal = Pdyn + Pstat
= Ptran + P + Pstat
sc
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Power Per Transition
isc
R
VDD
Dynamic Power
Vo
Vi
= CLVDD2/2 + Psc
CL
R
Ground
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Number of Transitions
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Outline



Motivation and Problem Statement
Background
Contributions:
A New Dynamic Power Analysis Algorithm






Bounded Delays and Ambiguity Intervals
Maximum Transitions
Minimum Transitions
Simulation and Power Estimation
Experimental Results and Observations
Conclusion
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Problem Statement and Motivation

Problem - Estimate dynamic power consumed in a
CMOS circuit for:




A set of input vectors
Delays subjected to process variation (typical in
nanoscale technologies)
Challenge - Existing method, Monte Carlo
simulation, is expensive.
Find a lower cost solution.
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Background



Bounded delay model is used to address process
variations in logic level simulation and timing
analysis. See references in the paper.
We model delay uncertainties by assigning each
gate lower and upper bounds on its delay. These
are known as min–max delays.
The bounds are obtained by adding specified
process-related variation to the nominal gate
delay for the technology.
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References



J. D. Alexander, Simulation Based Power Estimation for Digital
CMOS Technologies, Master’s Thesis, Auburn University,
December 2008.
J. D. Alexander and V. D. Agrawal, “Computing Bounds
on Dynamic Power Using Fast Zero-Delay Logic
Simulation,” Proc. 41st IEEE Southeastern Symp. System
Theory, March 2009, pp. 107-112. Paper describes
simulation algorithm and results.
This paper: Theoretical foundation – theorems on
ambiguity propagation and maximum and minimum
transitions – make the fast zero-delay analysis possible.
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Ambiguity Intervals
•
•
•
•
IV
FV
EA
LS
EA
FV
LS
EA is the earliest arrival time
LS is the latest stabilization time
IV is the initial signal value
FV is the final signal value
EAsv=-∞
EAdv
LSsv=∞
LSdv
EAdv=-∞
EAsv
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IV
LSdv=∞
LSsv
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Propagating Ambiguity Intervals
through Gates
The ambiguity interval (EA,LS) for a gate output is determined
by:
•Ambiguity intervals of input signals.
•Pre-transition and Post-transition steady-state values.
•Min-Max gate delays.
(mindel, maxdel)
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Representative Formulae

To evaluate the output of a gate, we analyze
inputs i:
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Theorem 1: Propagating
Ambiguity Intervals

Ambiguity interval at a gate output is:
where the inertial delay of the gate is bounded as
(mindel, maxdel).
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Finding Number of Transitions
3
14
7
5
8
10
12
10 12
14
2
[mintran,maxtran]
[0,2]
3
EA
14
(mindel, maxdel)
LS
[0,4]
5
EA
1,3
17
6
EA
17
LS
LS
where mintran is the minimum number of transitions and
maxtran the maximum number of transitions.
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Theorem 2: Maximum Transitions


First upper bound: We calculate the maximum transitions (Nd)
that can be accommodated in the ambiguity interval given by the
gate delay bounds and the (IV,FV) output values.
Second upper bound: We take the sum of the input transitions
(N) as the output cannot exceed this. We modify this by :
N=N–k
where k = 0, 1, or 2 for a 2-input gate and is determined by the
ambiguity regions and (IV, FV) values of inputs.

The maximum number of transitions is lower of the two upper
bounds:
maxtran = min (Nd, N)
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Examples of maxtran (k = 0)
Nd = ∞
N=8
maxtran=min (Nd, N) = 8
Nd = 6
N=8
maxtran=min (Nd, N) = 6
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Example: maxtran With Non-Zero k
[n1 + n2 – k = 8 ] ,
[n1 = 6]
EAsv = - ∞
EA
LSdv = ∞
LS
where k = 2
EAdv LSsv
[n2 = 4]
EAsv = - ∞
EAdv
LSdv = ∞
LSsv
[6]
[6+4–2=8]
[4]
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Theorem 3: Minimum Transitions

First lower bound (Ns): Based on steady state values, i.e., 00,
11 as no transition and 01, 10 as a single transition.

Second lower bound (Ndet): The minimum number of
transitions that can occur in the output ambiguity region is the
number of deterministic signal changes that occur within the
ambiguity region and such that signal changes are spaced at time
intervals greater than or equal to the inertial delay of the gate.

The minimum number of transitions is the higher of the two
lower bounds:
mintran = max (Ns, Ndet)
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Example: mintran
EAsv = - ∞
EAdv
LSsv = ∞
LSdv
EAdv = - ∞
EAsv


EA
LS
d
LSdv = ∞
LSsv
(mindel, maxdel)
There will always be a hazard in the output as long
as
(EAsv – LSdv) ≥ maxdel
Thus in this case the mintran is not 0 as per the
steady state condition, but is 2.
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Power Analysis Algorithm


maxdel, mindel = nominal delay ± Δ%
Three linear-time passes for each input vector:



First pass: zero delay simulation to determine initial and final
values, IV and FV, for all signals.
Second pass: determines earliest arrival (EA) and latest
stabilization (LS) from IV, FV values and bounded gate
delays.
Third pass: determines upper and lower bounds, maxtran and
mintran, for all gates from the above information.
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Simulation Setup




Standard gate delay 100 ps.
Wire-load model used; gate proportional to fan–out.
The power distribution determined for 1000 random
vectors with a vector period of 10000 ps.
For each vector pair, 1000 sample circuits were
simulated.
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Maximum Power

Monte Carlo Simulation vs. Min-Max analysis for circuit C880.
100 sample circuits with + 20 % variation were simulated for
each vector pair (100 random vectors).
R2 is coefficient of
determination, equals
1.0 for ideal fit.
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Minimum Power
R2 is coefficient of
determination,
equals 1.0 for
ideal fit.
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Average Power
10
9
Monte Carlo average power (mW)
R2 = 0.9527
8
7
6
5
4
3
2
1
0
0
2
4
6
8
MIN - MAX m ean pow er (m W)
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R2 is coefficient
of determination,
equals 1.0 for
ideal fit.
23
C880: Monte Carlo vs. Bounded
Delay Analysis
80000
1000 Random Vectors, 1000 Sample Circuits
70000
Frequency
60000
50000
40000
30000
20000
10000
2.
13
7
2.
74
74
3.
35
79
3.
96
83
4.
57
88
5.
18
92
5.
79
96
6.
41
01
7.
02
05
7.
63
1
8.
24
14
8.
85
19
9.
46
23
10
.0
73
10
.6
83
11
.2
94
1.
52
65
0
Power (mW)
Monte Carlo Simulation
Bounded Delay Analysis
Min Power
(mW)
Max Power
(mW)
CPU Time
(secs)
Min Power
(mW)
Max Power
(mW)
CPU Time
(secs)
1.42
11.59
262.7
1.35
11.89
0.3
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C2670: Effect of Inertial Delay
Transition Statistics for high activity gate 1407 in c2670 for a
random vector pair. Histograms obtained from Monte Carlo
Simulations of 100 sample circuits.
min-max delay (7ps,12ps)
min-max delay (1ps,3ps)
45
60
30
25
20
15
10
5
mintran = 0
Frequency
35
50
Frequency
maxtran =1 0
40
40
mintran = 0
70
50
maxtran = 8

30
20
10
0
0
0
2
4
6
8
10
Num ber of Transitions
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0
2
4
6
8
Num ber of Transitions
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mintran = 0
60
min-max delay (11ps,33ps)
50
30
20
10
40
maxtran = 4
40
maxtran = 6
Frequency
50
min-max delay (8ps,24ps)
Frequency
60
mintran = 0
Effect of Inertial Delay…
30
20
10
0
0
0
2
4
0
6
Num ber of Transitions
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2
4
Num ber of Transitions
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Power Estimation Results

Circuits implemented using TSMC025 2.5V CMOS library , with standard size
gate delay of 10 ps and a vector period of 1000 ps. Min-Max values obtained
by assuming ± 20 % variation. The simulations were run on a UNIX
operating system using a Intel Duo Core processor with 2 GB RAM.
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Zero-Delay Vs. Event-Driven
Simulation
9000
8000
Execution Time (secs)
7000
6000
5000
Event driven simulation
4000
Min-Max Simulation
3000
2000
1000
0
357
514
880
1161 1667 2290 2416 3466
Number of gates
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Conclusion

Bounded delay model allows power estimation method with
consideration of uncertainties in delays.

Analysis has a linear time complexity in number of gates and is
an efficient alternative to the Monte Carlo analysis.

Monte Carlo versus min-max analysis: Reduced dimension of
sample space - Monte Carlo is over vectors and circuits; minmax is over vectors only.

Future work: (a) Find number of vectors for convergence of
result; (b) find probability distribution of power.
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