Dynamic Power Estimation With
Process Variation Modeled as
Min–Max Delay
Jins Davis Alexander
Vishwani D. Agrawal
Department of Electrical and Computer Engineering
Auburn University, AL 36849 USA
1
Motivation
 Dynamic power increases with glitch
transitions, which in turn are a
functions of gate delays.
 Process variation can influence delays
in a circuit, especially in nanoscale
technologies.
 Thus we need to access this
variability for effective estimation of
power.
2
Motivation…
 Many existing techniques depend on Monte
Carlo approaches which are time
consuming and CPU intensive.
 Bounded delay models are usually
considered to address process variations in
logic level simulation and timing analysis.
 We propose a dynamic power analysis
method that uses min–max delay model for
variations, eliminating the need for Monte
Carlo simulation.
3
Outline
Ambiguity Intervals.
Maximum Transition Estimation.
Minimum Transition Estimation.
Simulation Methodology.
Experimental Results and
Observations.
 Conclusion.





4
Circuit c880 Simulation
Monte Carlo Estimation (500 samples)
120
Monte Carlo Simulation
Min-Max Simulation
60
Min
Pwr
(mW)
Max
Pwr
(mW)
Exec.
Time
(secs)
Min
Pwr
(mW)
Max
Pwr
(mW)
Exec.
Time
(secs)
40
2.78
3.38
339.8
2.75
3.59
0.23
80
20
3.
38
3.
3
3.
24
3.
19
3.
14
3.
08
3.
03
2.
97
2.
92
2.
86
0
2.
78
Frequency
100
Power (mW)
5
Ambiguity Interval of Signals.
FV
IV
EA




IV
LS
FV
EA
LS
EA is the earliest arrival time
LS is the latest stabilization time
IV is the initial signal value
FV is the final signal value
EAsv=-∞
EAdv
LSsv=∞
LSdv
EAdv=-∞
EAsv
LSdv=∞
LSsv
6
Propagating Ambiguity Intervals
through Gates.
The ambiguity interval (EA,LS) for a gate output is determined
from the ambiguity intervals of input signals, their pre-transition
and post-transition steady-state values, and the min-max gate
delays.
(mindel, maxdel)
7
Theorem 1.
 For a gate output:
 EA = max {E1, E2} + mindel
 LS = min {L1, L2} + maxdel
 Where following are for all inputs i




E1 = max{EAdv(i)}
E2 = min{EAsv(i)}
L1 = min{LSsv(i)}
L2 = max{LSdv(i)}
8
Finding Number of Transitions.
3
14
7
5
8
10 12
10
12 14
2
[mintran,maxtran]
[0,2]
3
EA
14
LS
5
EA
[0,4]
(mindel, maxdel)
6
17
1,3
EA
LS
17
LS
9
Estimating Maximum Transitions


First upper bound: We calculate the maximum transitions (Nd)
that can be accommodated in the ambiguity interval given by
the gate delay bounds and the (IV,FV) output values.
Second upper bound: We take the sum of the input transitions
(N) as the output cannot exceed this. We modify this by :
N=N–k
.....(1)
where k = 0, 1, or 2 for a 2-input gate and is determined by
the ambiguity regions and (IV, FV) values of inputs.

Theorem 2: The maximum number of transitions is minimum
of the two upper bounds:
maxtran = min (Nd, N)
.....(2)
10
Example 1: Upper Bounds.
Nd = ∞
N=8
maxtran=min (Nd, N) = 8
Nd = 6
N=8
maxtran=min (Nd, N) = 6
11
Example 2: k in Second Upper
Bound.
[n1 + n2 – k = 8 ] ,
[n1 = 6]
EAsv = 
LSdv = 
EAdv
EA
LS
where k = 2
LSsv
[n2 = 4]
EAsv =  
LSdv = 
EAdv
[6]
LSsv
[6+4–2=8]
[4]
12
Estimating Minimum Transitions



First lower bound (Ns): Based on steady state values, i.e.,
00, 11 as no transitions and 01, 10 as a single
transition.
Second lower bound (Ndet): The minimum number of
transitions that can occur in the output ambiguity region is
the number of deterministic signal changes that occur within
the ambiguity region and such that signal changes are spaced
at time intervals greater than or equal to the inertial delay of
the gate.
Theorem 3: The minimum number of transitions is the
maximum of the two lower bounds:
mintran= max (Ns, Ndet)
...(3)
13
Example 3: Lower Bound.
EAsv =  
EAdv
EA
LSsv = 
LS
LSdv
d
LSdv = 
EAdv =  
EAsv
LSsv
 There will always be a hazard in the output
as long as
(EAsv – LSdv) ≥ d
Thus in this case the mintran is not 0 as
per the steady state condition, but is 2.
14
Simulation Methodology
 maxdel, mindel = nominal delay ± Δ%
 Three linear-time passes for each input vector:
 First pass: zero delay simulation to determine initial
and final values, IV and FV, for all signals.
 Second pass: determines earliest arrival (EA) and
latest stabilization (LS) according to Theorem 1.
 Third pass: determines upper and lower bound,
maxtran and mintran, for all gates according to
Theorems 2 and 3.
15
Experimental Results: Maximum
Power.

Monte Carlo Simulation v/s Min-Max analysis for circuit C880. 100
sample circuits with + 20 % variation were simulated for each
vector pair (100 random vectors). Each point is maximum power
for one vector-pair over 100 sample circuits.
Ideal, for infinite samples
Regression line
R2 is coefficient of
determination, equals
1.0 for ideal fit.
16
Results: Minimum Power.
Monte Carlo Simulation v/s Min-Max analysis for circuit
C880. 100 sample circuits with + 20 % variation were
simulated for each vector pair (100 random vectors). Each
point is minimum power for one vector-pair over 100 sample
circuits.
Ideal, for infinite samples
Regression line
R2 is coefficient of
determination,
equals 1.0 for
ideal fit.
17
Observing Effect of Inertial Delay.
Transition Statistics for high activity gate 1407 in c2670 for a
random vector pair. Histograms obtained from Monte Carlo
Simulations of 100 sample circuits.
min-max delay (1ps,3ps)
min-max delay (7ps,12ps)
50
20
15
10
5
50
Frequency
25
mintran = 0
30
maxtran =1 0
35
40
30
maxtran = 8
60
40
mintran = 0
70
45
Frequency

20
10
0
0
0
2
4
6
Num ber of Transitions
8
10
0
2
4
6
8
Num ber of Transitions
18
mintran = 0
min-max delay (11ps,33ps)
60
50
30
20
10
40
maxtran = 4
40
maxtran = 6
Frequency
50
min-max delay (8ps,24ps)
Frequency
60
mintran = 0
Further Increasing Inertial Delay.
30
20
10
0
0
0
2
4
Num ber of Transitions
6
0
2
4
Num ber of Transitions
19
Table of Results…
Circuits implemented using TSMC025 2.5V CMOS library , with standard
size gate delay of 10 ps . Min-Max values obtained by assuming ± 20 %
variation.
20
Execution Time Comparison.
9000
Execution Time (secs)
8000
7000
6000
5000
Event driven simulation
4000
Min-Max Simulation
3000
2000
1000
0
357
514
880 1161 1667 2290 2416 3466
Number of gates
21
Conclusion.
 We have used min–max delay model to
successfully develop a power estimation
method with consideration of process
variations.
 Linear time complexity in number of gates
and an efficient alternative to the Monte
Carlo analysis.
 Future work includes considering process
dependent variation in leakage as well as in
node capacitances.
22
Thank You.
23