Energy Source Lifetime Optimization for a
Digital System through Power Management
Manish Kulkarni
&
Vishwani D. Agrawal
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
7/16/2016
Manish Kulkarni & Vishwani Agrawal
1
Outline
• Voltage and Clock Management (DVFS)
– A typical battery-powered system
•
•
•
•
Battery simulation model
Battery lifetime and efficiency
Problem statement
Proposed method
– Determine operating voltage
– Determine minimum battery size
– Extend battery size to satisfy required lifetime
• Minimum energy mode operation
• Summary
• References
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Dynamic Voltage and Frequency Scaling (DVFS)
VDD
4.2 V to 3.5 V
Lithium- ion
Battery
DC – DC
Voltage
Converter
[9]
Decoupling
Capacitor
Electronic
System
GND
• Electronic systems are not always required to be in highest
performance mode
• Frequency and voltage can be varied
• Multi-voltage domains can be created which can use DVFS or
power shutdown
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Battery Simulation Model
Lithium-ion battery, unit cell capacity: N = 1 (400mAh)
Battery sizes, N = 2 (800mAh), N = 3 (1.2Ah), etc.
Ref: M. Chen and G. A. Rincón-Mora, “Accurate Electrical Battery Model Capable of
Predicting Runtime and I-V Performance,” IEEE Transactions on Energy Conversion, vol.
21, no. 2, pp. 504–511, June 2006.
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Spice Simulation of Battery Model
For a fixed current load
1008 Sec
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Battery Efficiency
• Consider a 1.2 Ah battery and IBatt = 3.6A
• Ideal lifetime = 1.2Ah/3.6A = 1/3 hour = 1200s
• Actual lifetime from simulation = 1008s
• Efficiency = (Actual lifetime)/(Ideal lifetime)
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=
1008/1200
=
0.84 or 84%
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Problem Statement
• Selecting a battery: Battery should be capable
of supplying power (current) for required
system performance (clock rate).
• Meeting the battery lifetime requirement;
lifetime is the interval between replacement
or recharge.
• Extend battery lifetime by DVFS. Find VDD and
clock rate for maximum lifetime.
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Proposed Method
Step 1: Determine the operating voltage based on required
performance.
Step 2: Determine minimum battery size for efficiency ≥
85%
Step 3: Increase battery size over the minimum size to
meet lifetime requirement.
Step 4: Determine a lower performance mode with
maximum lifetime.
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Determining Operating Voltage
• 200,000 copies of 32-bit Ripple Carry Adder
(RCA)
– Makes it ≈ 70 million gate circuit
• Consider a performance requirement of
200MHz clock, critical path delay ≤ 5ns.
• Circuit simulation gives,
VDD = 0.6V and IBatt = 477mA.
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Spice Simulation of System
477 mA
200 MHz
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Determine Minimum Battery Size
• For required current (477 mA) &
• Battery Efficiency ≥ 85 %
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We Choose
400 mAh Battery
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Battery Lifetime vs. VDD and Clock Rate
• A meaningful measure of the work done by the
battery is its lifetime in terms of clock cycles.
• For the range of voltages with correct operation,
i.e., VDD = 0.1V to 1.0V, we obtain circuit delay
and clock rate from HSPICE simulation.
• Calculate battery lifetime in clock cycles for each
VDD.
• Find VDD and clock rate for maximum battery
lifetime.
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Simulation of 400mAh Battery
• Over operating voltage range of 0.1 V to 1 V
1.80E+12
DVFS
1.60E+12
Number of Cycles per Recharge
Ideal Battery
Simulated Battery
1.40E+12
1.20E+12
Higher Circuit Speed,
Lower Battery Efficiency
1.00E+12
8.00E+11
6.00E+11
619 Giga Cycles
or
50 minutes
4.00E+11
Higher Battery Lifetime,
Lower Circuit Speed
2.00E+11
0.00E+00
0.00
0.20
0.40
0.60
0.80
1.00
1.20
VDD (Volts)
0.098
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0.560
3.860 23.00
88.00
199.0
325.0
Manish Kulkarni & Vishwani Agrawal
446.0
557.0
657.0
(MHz)
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Need Longer Battery Lifetime
• Suppose battery lifetime for the system is to be at
least 3 hours.
• For smallest battery, size N = 1 (400mAh)
IBatt = 477mA,
Efficiency ≈ 98%,
Lifetime = 0.98 x 0.4/0.477 = 0.82 hour
• For 3 hour lifetime, battery size
N = 3/0.82 = 3.65 ≈ 4.
• We should use a 4 cell (1600mAh) battery.
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Meeting Lifetime Requirement
7.00E+12
400 mAHr Battery
Number of Cycles per Recharge
6.00E+12
1600 mAHr Battery
5.00E+12
2540 Giga Cycles
or
205 min ( > 3 Hrs)
4.00E+12
3.00E+12
619 Giga Cycles
or
50 minutes
2.00E+12
1.00E+12
0.00E+00
0.00
0.20
0.40
0.60
0.80
1.00
1.20
VDD (Volts)
0.098
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0.560 3.860 23.00
88.00 199.0 325.0 446.0
Manish Kulkarni & Vishwani Agrawal
557.0 657.0
(MHz)
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Minimum Energy Operation
7.00E+12
400 mAHr Battery
Number of Cycles per Recharge
6.00E+12
1600 mAHr Battery
6630 Giga Cycles
or 476 hours
5.00E+12
4.00E+12
1660 Giga Cycles
or 119 hours
3.00E+12
2.00E+12
1.00E+12
0.00E+00
0.00
0.20
0.40
0.60
0.80
1.00
1.20
VDD (Volts)
0.098
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0.560 3.860 23.00 88.00 199.0 325.0 446.0 557.0 657.0
Manish Kulkarni & Vishwani Agrawal
(MHz)
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Summary
Battery size
VDD = 0.6V, 200MHz
N
mAh
Effici.
%
1
400
4
1600
VDD = 0.3V*, 3.86MHz
Lifetime
x103
9
Effici.
%
Lifetime
x103
seconds
X10 9
cycles
seconds
X10
cycles
98
3
619
100+
430
1660
100+
12.7
2540
100+
1717
6630
> two-times
1. Battery size should match the current need and satisfy the lifetime
requirement of the system:
a) Undersize battery has poor efficiency.
b) Oversize battery is bulky and expensive.
2. Minimum energy mode can significantly increase battery lifetime.
3. Another case of operation with a miniature (undersized) battery is
discussed in the paper.
* Operation of circuits in sub-threshold voltage range (below 200 mV) have been verified [10][11]
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References
1.
2.
3.
4.
5.
7.
8.
9.
10.
11.
M. Pedram and Q. Wu, “Design Considerations for Battery-Powered Electronics,” Proc. 36th Design
Automation Conference, June 1999, pp. 861–866.
L. Benini, G. Castelli, A. Macii, E. Macii, M. Poncino, and R. Scarsi, “A Discrete-Time Battery Model for
High-Level Power Estimation,” Proc. Conference on Design, Automation and Test in Europe, Mar. 2000, pp.
35–41.
M. Chen and G. A. Rincón-Mora, “Accurate Electrical Battery Model Capable of Predicting Runtime and I-V
Performance,” IEEE Transactions on Energy Conversion, vol. 21, no. 2, pp. 504–511, June 2006.
Simulation model: 45nm bulk CMOS, predictive technology model (PTM), http://ptm.asu.edu/
Simulator: Synopsys HSPICE,
www.synopsys.com/Tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Documents/hspice
ds.pdf
M. Kulkarni and V. D. Agrawal, “Matching Power Source to Electronic System: A tutorial on battery
simulation”, VLSI Design and Test Symposium, July 2010
M. Kulkarni, “Energy Source Lifetime Optimization for a Digital System through Power Management,”
Master’s Thesis, Dec 2010.
Joyce Kwong, Yogesh K. Ramadass, Naveen Verma, Anantha P. Chandrakasan, “A 65 nm SubMicrocontroller With Integrated SRAM and Switched Capacitor DC-DC Converter” IEEE Journal Of Solidstate Circuits, vol. 44, No. 1, January 2009, pp. 115-126
S. Hanson, B. Zhai, M. Seok, B. Cline, K. Zhou, M. Singhal, M. Minuth, J. Olson, L. Nazhandali, T. Austin, D.
Sylvester, and D. S. Blaauw, “Performance and variability optimization strategies in a sub-200 mV, 3.5
pJ/inst, 11 nW subthreshold processor,” in Symp. VLSI Circuits Dig., Jun. 2007, pp. 152–153.
B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, “A variation-tolerant sub-200mV 6-T subthreshold SRAM,”
IEEE Journal of Solid-State Circuits, October 2008, pp. 2338-2348
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