ELEC 5270/6270 Spring 2015
Low-Power Design of Electronic Circuits
Vishwani D. Agrawal
James J. Danaher Professor
Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu
http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr13/course.html
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
1

 A circuit is designed for certain function. Its design must allow the power consumption necessary to execute that function.
 Power buses are laid out to carry the maximum current necessary for the function.
 Heat dissipation of package conforms to the average power consumption during the intended function.
 Layout design and verification must account for
“hot spots” and “voltage droop” – delay, coupling noise, weak signals.
ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
Copyright Agrawal, 2007 2

Other chips
System inputs
Functional inputs
VLSI chip system
Functional outputs
System outputs
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
3

Test vectors:
Pre-generated and stored in
ATE
Packaged or unpackaged device under test (DUT)
DUT output for comparison with expected response stored in ATE
VLSI chip
Clock Power
Automatic Test Equipment (ATE):
Control processor, vector memory, timing generators, power module, response comparator
ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
Copyright Agrawal, 2007 4

 Functional inputs:
 Functionally meaningful signals
 Generated by circuitry
 Restricted set of inputs
 May have been optimized to reduce logic activity and power
 Test vectors:
 Functionally irrelevant signals
 Generated by software to test modeled faults
 Can be random or pseudorandom
 May be optimized to reduce test time; can have high logic activity
 May use testability logic for test application
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
5

VLSI chip in system operation
8-bit
1-hot
3-bit random vectors
Binary to decimal converter vectors
VLSI chip system
VLSI chip under test
High activity
8-bit test vectors from ATE
VLSI chip
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
6

 Given a set of test vectors
 Reorder vectors to minimize the number of transitions at primary inputs
01010101
00110011
00001111
11 transitions
Combinational circuit
(tested by exhaustive vectors)
01111000
Rearranged vector set 00110011 produces 7 transitions
00011110
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
7

Original tests:
V1 V2 V3 V4 V5
1 1 0 0 0
1 0 1 0 0
1 0 1 0 1
1 0 1 1 1
10 input transitions
V1
3
V4
3
2
1
V2
1
2
3
4
V5
1
V3
2
Reordered tests:
V1 V3 V5 V4 V2
1 0 0 0 1
1 1 0 0 0
1 1 1 0 0
1 1 1 1 0
5 input transitions
Traveling salesperson problem (TSP) finds the shortest distance closed path
(or cycle) to visit all nodes exactly once.
But, we need an open loop solution.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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0
V0
1
4
0
0
V1
3
0
V4
3
2
V2
1
2
3
V5
1
2
V3
0
 Add a node V0 at distance 0 from all other nodes.
 Solve TSP for the new graph.
 Delete V0 from the solution.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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

TSP has exponential complexity; good heuristics are available.
For other extensions:
 V. Dabholkar, S. Chakravarty, I Pomeranz and S.
Reddy, “Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test
Application,” IEEE Trans. CAD , vol. 17, no. 12, pp.
1325-1333, Dec. 1998.
 Typical average power saving:
 30-50%
 50-60% with vector repetition (to satisfy peak power)
 ? ? ? With inserted vectors (to satisfy peak power)
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
10

 A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data
Structures and Algorithms , Reading,
Massachusetts: Addison-Wesley, 1983.


E. Horowitz and S. Sahni, Fundamentals of
Computer Algorithms , Computer Science Press,
1984.
B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K.
R. Coombes, J. E. Osborn and G. J. Stuck, A
Guide to MATLAB for Beginners and
Experienced Users , Cambridge University
Press, 2006.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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 A combinational circuit is tested by a set of five vectors.
The test system initializes to the first vector 0000, which should be retained as the starting vector. Remaining vectors can be arbitrarily sequenced. Find the minimum energy test sequence. How much does your sequence save over the original sequence? The given test vector sequence is:
Vector number 
0
0
1
0
0
1
1
2
1
1
0
0
3
1
0
1
1
4
0
0
0
0
5
1
1
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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Designated start
2
1
4
5
2
2
1 2
1
2
4 3
4 3
3
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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Slack = 6
Edge weight = 4
1
2
1
Slack = 2
2
2 3 4 5
3
3
4
2
2
5 2
3
3
4
1
5
2
All searches terminate before reaching leaf node. Minimum path length = 6
Slack
= – 1
S = 0 S = 0
Terminate search when slack ≤ 0
Copyright Agrawal, 2007
4
4
ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
2
4
2
Greedy path
Length = 6 14

Paul Wray, “Minimize Test Power for Benchmark Circuit c6288 by Optimal Ordering of Vectors,” Class Project,
ELEC 5270, Spring 2009.
PowerPoint Presentation and Report: www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/course.html
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
15

Primary inputs
Scan enable
SE
Scan-in
SI
Copyright Agrawal, 2007
Primary outputs
Combinational logic
Scan-out
SO
D’
Scan flipflops
D
D
SI
ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
1
0
SE
DFF
SO
D’
16

 Two modes of operation:
 Normal mode
 Scan mode
 Three-step test application:
 Scan-in: sets inputs of logic in scan mode.
 Capture: captures logic outputs in normal mode.
 Scan-out: observes captured outputs in scan mode.
 Tests are non-functional; some tests may consume excess power and could have been intentionally avoided in functional mode.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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Functional transitions
Functional state transitions
S1
State transition
Comb. State input changes/clock
S5 S2
000 → 010 1
000 → 100 1
S4
State encoding
S1 = 000
S2 = 001
S3 = 010
S4 = 011
S5 = 100
S3
001 → 011
010 → 001
011 → 000
100 → 011
Av. transitions
1
2
2
3 (Peak)
1.667
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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Functional state transitions
S1
Functional transitions
State transition
Comb. State input changes/clock
000 → 001
S5 S2
1
000 → 100 1
S4
S3
011 → 010
001 → 011
1
1
Reduced power state encoding
S1 = 000
S2 = 011
S3 = 001
S4 = 010
S5 = 100
010 → 000
100 → 010
Av. transitions
1
2 (Peak)
1.167 ( – 30%)
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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Primary inputs
Combinational logic
Primary outputs
Scan transitions
State transition
Per clock state changes
Scan-out
100
100 → 010 2
FF=0
010 → 101 3
FF=0
Shift-out transition
101 → 010 3
Scan-in
010
FF=1
Shift-in transition
All transitions
8
Shift-in transitions = Σ (scan chain length – position of transition from scanin)
Shift-out transitions = Σ (position of transition from scanout)
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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Primary inputs
1
0
Combinational logic
1
1
Primary outputs
FF=0
Capture transitions: 3
Note that 101 is not a functional state in the reduced power state encoding.
FF=1
1
0
1
FF=0
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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0 1 0 1 0
1 0 1 0 0
0 1 0 0 0
1 0 0 0 0
Combinational
Logic
Scanout
0 1 0 1
Copyright Agrawal, 2007
10 transitions F4 0
F3
0
F2
0
F1
0
Initial state: 0000
Final state: 0101
ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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1 1 0 0
0 0 0 0 0
1 1 0 0 0
0 0 0 0 0
1 0 0 0 0
2 transitions
Combinational
Logic
F4
0
F3 0
F2 0
F1 0
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
Scanout
23

Next vector states
Copyright Agrawal, 2007
0
1
0
1
Combinational
Logic
1
1
1
0
3 transitions
F4
1
F3 0
F2 1
F1 0
ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
Scanout
24

0
1
0
1
Next vector states
1111 or 1100 or 0011
Select 1100
Copyright Agrawal, 2007
Combinational
Logic
1
1
1
0
3 transitions
F4
1
F3 1
F2 0
F1 1
Captured response
ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
Scanout
25

 Capture power can be reduced (How?):
 A vector generation problem
 Shift-in and shift-out power reduced by vector ordering and scan chain ordering:
 Construct a flip-flop node graph; edges weighted with shift in/shift out activity
 Find shortest distance Hamiltonian paths between all node pairs
 Select the path that minimizes shift power
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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N Scan flip-flops: F
1 through F
N
; M vectors: V
1 through V
M
F
1
→ F
2
· → · F j
· → ·F k
· → · F
N
F
1
→ F
2
· → · F j
· → · F k
· → · F
N
V
1
0 1 ··· 1 ··· 0 ··· 1 1 1 ··· 1 ··· 0 ··· 0
V
2
1 1 ··· 0 ··· 0 ··· 0 0 1 ··· 1 ··· 1 ··· 0
··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ···
I j
I k
O j
O
··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· k
V
M
0 0 ··· 1 ··· 1 ··· 0 1 0 ··· 0 ··· 0 ··· 1
Flip-flop states for test input Test output states
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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Copyright Agrawal, 2007
F w w jk
= Hamming(I j
, I k
) + Hamming(O j
, O k
) w
12
F
1 w
13
F
2
16 w
26 w
14 w
24 w
23 w
15 w
25
F
3
6 w
36 w
46 w
35 w
56 w
34
F
5
F
4 w
45
ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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



High complexity of Hamiltonian path finding requires use of heuristics.
Average power saving: ~30-50% logic, ~10-20% flip-flops.
Y. Bonhomme, P. Girard, Landrault, and S. C.
Pravossoudovtich , “Power Driven Chaining of Flip-Flops in
Scan Architectures,” Proc. International Test Conf ., 2002, pp. 796 –803.
Y. Bonhomne, P. Girard, L. Guiller, Landrault, and S. C.
Pravossoudovtich , “Power-Driven Routing-Constrained
Scan Chain Design,” J. Electronic Testing: Theory and
Applications, vol. 20, no. 6, pp. 647 –660, Dec. 2004.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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D
SI
SE
CK
DFF
SFF: Scan FF cell
SO
D’
D 1
SO
SI 0
DFF
CK
SE
SFF-GD: Gated data scan FF cell
D’
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
30

CK
SE
SO
D
SI
1
0
DFF
D’
SFF-GCKD: Gated clock and data scan FF cell
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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 1,000 random vectors
 Clock period = 50ns
 Technology: TSMC025
FF cell used
No. of gates
Dynamic power ( μW)
Logic Glitch Dyn.
Sh.Ck.
Leak.
( μW)
Clock
( μW)
FF 2958 77.9
17.5
95.4
14.1
(
FF
μW) (
Total
μW)
0.129
220.3
751.6
1081.5
19.5
101.3
13.9
0.130
220.3
751.7
1087.3
SFF 3137
SFF-
GD
SFF-
GCKD
3317
3675
Copyright Agrawal, 2007
81.8
85.1
89.9
19.8
56.8
104.9
146.7
15.0
23.9
0.132
220.3
751.7
1091.9
0.136
118.8
ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
33.2
322.7
32

 Mentor Graphics Fastscan, 98.9% coverage
 Clock period = 50ns
 Technology: TSMC025
FF cell used
No. of gates
Dynamic power ( μW)
Logic Glitch Dyn.
Sh.Ck.
Leak.
( μW)
Clock
( μW)
SFF
SFF-
GD
SFF-
GCKD
3137 356.8
3317 93.5
60.4
33.6
417.2
127.2
3675 146.8
241.9
388.7
26.2
7.7
61.9
(
FF
μW) (
Total
μW)
0.146
220.3
848.5
1512.4
0.150
220.3
850.7
1206.0
0.154
118.9
164.1
733.7
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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 J. D. Alexander, Simulation Based Power
Estimation For Digital CMOS
Technologies, Master’s Thesis, Auburn
University, Dept. of ECE, December 2008.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
34

Scanin
D Q
FF1
D Q
FF2
D Q
FFN
Scanout
Scan Enable
CLK
Copyright Agrawal, 2007
Multi-phase clock generator
ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
35

Linear feedback shift register (LFSR)
Pseudo-random patterns
BIST
Controller
Circuit under test (CUT)
Circuit responses
Multiple input signature register (MISR)
Clock
C. E. Stroud, A Designer’s Guide to Built-In Self-Test , Boston: Springer,
2002.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
36

R1 R2
Copyright Agrawal, 2007
M1 M2
R3
A datapath
R4
ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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LFSR1 LFSR2
M1
MISR1
M2
MISR2
T2: test for M2
T1: test for M1
Test time
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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R1 LFSR2
M1
MISR1
M2
MISR2
T1: test for M1
T2: test for M2
Test time
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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 Test resources: Typically registers and multiplexers that can be reconfigured as test pattern generators (e.g., LFSR) or as output response analyzers (e.g., MISR).
 Test resources (R1, . . .) and tests (T1, . . .) are identified for the system to be tested.
 Each test is characterized for test time, power dissipation and resources it requires.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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T1 T2 T3 T4 T5 T6
R1 R2 R3 R4 R5 R6 R7 R8 R9
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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



A bipartite graph (or bigraph ) is a graph whose vertices can be divided into two disjoint sets U and V such that every edge connects a vertex in U to one in V ; that is, U and V are independent sets.
Equivalently, a bipartite graph is a graph that does not contain any odd-length cycles.
A bipartite graph has no clique of size 3 or larger.
A bipartite graph can be colored with two colors (chromatic number = 2).
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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T1
( 2 , 100)
T6
( 1 , 100)
T2
( 1 ,10)
T5
( 2 , 10)
T3
( 1 , 10)
Power
Pmax = 4
Copyright Agrawal, 2007
Test time T4
( 1 , 5)
Tests that form a clique can be performed concurrently.
ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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




A clique is an undirected graph in which every vertex is connected to every other vertex .
A clique is a complete graph.
the maximum clique problem , is to find the largest clique in a graph.
Finding whether there is a clique of a given size in a graph (the clique problem) is NP-complete.
C. Bron and J. Kerbosch (1973): “Algorithm 457: Finding
All Cliques of an Undirected Graph.,” Communications of the ACM , vol. 16, no. 9. ACM Press: New York.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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



A directed graph is called strongly connected if there is a path from each vertex in the graph to every other vertex.
S trongly connected components ( SCC ) of a directed graph are its maximal strongly connected subgraphs. If each strongly connected component is contracted to a single vertex, the resulting graph is a directed acyclic graph (DAG).
T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein. Introduction to
Algorithms , Second Edition, MIT Press and McGraw-Hill, 2001, ISBN 0-
262-03293-7.
Finding SCCs, O(V+E)
45 Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .

TEST LENGTH, Li CLIQUE NO. i TEST NODES POWER, Pi
12
13
14
15
9
10
11
6
7
4
5
8
1
2
3
T1, T3, T5
T1, T3, T4
T1, T6
T1, T5
T1, T4
T1, T3
T2, T6
T2, T5
T3, T5
T3, T4
T1
T2
T3
T4
T5
10
10
100
10
10
5
10
100
100
100
100
100
100
100
100
10
1
2
1
1
1
3
2
2
3
2
4
3
3
5
4
3
46

 For each clique (test session) i, define:
 Integer variable, xi = 1, test session selected, or xi = 0, test session not selected.
 Constants, Li = test length, Pi = power.
 Constraints to cover all tests:

T1 is covered if x1+x2+x3+x4+x5+x6+x11 ≥ 1
 Similar constraint for each test, Tk
 Constraints for power: Pi × xi ≤ Pmax
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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 Objective function:
 Minimize
Σ
Li × xi all cliques
 Solution:
 x3 = x8 = x10 = 1, all other xi’s are 0
 Test session 3 includes T1 and T6
 Test session 8 includes T2 and T5
 Test session 10 includes T3 and T4
 Test length = L3 + L8 + L10 = 120
 Peak power = max {P3, P8, P10} = 3 (Pmax = 4)
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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RAM 2
Time=61
Power=241
RAM 3
Time=38
Power=213
Random logic 1, time=134, power=295
Random logic 2, time=160, power=352
ROM 1
Time=102
Power=279
ROM 2
Time=102
Power=279
RAM 4
Time=23
Power=96
RAM 1
Time=69
Power=282
Reg. file
Time = 10
Power=95
* Y. Zorian, “A Distributed Control Scheme for Complex VLSI Devices,”
Proc. VLSI Test Symp ., April 1993, pp. 4-9.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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1200
Reg. file
Power limit = 900
900
RAM 2
600 RAM 3
Random logic 1
ROM 1
300
RAM 1
Random logic 2
ROM 2
RAM 4
0 100 200 300 400
Test time 331
R. M. Chou, K. K. Saluja and V. D. Agrawal, “Scheduling Tests for VLSI
Systems under Power Constraints,” IEEE Trans. VLSI Systems , vol. 5, no. 2, pp. 175-185, June 1997.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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 Obtainable from ILP:

 {RL1, RL2, RAM2}
 {RAM3, RAM4, RF}
Test length =160
 {RAM1, ROM1, ROM2} Test length = 102
Test length = 38
 Total test length = 300
See, E. Larsson and C. P. Ravikumar , “Power-Aware
SystemLevel Test Planning,” Chapter 6, Section 6.4.1 in
Power-Aware Testing and Test Strategies for Low Power
Devices , P. Girard, N. Nicolici and X. Wen (Eds.),
Springer, 2010.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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
N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of
VLSI Circuits , Boston: Springer, 2003.
 E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization , Springer 2005.
 P. Girard, X. Wen and N. A. Touba , “Low-Power Testing,” in System on Chip Test Architectures , L.-T. Wang, C. E. Stroud and N. A.
Touba, editors, Morgan-Kaufman, 2008.
 N. Nicolici and P. Girard, Guest Editors, “Special Issue on Low
Power Test,” J. Electronic Testing: Theory and Applications, vol. 24, no. 4, pp. 325 –420, Aug. 2008.
 P. Girard, N. Nicolici and X. Wen, Power-Aware Testing and Test
Strategies for Low Power Devices , Springer, 2010.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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 Test time can be further reduced.
 References:

V. Sheshadri, V. D. Agrawal, and P. Agrawal, “Optimal
Power-Constrained SoC Test Schedules With
Customizable Clock Rates,” Proc. 25th IEEE
International System-on-Chip Conf.
, Sept. 2012, pp.
271 –276.
 V. Sheshadri, V. D. Agrawal, and P. Agrawal,
“Optimum Test Schedule for SoC with Specified Clock
Frequencies and Supply Voltages,” Proc. 26th
International Conf. VLSI Design , Jan. 2013, pp. 267 –
272.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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 Selectable clock frequency for each test session.
 Increase test clock frequency by factor F
 Test time divided by F
 Test power multiplied by F
 Proper choice of F for each session can optimize overall test time.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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 F j
= Frequency factor of j th session.
 Frequency factor limited by:
 P max
(Power Constraint)
 Max. speed of slowest core in session
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
55

Nominal clock
Copyright Agrawal, 2007
Slower clock
Faster clock
Prev. Best Optimal
Solution
ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
56


Each core’s max. clock rate decided by:
 Max. power limit of core (power constraint)
 Critical path delay (structural constraint)
 Both constraints also influenced by V
DD
.
 Power Constraint:
P core

V 2
DD
 f
 Structural constraint:
(known as Alpha power law) delay 

V
DD
V
DD
 V
TH
 
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .

57

DD
 Power constrained test:
As V
DD

, P core

T
CLK

, Test time

 Structure constrained test:
DD


CLK


 An optimal V
DD constraints.
can balance the two
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
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
DD
Experiments on ISCAS circuits show up to 62% improvement in test time.
Simulation and experimental test time plots for s298 *
* P. Venkataramani and V. D. Agrawal, “Reducing Test Time of Power Constrained Test by
Optimal Selection of Supply Voltage.”
Proc. 26 th Int. Conf. VLSI Design , Jan. 2013, pp. 273
–
278.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
59

Nominal clock
Saturates at 268.3 time units.
Prev. Best Optimal
Solution
Slower clock
Faster clock
Point A
• Cannot further reduce time by increasing Frequency factor.
ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
Copyright Agrawal, 2007 60

 At Point A:
 All test session frequencies are power constrained.
 Structural constraint limit >> power constraint limit.
 Nominal V
DD
= 1V, V
TH
= 0.5V, α = 1
 All cores can be tested at same voltage.
 Optimal V
DD same for all cores.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
61

 At Point A:
 All test session frequencies are power constrained.
 Structural constraint limit >> power constraint limit.
 Nominal V
DD
= 1V, V
TH
= 0.5V, α = 1
 All cores can be tested at same voltage.
 Optimal V
DD same for all cores.
Copyright Agrawal, 2007 ELEC6270 Spring 15, Lecture 6 Feb 27 . . .
62

DD
Structure constrained test
Power constrained test
Optimum V
DD
• 42% reduction in overall test time at optimal V
DD
.
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