ELEC 7770 Spring 2014
Advanced VLSI Design
Introduction to CAD Tools
Murali Dharan
08/01/2014
Course Objectives
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Learn basic ideas, concepts, theory and
methods.
Get experience with tools and techniques.
VLSI Design Methods
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Algorithms and architectures
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High-level and software techniques
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Gate and circuit-level methods
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Test Power
VLSI Simulation and Synthesis Tools
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QuestaSim
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LeonardoSpectrum
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ASIC and standard cell synthesis
DesignArchitect-IC
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Designing, compiling and simulating
designs
Schematic Capture
HSPICE
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Circuit simulation and verification
Some Power Analysis Tools and
Techniques
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PowerPlay
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PrimeTime PX
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Early stage power estimator
NanoSim
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Logic simulation based power estimator
Analog Circuit Engine (ACE) simulator
HSPICE
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SPICE Engine simulator (Industry standard)
EDA Tools Setup
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Download sample.bashrc file from Dr.
Nelson's website.
Rename file to .bashrc and save it on your
home directory.
http://www.eng.auburn.edu/~nelson/courses/
elec5250_6250/bashrc
QuestaSim
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Invoked using the command “vsim” at the
shell prompt
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Create HDL models (behavioral/structural)
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Can verify functionality using simulations
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Supports VHDL, Verilog, SystemC,
SystemVerilog
QuestaSim
QuestaSim Simulation steps
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After writing your HDL code, you should
compile it to check for errors and/or
inconsistencies.
If no errors are there, the compiled code will
be available in your “work” library.
To run the simulation, you can double click
the module in the “work” library.
LeonardoSpectrum Synthesis Steps
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Load technology library in the database
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Load the HDL file in the database
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Specify design constraints (timing, area)
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Compile/optimize design
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Generate technology specific HDL netlists
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Generate reports (area, timing)
Synthesis Steps
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Execute “spectrum -file filename.tcl” at the
shell prompt.
Tcl file contains the list of spectrum
commands which are executed sequentially.
Load Library
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load_library
/linux_apps/ADK3.1/technology/leonardo/tsmc0
35_typ
Available ADK libraries:
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tsmc035_typ (use this for projects)
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tsmc025_typ
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tsmc018_typ
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ami12_typ
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ami05_typ
Read HDL file
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read {file1.vhd folder/file2.vhd “file 3.vhd”} format VHDL (or verilog)
Syntax check and builds database (analyze)
Synthesize generic gates and black boxes
(elaborate)
Technology independent logic optimization
(pre_optimize)
Optimize design
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optimize <design> (default is current design)
Various switches can change the functionality
of the command
-effort quick (one pass) or standard (multiple
passes)
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-area, -delay, -auto (default)
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-hierarchy preserve, flatten or auto (default)
Save design to file
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write <filename>
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-silent (no warnings or messages)
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-format <format name>
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Verilog (.v)
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VHDL (.vhd)
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SDF (.sdf)
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EDIF (.edf)
Area report
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report_area [<filename>]
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-cell_usage
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-hierarchy
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-all_leafs
Delay report
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report_delay [<filename>]
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-longest_path
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-end_points
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-start_points
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-clock_frequency
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-critical_paths
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-from <start_points>
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-to <end_points>
Spectrum Documentation
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In shell prompt, type mgcdocs $LEO_DOCS
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User's Manual
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Reference Manual
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HDL Synthesis Manual
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Synthesis and Technology Manual
DesignArchitect-IC
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Invoked using the command “adk_daic” at the
shell prompt.
Loads the ADK libraries set up at the .bashrc
file.
Import the newly synthesized verilog netlist
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Go to File -> Import Verilog
Mapping file $ADK/technology/adk_map.vmp
DesignArchitect-IC
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Click Open Schematic, and point to the folder
where the design was saved.
Click Update LVS to create a SPICE netlist
which will be edited and used to run the
simulations.
The netlist will be named module.src.net and
will be in the design folder.
SPICE Netlist modifications
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The length and width parameters need to be
changed while keeping the ratios constant.
Change the L value to match the technology
file specifications.
Change the W values w.r.t the L values such
that the previous ratios are maintained.
Include the transistor technology
fileshttp://ptm.asu.edu
SPICE Netlist modifications
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A top level module needs to be created which
instantiates the primary inputs and outputs.
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X_modulename signal1 signal2...
modulename
.end command is added at the end of the
netlist which shows the end of SPICE netlist.
Useful SPICE Commands
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.inc <filename>
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.option post brief probe
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Post stores simulation results for analysis
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Brief doesn't print data file till .end
statement
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Probe limits output to .probe, .print, .plot,
and .graph statements
.param <parameter value>
SPICE Data Statements
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Independent DC Sources
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Vname N1 N2 Type Value
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Iname N1 N2 Type Value
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N1 is the positive terminal
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N2 is the negative terminal
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Type can be DC, AC or TRAN
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Value is the value of the source
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Names should prefix with V or I
SPICE Data Statements
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Dependent DC Sources
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Vname N1 N2 PWL (T1 V1 T2 V2 ...)
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Vname N1 N2 PULSE (V1 V2 Td Tr Tf PW
Period)
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Td – initial delay time
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Tr – rise time
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Tf – fall time
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PW – pulse width
SPICE Data Statements
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Entering a vector file
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.vec 'filename'
Vector Pattern definition
RADIX <1, 3 or 4> <1, 3 or 4>
Vname V1[MSB:LSB] V2[MSB:LSB]
IO I O B
Tunit ns
[Period]
Time1 signal1_value1 signal2_value1
SPICE Data Analysis
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.tran step PERIOD
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Step indicates at how many intervals in the
period the signals will be sampled.
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PERIOD means till what time the circuit will
be analyzed.
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.probe v(signal_name1) v(signal_name2)...
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.measure <tran> <variable> from <> to <>
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.print power
SPICE Simulations and Analysis
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HSPICE invoked by writing “hspice” in the
shell prompt.
Opens up a xterm window, then hspice is
invoked for a specific netlist.
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hspice -i inputfile.sp > output.out
Waveform viewer invoked using the
command “ezwave” from the shell prompt.
Used to view the waveforms of the probed
signals after the SPICE simulations.
NanoSim
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Invoked with “nsim” command at shell
prompt, then typing “nanosimgui” at the xterm
window.
Uses the same SPICE netlist used in
HSPICE.
HSPICE more accurate, but NanoSim faster
for larger circuits.
References
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Dr. Nelson's CAD Tools course
http://www.eng.auburn.edu/~nelson/courses/
elec5250_6250/
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HSPICE Reference Manual
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NanoSim Reference Manual
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Predictive Technology Model website
http://ptm.asu.edu