ELEC 7770
Advanced VLSI Design
Spring 2007
SOC Test Scheduling
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
vagrawal@eng.auburn.edu
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07
Spring 07, Jan 30
ELEC 7770: Advanced VLSI Design (Agrawal)
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Power Considerations in Design
 A circuit is designed for certain function. Its design must



allow the power consumption necessary to execute that
function.
Power buses are laid out to carry the maximum current
necessary for the function.
Heat dissipation of package conforms to the average
power consumption during the intended function.
Layout design and verification must account for “hot
spots” and “voltage droop” – delay, coupling noise, weak
signals.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Testing Differs from Functional
Operation
Other chips
System
inputs
System
outputs
VLSI chip
system
Functional inputs
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Functional outputs
ELEC 7770: Advanced VLSI Design (Agrawal)
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Basic Mode of Testing
Packaged or unpackaged
device under test (DUT)
DUT output for
comparison with
expected response
stored in ATE
VLSI chip
Test vectors:
Pre-generated
and stored in
ATE
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Clock
Power
Automatic Test Equipment (ATE):
Control processor, vector memory,
timing generators, power module,
response comparator
ELEC 7770: Advanced VLSI Design (Agrawal)
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Functional Inputs vs. Test Vectors
 Functional inputs:
 Functionally meaningful
 Test vectors:
 Functionally irrelevant
signals
 Generated by circuitry

 Restricted set of inputs

 May have been
optimized to reduce
logic activity and power
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

signals
Generated by software
to test faults
Can be random or
pseudorandom
May be optimized to
reduce test time; can
have high logic activity
May use testability logic
for test application
ELEC 7770: Advanced VLSI Design (Agrawal)
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An Example
VLSI chip in system operation
3-bit random
vectors
Binary to
decimal
converter
8-bit
1-hot
VLSI chip
vectors
system
VLSI chip under test
High activity
8-bit
test vectors
from ATE
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VLSI chip
ELEC 7770: Advanced VLSI Design (Agrawal)
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Reducing Comb. Test Power
1
V1 V2 V3 V4 V5
1 1 0 0 0
1 0 1 0 0
1 0 1 0 1
1 0 1 1 1
10 input transitions
V1
3
4
V2
3
3
2
V4
2
1
V3
1
V5
2
Traveling salesperson problem (TSP): Find the shortest distance
closed path (or cycle) to visit all nodes exactly once.
V1 V3 V5 V4 V2
1 0 0 0 1
5 input transitions
1 1 0 0 0
1 1 1 0 0
1 1 1 1 0
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Open-Loop TSP
1
3
V1
0
V0
0
0
0
2
3
V4
4
V2
2
1
3
V3
1
V5
2
0
 Add a node V0 at distance 0 from all other nodes.
 Solve TSP for the new graph.
 Delete V0 from the solution.
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Traveling Salesperson Problem
 A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data

Structures and Algorithms, Reading,
Massachusetts: Addison-Wesley, 1983.
E. Horowitz and S. Sahni, Fundamentals of
Computer Algorithms, Computer Science Press,
1984.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Scan Testing
Primary
inputs
Primary
outputs
Combinational
logic
Scan-out
SO
Scan enable
SE
Scan-in
SI
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Scan
flipflops
D
D
SI
ELEC 7770: Advanced VLSI Design (Agrawal)
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0
SO
mux
D’
SE
DFF
D’
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Example: State Machine
Functional transitions
S1
S5
S4
S2
S3
Reduced power state encoding
S1 = 000
S2 = 011
S3 = 001
S4 = 010
S5 = 100
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State transition
Comb. Input
changes
000 → 001
1
000 → 100
1
011 → 010
1
001 → 011
1
010 → 000
1
100 → 010
2
ELEC 7770: Advanced VLSI Design (Agrawal)
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Scan Testing of State Machine
Primary
inputs
Combinational
logic
Primary
outputs
Scan-out
100
FF=0
FF=0
FF=1
Test transitions
State
transition
Comb.
Input
changes
100 → 010
2
010 → 101
3
101 → 010
3
Scan-in
010
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Low Power Scan Flip-Flop
SO
mux
D
SI
D
DFF
1
D’
SI
0
mux
SO
DFF
D’
SE
SE
Scan FF cell
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Low power scan FF cell
ELEC 7770: Advanced VLSI Design (Agrawal)
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Built-In Self-Test (BIST)
Linear feedback shift register (LFSR)
BIST
Controller
Pseudo-random patterns
Circuit under test (CUT)
Circuit responses
Multiple input signature register (MISR)
Clock
C. E. Stroud, A Designer’s Guide to Built-In Self-Test, Boston: Kluwer
Academic Publishers, 2002.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Test Scheduling Example
R1
R2
M1
M2
R3
R4
A datapath
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ELEC 7770: Advanced VLSI Design (Agrawal)
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BIST Configuration 1: Test Time
M1
MISR1
LFSR2
M2
Test power
LFSR1
T2: test for M2
T1: test for M1
MISR2
Test time
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ELEC 7770: Advanced VLSI Design (Agrawal)
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BIST Configuration 2: Test Power
M1
MISR1
LFSR2
M2
Test power
R1
T1: test for M1
T2: test for M2
MISR2
Test time
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Testing of MCM and SOC
 Test resources: Typically registers and multiplexers


that can be reconfigured as test pattern generators
(e.g., LFSR) or as output response analyzers (e.g.,
MISR).
Test resources (R1, . . .) and tests (T1, . . .) are
identified for the system to be tested.
Each test is characterized for test time, power
dissipation and resources it requires.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Resource Allocation Graph
T1
R1
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R2
T2
R3
T3
R4
T4
R5
T5
R6
ELEC 7770: Advanced VLSI Design (Agrawal)
R7
T6
R8
R9
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Test Compatibility Graph (TCG)
T1
(2, 100)
T6
(1, 100)
T2
(1,10)
T5
(2, 10)
T3
(1, 10)
Power
Pmax = 4
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Test time
T4
(1, 5)
Tests that form a
clique can be performed
concurrently.
ELEC 7770: Advanced VLSI Design (Agrawal)
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Test Scheduling Algorithm
 Identify all possible cliques in TCG:

 C1 = {T1, T3, T5}
 C2 = {T1, T3, T4}
 C3 = {T1, T6}
 C4 = {T2, T5}
 C5 = {T2, T6}
Break up clique sets into power compatible sets
(PCS), that satisfy the power constraint.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Test Scheduling Algorithm . . .
 PCS (Pmax = 4), tests within a set are ordered for
decreasing test length:
 C1 = {T1, T3, T5} → (T1, T3), (T1, T5), (T3, T5)
 C2 = {T1, T3, T4} → (T1, T3, T4)
 C3 = {T1, T6} → (T1, T6)
 C4 = {T2, T5} → (T2, T5)
 C5 = {T2, T6} → (T2, T6)
 Expand PCS into subsets of decreasing test lengths.
Each subset is an independent test session, consisting
of tests that can be concurrently applied.
 Select test sessions to cover all tests such that the
added time of selected sessions is minimum.
Spring 07, Jan 30
ELEC 7770: Advanced VLSI Design (Agrawal)
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TS Algorithm: Cover Table
Test sessions
T1
(T1, T3, T4)
X
(T1, T5)
X
(T1, T6)
X
(T2, T6)
T2
(T3, T4)
T4
X
X
T6
X
X
X
100
X
100
X
100
X
10
X
10
X
10
X
X
Length
100
X
(T5)
(T4)
T5
X
(T3, T5)
(T2, T5)
T3
10
5
Selected sessions are (T3,T4), (T2, T5) and (T1, T6). Test time = 120.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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A System Example: ASIC Z*
RAM 2
Time=61
Power=241
ROM 1
Time=102
Power=279
RAM 3
Time=38
Power=213
ROM 2
Time=102
Power=279
Random logic 1, time=134, power=295
Random logic 2, time=160, power=352
RAM 4
Time=23
Power=96
RAM 1
Time=69
Power=282
Reg. file
Time = 10
Power=95
*Y. Zorian, “A Distributed Control Scheme for Complex VLSI Devices,”
Proc. VLSI Test Symp., April 1993, pp. 4-9.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Test Scheduling for ASIC Z
1200
Reg. file
Power limit = 900
Power
900
600
RAM 2
RAM 3
Random logic 1
ROM 1
300
RAM 1
Random logic 2
ROM 2
RAM 4
0
200
300
400
Test time
331
•R. M. Chou, K. K. Saluja and V. D. Agrawal, “Scheduling Tests for VLSI
Systems under Power Constraints,” IEEE Trans. VLSI Systems, vol. 5,
no. 2, pp. 175-185, June 1997.
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References
 N. Nicolici and B. M. Al-Hashimi, Power
Constrained Testing of VLSI Circuits, Boston:
Kluwer Academic Publishers, 2003.
E. Larsson, Introduction to Advanced Systemon-Chip Test Design and Optimization, Springer
2005.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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