ELEC 5270/6270 Spring 2009
Low-Power Design of Electronic Circuits
Power Analysis and Process Variation
Vishwani D. Agrawal
James J. Danaher Professor
Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
vagrawal@eng.auburn.edu
http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/course.html
Copyright Agrawal, 2009
ELEC5270-001/6270-001 Spr 09, Lecture 6
1
Process Variation in Nanoscale Devices
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Nanoscale device have dimensions smaller than 100
nm, typically, 65nm, 45nm, 32nm, 22nm, etc.
As geometries become closer to molecular dimensions,
percentage random variation in parameters become
large.
Affected physical parameters: transistor width (W) and
length (L), interconnect width and spacing, doping level.
Affected electrical characteristics: on and off resistances
of transistors, threshold voltage and leakage current,
capacitances.
Major influence on gate delays, ±20%, or more.
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ELEC5270-001/6270-001 Spr 09, Lecture 6
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Dynamic Power and Process Variation




Dynamic power increases with glitch
transitions, which are functions of gate
delays.
Process variation can influence delays in a
circuit, especially in nanoscale technologies.
Monte Carlo simulation used to address the
variation is time consuming and expensive.
Bounded delay models are usually
considered to address process variations in
logic level simulation and timing analysis.
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References
Simulation:
 S. Chakraborty and D. L. Dill, “More Accurate Polynomial-Time MinMax Timing Simulation,” Proc. 3rd International Symp. Advanced
Research in Asynchronous Cir. and Syst., Apr. 1997, pp. 112-123.
 J. W. Bierbauer, J. A. Eiseman, F. A. Fazal, and J. J. Kulikowski,
“System Simulation With MIDAS,” AT&T Tech. J., vol. 70, no. 1, pp.
36–51, Jan. 1991.
 S. Bose, H. Grimes, and V. D. Agrawal, “Delay Fault Simulation With
Bounded Gate Delay Model,” Proc. International Test Conf., 2007, pp.
23–28.
Timing anlysis:
 S. Chakraborty, D. L. Dill, and K. Y. Yun, “Min-Max Timing Analysis
and an Application to Asynchronous Circuits,” Proc. IEEE, vol. 87, no.
2, pp. 332–346, Feb. 1999.
Delay fault testing:
 H. Grimes, Reconvergent Fanout Analysis of Bounded Gate Delay
Faults, Master’s thesis, Auburn University, Dept. of ECE, Aug. 2008.
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ELEC5270-001/6270-001 Spr 09, Lecture 6
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Problem Statement

Given a set of vectors (random or
functional), determine the range of
dynamic power consumption for
specified bounds on delay variation.
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Power Analysis Methods

Monte Carlo simulation:
 R.
Burch, F. Najm, P. Yang, and T. Trick,
“McPOWER: A Monte Carlo Approach to Power
Estimation,” Proc. IEEE/ACM International
Conference on Computer-Aided Design, pp. 90–
97, Nov 1992.

Bounded-delay analysis:
 J.
D. Alexander, Simulation Based Power
Estimation for Digital CMOS Technologies,
Master’s thesis, Auburn University, Dept. of ECE,
Dec. 2008.
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ELEC5270-001/6270-001 Spr 09, Lecture 6
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C880: Monte Carlo Simulation
80000
1000 Random Vectors, 1000 Sample Circuits
± 20% random delay variation
70000
Frequency
60000
50000
40000
30000
20000
10000
2.
13
7
2.
74
74
3.
35
79
3.
96
83
4.
57
88
5.
18
92
5.
79
96
6.
41
01
7.
02
05
7.
63
1
8.
24
14
8.
85
19
9.
46
23
10
.0
73
10
.6
83
11
.2
94
1.
52
65
0
Power (mW)
Copyright Agrawal, 2009
Min Power
(mW)
Max Power
(mW)
CPU Time
(secs)
1.42
11.59
262.7
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Bounded Delay Model
Model delay uncertainties by assigning
each gate a lower and an upper bound on
delay, also known as min-max delay.
 The bounds can be obtained by adding
specified process-related variation to the
nominal gate delay for the technology.
 In this model, intervals of signal
uncertainties are defined at the output of
each gate.

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Ambiguity Delay Intervals
IV
FV
EA
•
•
•
•
IV
LS
FV
EA
LS
EA is the earliest arrival time
LS is the latest stabilization time
IV is the initial signal value
FV is the final signal value
EAsv=-∞
LSsv=∞
EAdv
LSdv
EAdv=-∞
LSdv=∞
EAsv
Copyright Agrawal, 2009
mindel,
maxdel
?
LSsv
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Sensitizing and Driving Values
Relative to Gate a Signal Feeds Into
Earliest possible termination
of sensitization value
EAsv=-∞
EAdv
Sensitizing
value (sv)
EAdv=-∞
EAsv
LSsv=∞
LSdv
mindel,
maxdel
LSsv
Driving value (dv)
?
LSdv=∞
Definite termination of
sensitization value
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Propagating Ambiguity Intervals
through Gates
The ambiguity interval (EA,LS) for a gate output is determined
from the ambiguity intervals of input signals, their pretransition and post-transition steady-state values, and the
min-max gate delays.
(mindel, maxdel)
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Summarize Input Signals

To evaluate the output of a gate, we
analyze inputs i:
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Use Inertial Delay of Gate

Ambiguity interval at gate output:
where the inertial delay of the gate is
bounded as (mindel, maxdel).
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Finding Number of Transitions
3
14
7
5
8
10
12
10 12
14
2
[mintran,maxtran]
[0,2]
3
EA
5
EA
14
(mindel, maxdel)
LS
[0,4]
1,3
6
EA
17
LS
17
LS
where mintran is the minimum number of transitions and
maxtran the maximum number of transitions.
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Estimating maxtran
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Nd: First upper bound is the largest number of transitions
that can be accommodated in the ambiguity interval
given by the gate delay bounds and the (IV, FV) output
values.
N: Second upper bound is the sum of the input
transitions as the output cannot exceed that. Further
modify it as
N=N–k
where k = 0, 1, or 2 for a 2-input gate and is determined
by the ambiguity regions and (IV, FV) values of inputs.
The maximum number of transitions is lower of the two
upper bounds:
maxtran = min (Nd, N)
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ELEC5270-001/6270-001 Spr 09, Lecture 6
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Effect of Gate Inertial Delay
D << W
W
D<W
D
D ≈W
D>W
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ELEC5270-001/6270-001 Spr 09, Lecture 6
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First Upper Bound, Nd
Nd = 1 + (LS – EA)/mindel
└
┘
1
mindel
mindel, maxdel
EA
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LS
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Examples of maxtran (k = 0)
Nd = ∞
N=8
maxtran=min (Nd, N) = 8
Nd = 6
N=8
maxtran=min (Nd, N) = 6
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Example: maxtran With Non-Zero k
[n1 = 6]
EAsv = - ∞
LSdv = ∞
EAdv
EAsv = - ∞
EA
LS
where k = 2
LSsv
[n2 = 4]
EAdv
[n1 + n2 – k = 8 ] ,
LSdv = ∞
LSsv
[6]
[6+4–2=8]
[4]
Copyright Agrawal, 2009
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Estimating mintran
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Ns: First lower bound is based on steady state values, IV  FV,

If 0  0 or 11, then Ns = 0

If 0 1 or 1 0, then Ns = 1

In case of split ambiguity intervals, separate Ns is obtained for
each interval and then all are added up

Ndet: Second lower bound is the minimum number of transitions
permitted by the maximum inertial delay of the gate (maxdel).

The minimum number of transitions is the higher of the two lower
bounds:
mintran = max (Ns, Ndet)
Copyright Agrawal, 2009
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Example: mintran
EAsv = - ∞
EAdv
LSsv = ∞
LSdv
EAdv = - ∞
EAsv


EA
LS
d
LSdv = ∞
LSsv
(mindel, maxdel)
There will always be a hazard in the output
as long as
(EAsv – LSdv) ≥ maxdel
Thus in this case the mintran is not 0 as per
the steady state condition, but is 2.
Copyright Agrawal, 2009
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Multiple Ambiguity Intervals
•
Multiple ambiguity intervals are waveform containing
intermittent regions of deterministic signal states.
•
We arrange the (EA, LS) values at the gate inputs in order
of their temporal occurrences.
•
If an (LS) value occurs before an (EA) value, then multiple
ambiguity are separated by a deterministic value.
•
We propagate the split ambiguity intervals to the output on
the condition that the deterministic interval is longer than
the gate inertial delay.
Copyright Agrawal, 2009
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Example
EA1
LS1
EA1+ d1
EA2
LS3 + d2
LS2
d1,d2
EA3
LS3
Without ordering input ambiguity intervals.
EA1
LS1
EA1+ d1
EA2
EA3 + d1
LS2
d1,d2
EA3
LS2 + d2
LS3 + d2
LS3
Ordering of input ambiguity intervals.
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Simulation Methodology


maxdel, mindel = nominal delay ± Δ%
Three linear-time passes for each input vector:



First pass: zero delay simulation to determine initial
and final values, IV and FV, for all signals.
Second pass: determines earliest arrival (EA) and
latest stabilization (LS) from IV, FV values and
bounded gate delays.
Third pass: determines upper and lower bounds,
maxtran and mintran, for all gates from the above
information.
Copyright Agrawal, 2009
ELEC5270-001/6270-001 Spr 09, Lecture 6
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Effect of Gate Delay Distribution
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
Experiment conducted to see if the distribution of
gate delays has an effect on power distribution.
For uniform distribution: Gate delays were
randomly sampled from uniform distribution [a, b],
where a = nominal delay – Δ% and b = nominal
delay + Δ% This distribution has a variance σ2 =
(b – a)2/12 = Δ2(nom. delay)2/30,000.
For normal distribution: Gate delays were
randomly sampled from a Gaussian density with
mean = nom. delay, and variance σ2 as above.
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Monte Carlo Experiment
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

A standard gate node delay of 100 ps was
taken. A wire load delay model was followed
with each nominal gate delay being a function of
its fan-out.
The power distribution is for 1000 random
vectors with a vector period of 10000 ps.
For each vector pair 1000 sample circuits were
simulated.
Copyright Agrawal, 2009
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180000
160000
Uniform Distribution
Frequency
140000
120000
100000
80000
60000
40000
20000
0
0.12 0.17 0.21 0.26 0.31 0.36 0.41 0.46 0.51 0.56 0.61 0.66 0.71 0.76 0.81 0.86 0.91 0.96 1.01 1.06 More
Power in (mW)
180000
160000
Normal Distribution
Frequency
140000
120000
100000
80000
60000
40000
20000
0
Power in (mW)
Copyright Agrawal, 2009
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Experimental Result (Maximum Power)

Monte Carlo Simulation vs. Min-Max analysis for circuit
C880. 100 sample circuits with + 20 % variation were
simulated for each vector pair (100 random vectors).
R2 is coefficient of
determination, equals 1.0 for
ideal fit.
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ELEC5270-001/6270-001 Spr 09, Lecture 6
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Result…(Minimum Power)
R2 is coefficient of
determination, equals
1.0 for ideal fit.
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Results…(Average Power)
10
9
Monte Carlo average power (mW)
R2 = 0.9527
8
7
6
5
4
3
R2 is coefficient of
determination, equals
1.0 for ideal fit.
2
1
0
0
2
4
6
8
10
MIN - MAX m ean pow er (m W)
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C880: Monte Carlo vs. Bounded
Delay Analysis
80000
1000 Random Vectors, 1000 Sample Circuits
70000
Frequency
60000
50000
40000
30000
20000
10000
2.
13
7
2.
74
74
3.
35
79
3.
96
83
4.
57
88
5.
18
92
5.
79
96
6.
41
01
7.
02
05
7.
63
1
8.
24
14
8.
85
19
9.
46
23
10
.0
73
10
.6
83
11
.2
94
1.
52
65
0
Power (mW)
Monte Carlo Simulation
Bounded Delay Analysis
Min Power
(mW)
Max Power
(mW)
CPU Time
(secs)
Min Power
(mW)
Max Power
(mW)
CPU Time
(secs)
1.42
11.59
262.7
1.35
11.89
0.3
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Power Estimation Result

Circuits implemented using TSMC025 2.5V CMOS library , with
standard size gate delay of 10 ps and a vector period of 1000 ps.
Min-Max values obtained by assuming ± 20 % variation. The
simulation was run on a UNIX operating system using a Intel Duo
Core processor with 2 GB RAM.
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Conclusion

Bounded delay model allows power
estimation method with consideration of
uncertainties in delays.

Analysis has a linear time complexity in
number of gates and is an efficient alternative
to the Monte Carlo analysis.
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Future Refinements


Consider process dependent variations in leakage and in
node capacitances.
Use statistical methods to determine distributions of
average and peak power consuming circuits. See following
references:

V. Bartkute and L. Sakalauskas, “Three Parameter Estimation of the Weibull
Distribution by Order Statistics,” in C. H. Skiadas, editor, Recent Advances in
Stochastic Modeling and Data Analysis, pp. 91–100, World Scientific, 2007.

Q. Qiu, Q. Wu, and M. Pedram, “Maximum power estimation using the
limiting distributions of extreme order statistics,” in Proc. Design Automation
Conference, June 1998, pp. 684–689.
Q.Wu, Q. Qiu, and M. Pedram, “Estimation of Peak Power Dissipation in
VLSI Circuits Using the Limiting Distributions of Extreme Order Statistics,”
IEEE transactions on Computer Aided Design of Integrated Circuits and
Systems, vol. 20, no. 8, p. 942.

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