Hierarchical Fault Collapsing
for Logic Circuits
Master’s Defense
Raja K. K. R. Sandireddy
Dept. of ECE, Auburn University
Thesis Advisor:Vishwani D. Agrawal
Committee Members:Victor P. Nelson, Charles E. Stroud
Dept. of ECE, Auburn University
Outline
• Introduction
• Background
– Fault Equivalence and Fault Dominance
– Functional collapsing
– Hierarchical fault collapsing
•
•
•
•
•
•
Fault Equivalence and Dominance definitions
Algorithm to find dominance relations
Results of functional collapsing
Hierarchical fault collapsing
Results of hierarchical fault collapsing
Conclusions and Future work
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Introduction
Test Vector Generation Flow
DUT
Fault model
Generate fault list
Collapse fault list
Required fault
coverage
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Generate test vectors
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Stuck-at Fault
• Single stuck-at fault model is the most
popular model.
a0a a1
c0c c1
b0b b1
• Subscript fault notation: a0 means stuck-at-0
on line a.
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Equivalence
Structural R-equivalence1:
Two faults f1 and f2 are said
to be R-equivalent if they produce the same reduced circuit
graph [netlist] when faulty values are implied and constant
edges [signals] are removed.
Functional F-equivalence1:
Two faults f1 and f2 are
said to be F-equivalent if they modify the Boolean function
of the circuit in the same way, i.e., they yield the same output
functions.
E. J. McCluskey and F. W. Clegg, “Fault Equivalence in Combinational
Logic Networks,” IEEE Trans. Computers, vol. C-20, no. 11, Nov. 1971,
pp. 1286-1293.
1
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Structural Equivalence
a0 a1
a1 ≡ b1 ≡ c1 : Equivalence
c0 c1
b0 b1
Equivalent faults are indistinguishable at all primary
outputs of the circuit.
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Structural Dominance
A fault fi is said to dominate fault fj if the faults
are equivalent with respect to test set of fault fj.
a0 a1
c0 c1
b0 b1
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Dominance
relations
a0  c0
b0  c0 Equivalence Relations
a1  c1
a1 ≡ c 1
a1  c 1
b1  c1
b1 ≡ c 1
a1 ≡ b1 ≡ c 1
b1  c1
a 1  b1
a1 ≡ b1
a 1  b1
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}
}
}
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Fault Collapsing
• Equivalence Collapsing:
It is the process of
selecting one fault from each equivalence fault set.
• Dominance Collapsing:
From the equivalence
collapsed set, all the dominating faults are left out
retaining their respective dominated faults.
For the OR gate,
a0 a1
Equivalence collapsed set = {a0, b0, c0, c1}
Dominance collapsed set = {a0, b0, c1}
c0 c1
b0 b1
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Collapse Ratio
Collapse Ratio 
| Set of collapsed faults |
| Set of all faults |
Example: Full adder circuit.
Total faults: 60
Structural equivalence collapsed set2, 3 = 38 (0.63)
Structural dominance collapsed set3 = 30 (0.5)
Hitec: T. M. Niermann and J. H. Patel, “HITEC: A Test Generation Package
for Sequential Circuits,” Proc. European Design Automation Conference, Feb.
1991, pp. 214-218.
3 Using Fastest: T. P. Kelsey, K. K. Saluja, and S. Y. Lee, “An Efficient Algorithm for
Sequential Circuit Test Generation,” IEEE Trans. Computers, vol. 42, no. 11, pp.
1361-1371, Nov. 1993.
2 Using
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Dominance Graph
A 2-input OR gate and its
dominance graph
Dominance Matrix
a
a0
a1
b0
b1
c0
c1
a0
1
0
0
0
1
0
a1
0
1
0
1
0
1
b0
0
0
1
0
1
0
b1
0
1
0
1
0
1
c0
0
0
0
0
1
0
c1
0
1
0
1
0
1
c
b
c0
c1
b1
a1
b0
a0
Used for fault collapsing.
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Two Algorithms: Equivalence
and Dominance4
a0
a1
b0
b1
c0
c1
Algorithm
Equivalence
a0
b0
c0
c1
a0
1
0
1
0
a0
1
0
0
0
1
0
a1
0
1
0
1
0
1
b0
0
1
11
0
b0
0
0
1
0
1
0
c0
0
0
1
0
b1
0
1
0
1
0
1
c1
0
0
0
1
c0
0
0
0
0
1
0
c1
0
1
0
1
0
1
a0
b0
c1
a0
1
0
0
b0
0
1
0
c1
0
0
1
Algorithm
Dominance
A. V. S. S. Prasad, V. D. Agrawal, and M. V. Atre, “A New Algorithm for Global Fault Collapsing into
Equivalence and Dominance Sets,” Proc. International Test Conf., Oct. 2002, pp. 391-397.
4
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Functional Equivalence
F1
F0
Z If faults in blocks F1
and F2 are equivalent,
then Z ≡ 0.
F2
F1
Z
F2
For the full-adder, functional equivalence collapsed set = 26 (0.43).
{Structural equiv. = 38, Structural dom. = 30}
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Functional Dominance5
F1
F0
1
Z
0
1
F2
If the fault introduced in block F1 dominates the fault in
block F2, then Z is always 0.
For the full adder, functional dominance collapsed set = 12 (0.20)
{Structural equiv. = 38, Structural dom. = 30, Functional equiv.= 23}
V. D. Agrawal, A. V. S. S. Prasad, and M. V. Atre, “Fault Collapsing via
Functional Dominance,” Proc. International Test Conf., 2003, pp. 274-280.
5
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Hierarchical Circuits
Increasing complexity of designs is efficiently handled
by hierarchical design process.
Hierarchical fault collapsing:
• Create a library
– For smaller sub-circuits, exhaustive collapsing is done
using the methods discussed earlier.
– For larger sub-circuits, use structural collapsing.
• At the top level, do structural collapsing using the
library information to collapse the faults at lower
levels.
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Hierarchical Fault Collapsing
Advantages:
• Fault set computed once is reused for all instances of
the sub-circuit.
• Exhaustive collapsing of faults in smaller circuits to
achieve smaller collapsed sets.
• Faster collapsing.
Theorem6: If two faults are functionally equivalent in a
sub-circuit Ci that is embedded in a circuit Cj then
they are also functionally equivalent in Cj .
Note: Functional equivalence here means diagnostic equivalence as defined next.
R. Hahn, R. Krieger, and B. Becker, “A Hierarchical Approach to Fault
Collapsing,” Proc. European Design & Test Conf., 1994, pp. 171–176.
6
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Equivalence Definitions
• Fault Equivalence:
Two faults are equivalent if and only if the
corresponding faulty circuits have identical output functions.
For multiple output circuits, this is extended for two possible
interpretations.
• Diagnostic Equivalence -
Two faults of a Boolean circuit are
called diagnostically equivalent if and only if the pair of the output
functions is identical at each output of the circuit.
• Detection Equivalence -
Two faults are called detection
equivalent if and only if all tests that detect one fault also detect the
other fault, not necessarily at the same output.
For single output circuits, diagnostic and detection equivalence mean the same.
Diagnostic equivalence implies detection equivalence.
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Examples to Demonstrate
Detection Equivalence
s-a-1
Q
s-a-1
R
The faults P1, Q1 and R1 are
detection equivalent faults,
but not diagnostic equivalent.
P s-a-1
A
s-a-0
Y
B
The faults c0 and Y0 are
detection equivalent faults,
but not diagnostic equivalent.
Z
c
s-a-0
For the full adder, diagnostic equivalence collapsed set = 26 (0.43),
detection equivalence collapsed set = 23 (0.38)
{Structural equiv. = 38, Structural dom. = 30, Functional equiv.= 26, Functional dom.= 12}
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Dominance Definitions
• Fault Dominance7
- A fault fi is said to dominate fault fj if
(a) the set of all vectors that detects fault fj is a subset of all
vectors that detects fault fi and (b) each vector that detects fj
implies identical values at the corresponding outputs of faulty
versions of the circuit.
Conventionally dominance is defined as:
• A fault fi is said to dominate fault fj if the faults are equivalent
with respect to test set of fault fj.
• If all tests of fault fj detect another fault fi, then fi is said to
dominate fj.
J. F. Poage, “Derivation of Optimum Tests to Detect Faults in Combinational
Circuits", Proc. Symposium on Mathematical Theory of Automata, 1962, pp.
483-528.
7
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Dominance Definitions Contd.
For multiple output circuits, the two possible interpretations of
dominance:
• Diagnostic dominance - If all tests of a fault f1 detect another fault
f2 on the exact same outputs where f1 was detected, then f2 is said
to diagnostically dominate f1.
• Detection dominance - If all tests of a fault f1 detect another fault
f2, irrespective of the output where f1 was detected, then f2 is said to
detection dominate f1 .
Diagnostic dominance implies detection dominance.
For the full adder, diagnostic dominance collapsed set = 12 (0.2)
detection dominance collapsed set = 6 (0.1)
{Structural equiv. = 38, Structural dom. = 30, Diagnostic equiv.= 26, Detection
equiv.= 23}
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Functional Dominance
Faults in this circuit are
checked for
redundancy
F0
F0
D or D
D0 or D
10
F1
Fault introduced in
this circuit
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Algorithm to Find All
Dominance Relations
1. Select a fault from the given circuit and build the circuit
as shown in previous slide with the fault introduced in the
bottom block whose function is F1.
2. Check for redundant faults in the top block, F0.
3. For each redundant fault found in step 2, a 1 is placed in
the dominance matrix at the intersection of the row
corresponding to the redundant fault and the column
corresponding to the fault in the bottom block. Thus, we
obtain all values of a column of the dominance matrix in
a single iteration.
4. Go to step 1 until there is no fault left.
5. Now we will have the dominance matrix with all the
functional dominance relations included.
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Algorithm Contd.
6. Transitive closure of the dominance matrix is computed,
which is then reduced using algorithm equivalence4. This
reduced matrix still consists of dominance relations
within an equivalence collapsed set of faults.
7. If dominance collapsing is required, then the reduced
matrix of the previous step is further reduced according to
algorithm dominance4.
For simplicity, the redundant faults of the given circuit
(stand-alone F0) are not considered in step 1.
A. V. S. S. Prasad, V. D. Agrawal, and M. V. Atre, “A New Algorithm for Global
Fault Collapsing into Equivalence and Dominance Sets,” Proc. International Test
Conf., Oct. 2002, pp. 391-397.
4
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For Multiple Output Circuits
For a circuit with 2 outputs, the schemes used to find the
dominance relations:
F0
F0
F0
F0
F1
F1
Diagnostic collapsing
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Detection collapsing
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Results: Functional Collapsing
Number of Collapsed Faults (Collapse Ratio)
Functional Collapsing – New Results
Circuit
Name
All
Faults
Structural
Functional5
Diagnostic
Criterion
Detection
Criterion
Equiv.2
Dom.3
Equiv.
Dom.
Equiv.
Dom.
Equiv.
Dom.
XOR
24
16
(0.67)
13
(0.54)
10
(0.42)
4
(0.17)
10
(0.42)
4
(0.17)
10
(0.42)
4
(0.17)
Full
Adder
60
38
(0.63)
30
(0.50)
26
(0.43)
14
(0.23)
26
(0.43)
12
(0.20)
23
(0.38)
6
(0.10)
8-bit
Adder
466
290
(0.62)
226
(0.49)
194
(0.42)
112
(0.24)
194
(0.42)
96
(0.21)
191
(0.41)
48
(0.10)
ALU
(74181)
502
301
(0.60)
248
(0.49)
--
--
253
(0.50)
155
(0.31)
234
(0.47)
92
(0.18)
2 Using
Hitec (obtained from Univ. of Illinois at Urbana-Champaign)
Fastest (obtained from Univ. of Wisconsin at Madison)
5 Agrawal, et al. ITC’03
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Results: Test Vectors
Test vectors obtained using Gentest ATPG8.
No. of test vectors (no. of target faults)
Circuit
Structural
Functional – New Results
Equivalence
Dominance
Diagnostic
Dominance
Detection
Dominance
Full Adder
6 (38)
6 (30)
7 (12)
6 (6)
8-bit Adder
33 (290)
28 (226)
32 (96)
28 (48)
ALU
44 (293)
44 (240)
39 (147)
38 (84)
8 W.
T. Cheng and T. J. Chakraborty, “Gentest: An Automatic Test Generation System for
Sequential Circuits,” Computer, vol. 22, no. 4, pp. 43–49, April 1989.
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Hierarchical Fault Collapsing
Line Oriented Structural Fault Collapsing9:
Type of gate the line
feeds into
Put this (these) fault (s)
on the line
INV, BUF
None
OR, NOR
s-a-0
AND, NAND
s-a-1
Sub-circuit, Fanout
s-a-0, s-a-1
Primary Output
s-a-0, s-a-1
M. Nadjarbashi, Z. Navabi, and M. R. Movahedin, “Line Oriented Structural Equivalence
Fault Collapsing,“ IEEE Workshop on Model and Test, 2000.
9
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Hierarchical Fault Collapsing
G1
0 1
A
01
0 1
0
M
B
0
1
G2
G3
G4
0 1
1
0
C
Algorithm to find the dominance matrix and its transitive closure:
1. Consider a fault (f1) stuck-at-b at the input of a Boolean gate.
2. If the gate is of inverting type (NOT, NOR, NAND), then invert b.
3. If the equivalent set has s-a-b on this gate output, say f2, then return this fault
– place a 1 at the intersection of the row corresponding to f1 and column
corresponding to f2 – use Update10 for transitive closure. End.
4. Move one gate forward towards the primary output and go to step 2.
K. K. Dave, V. D. Agrawal, and M. L. Bushnell, “Using Contrapositive Law in an
Implication Graph to Identify Logic Redundancies,” Proc. 18th International Conf. VLSI
Design, Jan. 2005, pp. 723-729.
10
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Collapsed Information File as
Saved in Library
$RELATIONs:
1: 4 5 12 0
2: 6 13 0
3: 9 13 0
4: 1 5 12 0
5: 1 4 12 0
6: 2 13 0
9: 13 0
12: 1 4 5 0
13: 0
$INPUTs:
a12
b* 3 4
$OUTPUTs:
g3 12 13
$TOTAL: 14
$FAULTs:
g1(0) 5
g1(1) 6
g2(1) 9
$REDUNDANT:
g1(b,0) 14
Collapsed fault set sizes
Flat
Hierarchical
Equivalence
12
11
Dominance
8
8
Feb. 9, 2005
g1
a
b
Circuit M
g3
g2
A
B
G1
M
G2 G3
G4
C
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Results: Collapse Ratios
Comparison of fault collapse ratios
0.7
Structural Equiv.
0.6
0.5
0.4
0.3
Hierarchical Equiv.
(diagnostic)
Structural Dom.
0.2
0.1
0
Hierarchical Dom.
(diagnostic)
Full
Adder
64-bit
Adder
1024-bit
Adder
c432
c499
Total Faults:
Full adder: 60, 64-bit Adder: 3714, 1024-bit Adder: 59394, c432:1116, c499:2646
Detection collapsing can be used only for those sub-circuits
whose outputs are POs at the top-level.
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CPU Time (s) for Different Sections of
Our Program for Flattened Circuits
64-bit
128-bit
256-bit
512-bit
1024-bit
2048-bit
4096-bit
8192-bit
Flat Structure
Processing
Equivalence
Collapsing
Dominance
Collapsing
Total
0.13
0.54
2.05
8.60
38.3
163.1
667.4
2662
0.02
0.05
0.09
0.17
0.36
0.74
1.49
3.43
0.03
0.05
0.09
0.20
0.41
0.84
1.63
3.73
0.24
0.75
2.49
9.38
39.9
166.4
674.1
2676
CPU time clocked on a 360MHz Sun UltraSparc 5_10 machine with 128MB memory.
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CPU Time (s) for Different Sections of
Our Program for Flattened Circuits
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CPU Time (s) of Different Commands
of Hitec for Fault Collapsing
64-bit
128-bit
256-bit
512-bit
1024-bit
2048-bit
4096-bit
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Structure
Processing (level)
Equivalence
Collapsing (equiv)
Total
0.32
1.03
4.0
16.0
64.9
275.1
1045
0.16
0.34
0.88
3.15
12.2
50.4
210
0.57
1.47
5.09
19.5
77.7
326
1258
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Comparison of CPU Times (s) Taken
by Hitec and Our Program
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CPU Time (s) of Different Sections of
Our Program for Hierarchical Circuits
64-bit
128-bit
256-bit
512-bit
1024-bit
2048-bit
4096-bit
8192-bit
Feb. 9, 2005
Structure
Processing
Equiv.+Dom.
Collapsing
Library
Total
0.01
0.03
0.05
0.17
0.55
2.10
9.25
40.1
0.01
0.02
0.02
0.04
0.08
0.20
0.37
0.79
0.07
0.13
0.19
0.36
0.73
1.52
3.1
6.0
0.10
0.19
0.39
0.81
1.82
4.72
14.3
50.2
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CPU Time (s) of Our Program for
Hierarchical and Flattened Circuits
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CPU Time (s) Improvement by Hierarchy
Flattened circuit
Hierarchical circuit
Hitec
Our Program Two-level Multi-level
64-bit
128-bit
256-bit
512-bit
1024-bit
2048-bit
4096-bit
8192-bit
Feb. 9, 2005
0.57
1.47
5.09
19.5
77.7
326
1258
--
0.24
0.75
2.49
9.38
39.9
166.4
674.1
2676
Raja Sandireddy: MS Defense
0.16
0.32
0.69
1.52
3.60
10.3
35.1
127.2
0.10
0.24
0.49
1.05
2.31
4.80
16.6
55.0
36
CPU Time (s) for Hierarchical Collapsing
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Conclusions
• Diagnostic and detection collapsing should be used only with
smaller circuits.
• Collapse ratios using detection dominance collapsing is about
10-20%.
• For larger circuits described hierarchically, use hierarchical fault
collapsing.
• Hierarchical fault collapsing:
– Better (lower) collapse ratios due to functional collapsed library
– Order of magnitude reduction in collapse time.
8192-bit Adder
• Smaller fault sets:
– Fewer test vectors
– Reduced fault simulation effort
– Easier fault diagnosis.
Dom. Collapsed Set Size
(Collapse Ratio)
CPU s
Flat
Hierarchical
Flat
Hier.
229378 (0.48)
98304 (0.21)
2676
55
• Use caution when using dominance collapsing!!
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Future Work
• Generate fault collapsing library of standard cells
(Mentor Graphics, etc.)
• Incorporate VHDL or Verilog input for hierarchical
netlist.
• Efficient redundancy detection program.
• Customized ATPG to obtain minimal test vector set.
• Extend the work for sequential circuits.
• Extend the work for other fault models.
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THANK YOU
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