W4118 Operating Systems
Instructor: Junfeng Yang
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Logistics
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Homework 4 deadline extended 3:09pm 3/31
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Last Lecture: Paging
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Disadvantages of contiguous allocation
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External fragmentation
Wasteful allocation of unused memory
No sharing
Paging: divide memory into fixed-sized pages
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Each address is split into page number and page
offset
Page table maps virtual page number to physical
page number
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Last lecture: Paging Advantages
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No external fragmentation
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Don’t need to allocate unused memory
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Fine-grained sharing
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Two page table entries from two process can point
to the same physical page
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Easy to swap out to disk (later this lecture)
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Efficient Allocation and Free
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Allocation: since fixed size, no search necessary
Free: insert page to free list
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Last lecture: Paging Disadvantages
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Internal fragmentation
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Page tables can be large
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• Multi-level page tables
• Hashed page tables
• Inverted page tables
Inefficiency: two memory accesses for each CPU
memory access
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Techniques to reduce memory overhead
Translation look ahead buffer (TLB): exploit temporal and
spatial locality to reduce the number of memory accesses
Page size?
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Too small?
Too large?
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Today
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Segmentation
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Virtual memory
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Segmentation
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Divide address space into logical segments
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Each logical segment can be part of physical memory
Separate base and limit for each segment (+ protection bits)
How to specify a segment?
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User part of logical address (similar to how to select a page)
• Top bits specify segment
• Low bits specify offset within segment
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Implicitly by type of memory reference
• Code v.s. Data segment
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Special registers
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User’s View of a Program
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Logical View of Segmentation
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4
1
2
2
3
4
3
user space
physical memory space
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Segmentation Architecture
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Logical address consists of a two tuple:
<segment-number, offset>,
Segment table – maps two-dimensional physical
addresses; each table entry has:
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base – contains the starting physical address where the
segments reside in memory
limit – specifies the length of the segment
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Segmentation Architecture (Cont.)
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Protection
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With each entry in segment table associate:
• validation bit = 0  illegal segment
• read/write/execute privileges
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Protection bits associated with segments; code
sharing occurs at segment level
Since segments vary in length, memory
allocation is a dynamic storage-allocation
problem
A segmentation example is shown in the
following diagram
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Segmentation Hardware
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Example of Segmentation
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Segmentation Advantages
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Advantages
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Sharing of segments
Easier to relocate segment than entire program
Avoids allocating unused memory
Flexible protection
Efficient translation
• Segment table small  fit in MMU
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Disadvantages
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Segments have variable lengths  dynamic
allocation overhead (Best fit? First fit?)
External fragmentation: wasted memory
• Segments can be large
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Combine Paging and Segmentation
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Structure
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Segments: logical units in program, such as code, data,
and stack
• Size varies; can be large
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Each segment contains one or more pages
• Pages have fixed size
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Two levels of mapping to reduce page table size
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Page table for each segment
Base and limit for each page table
Similar to multi-level page table
Logical address divided into three portions
seg #
page # offset
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Example: 80x86
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Supports both segmentation and segmentation
with paging
CPU generates logical address
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Given to segmentation unit
• Which produces linear addresses
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Linear address given to paging unit
• Which generates physical address in main memory
• Paging units form equivalent of MMU
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80x86 Segment Selector
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Logical address: segment selector + offset
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Segment selector stored in segment registers (16-bit)
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cs: code segment selector
ss: stack segment selector
ds: data segment selector
es, fs, gs
Segment register can be implicitly or explicitly
specified
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mov $8049780, %eax // implicitly use ds
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mov %ss:$8049780, %eax // explicitly use ss
• Logical address: ds : $8049780
• Logical address: ss : $8049780
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80x86 Segmentation Unit
Descriptor table
seg descriptor
segment
memory
ds
seg selector
mov $8049780, %eax
seg descriptor
CPU
Two memory references
for one load! How to
optimize?
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Translating Logical to Linear Address
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80x86 Paging Unit
4MB page
started with
Pentium
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Today
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Segmentation
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Virtual memory
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Motivation
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Previous approach to memory management
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Must completely load user process in memory
One process with large address space or many processes
with combined address space  out of memory
Observation: locality of reference
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Temporal locality: access memory location accessed just
now
Spatial locality: access memory location adjacent to
locations accessed just
Programs spend majority of time in small piece of code
• 90% of time in 10% of code (Knuth’s estimate)
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Thus, processes only need small amount of address
space at any moment
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Virtual Memory Idea
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OS and hardware produce illusion of a disk as
fast as main memory
Process runs when not all pages are loaded in
memory
Keep referenced pages in main memory
Keep unreferenced pages on slower, cheaper
backing store (disk)
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Memory Hierarchy
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Levels of memory in computer system
size
speed
registers
cache
cost
< 1 cycle
a few cycles
memory
<100 ns
disk
a few ms
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Virtual Address Space
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Virtual address maps to one of three locations
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Physical memory: small, fast, expensive
Disk: large, slow, cheap
Nothing
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Virtual Memory Operation
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What happens when reference a page in
backing store?
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Recognize location of page
Choose a free page
Bring page from disk into memory
Above steps need hardware and software
cooperation
How to detect if a page is in memory?
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Extend page table entries with present bits
• Page fault: if bit is cleared then referencing resulting
in a trap into OS
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Handling a Page Fault
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OS selects a free page
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OS brings faulting page from disk into memory
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Page table is updated, present bit is set
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Process continues execution
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Steps in Handling a Page Fault
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Continuing Process
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Continuing process is tricky
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Page fault may have occurred in middle of
instruction
Want page fault to be transparent to user
processes
Options
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Skip faulting instruction?
Restart instruction from beginning?
• What about instruction like: mov ++(sp), R2
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Requires hardware support to restart
instructions
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OS Decisions
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Page selection
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When to bring pages from disk to memory?
Page replacement
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When no free pages available, must select victim
page in memory and throw it out to disk
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Page Selection Algorithms
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Demand paging: load page on page fault
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Request paging: user specifies which pages are
needed
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Start up process with no pages loaded
Wait until a page absolutely must be in memory
Users do not always know best
Preparing: load page before it is referenced
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When one page is referenced, bring in next one
Do not work well for all workloads
• Difficult to predict future
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Page Replacement Algorithms
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Optimal: throw out page that won’t be used for longest time
in future
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Random: throw out a random page
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Easy to implement
Works surprisingly well
FIFO: throw out page that loaded in first
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Best algorithm if we can predict future
Good for comparison, but not practical
Fair: all pages receive equal residency
LRU: throw out page that hasn’t been used in longest time
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Past predicts future
With locality: approximates Optimal
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Page Replacement Algorithms
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Want lowest page-fault rate
Evaluate algorithm by running it on a
particular string of memory references
(reference string) and computing the number
of page faults on that string
In all our examples, the reference string is
1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
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Optimal Algorithm
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Replace page that will not be used for longest
period of time
4 frames example
1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1
4
6 page faults
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3
4
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How do you know this?
Used for measuring how well your algorithm
performs
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First-In-First-Out (FIFO) Algorithm
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Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
3 frames (3 pages can be in memory at a time per process):
1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1
1
4
5
2
2
1
3
3
3
2
4
1
1
5
4
2
2
1
5
3
3
2
4
4
3
9 page faults
10 page faults
4 frames: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
Belady’s Anomaly: more frames  more page faults
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Graph of Page Faults Versus The Number of
Frames
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FIFO Illustrating Belady’s Anomaly
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Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
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Least Recently Used (LRU) Algorithm
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Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1
1
1
1
5
2
2
2
2
2
3
5
5
4
4
4
4
3
3
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Counter implementation:
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Every page entry has a counter; every time page is
referenced through this entry, copy the clock time
into the counter
When a page needs to be changed, look at the
counters to determine which are to change
Problem: have to search all pages/counters!
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Implementing LRU: Stack
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Stack implementation – keep a stack of
page numbers in a double link form:
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Page referenced:
• move it to the top
• requires 6 pointers to be changed
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No search for replacement
• bottom entry is by definition least used
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Use Of A Stack to Record The Most Recent Page
References
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LRU: Concept vs. Reality
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LRU is considered to be a reasonably good
algorithm
Problem is in implementing it
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Counter implementation: counter per page, copied
per memory reference, have to search pages on
page replacement to find oldest
Stack implementation: no search, but pointer swap
on each memory reference
Thus the efforts to design efficient
implementations that approximate LRU
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LRU Approximation Algorithms
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Reference bit
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With each page associate a bit, initially = 0
When page is referenced bit set to 1
Replace the one which is 0 (if one exists)
• We do not know the order, however
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Second chance
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Need reference bit
Clock replacement
If page to be replaced (in clock order) has reference
bit = 1 then:
• set reference bit 0
• leave page in memory
• replace next page (in clock order), subject to same rules
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Second-Chance (clock) Page-Replacement
Algorithm
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Paging in 64 bit Linux
Platform
Page
Size
Address
Bits
Used
Alpha
8 KB
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3
10+10+10+13
IA64
4 KB
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3
9+9+9+12
PPC64
4 KB
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3
10+10+9+12
sh64
4 KB
41
3
10+10+9+12
X86_64
4 KB
48
4
9+9+9+9+12
Paging
Levels
Address
Splitting
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