TMS320C24x Overview
Max Chyou
Engineering Manager
AmRoad Co.Ltd.
Maxchyou@amroad.com.tw
Copyright © Am Road Electronics Co., Ltd.
Contents
 Introduction
 Architectural Overview
 Clocks
 Power Management
 Interrupts
 Timer
 PWM Architecture
 Space Vector
 Q&A
Introduction
Introduction
Why DSP?
 Benefits of Digital System

Reliability, flexibility

Time sharing / task switching

Freedom from environmental effects

Bandwidth and resolution of analog system
Introduction
Why DSP?
 Optimized Architecture

Instruction set tailored for signal processing functions

Architecture minimizes numerical problems in processing
discrete signals
Introduction
Why DSP?
 High Performance

Implementation of complex algorithms in real-time

Implementation of high sampling rates

Minimizes computational delay

Performance to implement multiple functions
Introduction
 Features
 Benefits

Single-cycle instruction

High sampling rates /
control of high bandwidth
system

DSP instruction set

Real-time execution of
advanced control
algorithms

Multiple buses

Simultaneous access of
data and instructions

Hardware multiplier

Minimize computational
delays

Hardware scaling shifters
Introduction
 Features
 Benefits

Hardware scaling shifters

Fast scaling / dynamic
range

16-bit word length

Minimize quantization
errors

32-bit ALU / ACC

Minimize truncation errors

Hardware stack

Fast interrupt processing

Saturation mode

Prevent wrap around of
ACC
Introduction
 Function
 Benefits

Notch filter algorithms

Cancel mechanical
resonance

Adaptive Kalman filter
algorithms

Reduce sensor noise

State estimator algorithms

Estimate multiple variables

Vector control algorithms

Real-time axis
transformation

Pulse width modulation
(PWM)

Improve motor control
Introduction
 Function
 Benefits

Notch filter algorithms

Cancel mechanical
resonance

Adaptive Kalman filter
algorithms

Reduce sensor noise

State estimator algorithms

Estimate multiple variables

Vector control algorithms

Real-time axis
transformation

Pulse width modulation
(PWM)

Improve motor control
Introduction
 Function
 Benefits

High order PID control
loop

Precise control

High sample rate

High system bandwidth

Time division multiplexing

Several control system
implementations with 1
DSP device

Fuzzy set control
algorithms

“Intelligent” control
Introduction
 Function
 Benefits

Dead band controller

Quick settling time

State controller

Control many variables

Power factor correction

Reduce motor power loss

FFT algorithms

Analyze mechanical
resonance

Adaptive control
algorithms

Reduce disturbance
effects
DSP CORE
Core Architecture
•
Controller
A(15-0)
Program Bus
•
Program
Memory
Memory
Mapped
Registers
D(15-0)
Data Bus
Peripherals
* ‘C240 Only System
Interface
Module *
Multiplier
Data
Memory
Peripherals
(Event Mgr)
ALU/Shifters
Core Architecture
Data Bus
16
16
16
16
T (16)
MULTIPLIER
P (32)
SHIFTER (0-16)
32
SHIFTER (-6, 0, 1, 4)
32
32
MUX
32
32
ALU (32)
32
C
Data Bus
ACCH (16) ACCL (16)
•
32
SFL (0-7)
16
16
16
MUX
16
Core Architecture
16
Program Bus
16
•
16
12-15
MUX
16
Program
ROM /
FLASH
•
PC
• 16
16
STACK
(8x16)
Address
A(15-0)
MUX
16
Instruction
16
16
16
MUX
D(15-0)
16
Data Bus
To Data Memory
16
Peripheral
Clock Signals
XTAL1
crystal
x4
PLL
Clock Module
39.0625 kHz
Prescaler
WDCLK
Watchdog
CLKOUT
XTAL2
CPU Core Memory CAN
Event Manager SCI SPI
External Memory Interface
CPUCLK
Prescaler
ADCCLK
ADC
Architecture
Data Bus
16
From Program Memory
3
3
ARP(3)
3
ARB(3)
3
16
16
•
•
MUX
AR0(16)
AR1(16)
AR2(16)
AR3(16)
AR4(16)
AR5(16)
AR6(16)
AR7(16)
Program Bus
16
9
7 LSB
From IR
DP(9)
9
16
16
MUX
• 16
16
MUX
ARAU(16)
16
16
Data / Program
Data
RAM
RAM
16
MUX
16
16
16
Architecture
Event Manager
GP Timers
Compare Unit
Non-EV Manager
Capture Unit
Quadrature
Encoder
Pulse (QEP)
Watchdog Timer
SPI
SCI
A/D Converter
I /O Pins
CAN
System
Interface
Module
(‘F/C240 only)
Data Bus
PWM Outputs
Dead-Band Logic
Watchdog Timer
•
WDCLK
System
Reset
•
6 - Bit
Free Running
Counter
/64
/32
/16
/8
/4
/2
111
110
101
100
011
010
001
000
CLR
•
WDPS
WDCR . 2 - 0
•
WDCR . 6
WDDIS
•
WDCNTR . 7 - 0
8 - Bit Watchdog
Counter
One-Cycle
Delay
CLR
WDCR . 5 - 3 WDCHK 2-0
Watchdog
Reset Key
Register
55 + AA
Detector
Good Key
Bad Key
••
••
1 0 1
3
3
/
/
Bad WDCR Key
•
Power Manager
Low Power Mode
Comments
Normal Run
Power
~80 mA @ 20 MIPS
Idle 1
CPU off
~ 50 mA
Idle 2
All Peripherals off
(except watchdog)
~ 7 mA
Halt
Oscillator & Watchdog off
~ < 1 mA
Note: PLL is on all the time for ‘X241/2/3!
Interrupt
RS
NMI
‘C24x
CORE
INT1
INT2
INT3
INT4
INT5
INT6
 2 non-maskable interrupts
(RS, NMI)
 6 maskable interrupts
(INT1 - INT6)
System Reset
‘C24x Core
Watchdog Timer
RS
RS pin active
To RS pin
Reset
Vcc
10K
• •
‘C24x
RS
External
Device
reset
• RS pin must be held low a minimum of one CPUCLK
cycle to ensure recognition of a reset
17 CPUCLK cycles
RS
8 cycles min.
Reset Vector
Fetched
• Once a reset source is activated, RS pin is driven low
for 8 CPUCLK cycles minimum
Event Management
EV and Non-EV
Peripherals
‘C24x CORE
Internal Sources
External Sources
RS
PDPINT
XINT1
XINT2
NMI
EV and
Non-EV
Peripheral
Interface
RS
NMI
INT1
INT2
INT3
INT4
INT5
INT6
Event Management
Core
Interrupt
(IFR)
“Latch”
INT1
1
INT2
0
INT3
1
(IMR)
“Switch”
(INTM)
“Global Switch”
‘C24x
Core
Event Management
To Core
Interrupt
INT1
XINT1
Flag
Polarity
Enable
Arbitrator
XINT2
Flag
Polarity
Enable
ADCINT
Flag
Enable
Event Management
Core
INT1
Compare 1,2,3
Timer 1
INT2
Timer 2
Capture 1,2,3
INT3
PDPINT
INT4
INT5
INT6
EV
•
XINT1,2 (high priority)
SPI, SCI, CAN (high priority)
ADC (high priority)
SPI, SCI, CAN (low priority)
ADC (low priority)
XINT1,2 (low priority)
Non
EV
Latency
 Latency

delay between an interrupt request and the first interrupt
specific code fetch
 TMS320C24x Latency Components
 Peripheral
interface time (synchronization)
 CPU response time (core latency)
 ISR branching time (ISR latency)
Stack Operation
Hardware stack is expandable to data memory
using PSHD/POPD
INT
CALL
8-LEVEL
POPD
HARDWARE
PC
RET
DATA
MEMORY
STACK
PSHD
PUSH
POP
ACCL
Protection
 Interrupt latency may not protect hardware when
responding to over current through ISR software
 PDPINT has a fast, clock independent logic path to highimpedance the PWM output pins (~ 45-55 ns)
‘C24x
DSP
CORE
PDPINT
flag
clock synch.
Over
Current
Sensor
PDPINT Enable
P
W
M
O
U
T
P
U
T
S
Timer
GP Timer
Stop/Hold
Up Counting
Continuous
Up/Down Counting
Continuous
Directional
Timer Architecture
TMRCLK
pin
CPUCLK
(internal DSP)
MUX
clocking
signal
Prescale
Counters
TxCNT
Timer
Counter
TMRDIR
pin
16
Compare
Logic
16
Period Register
Buffer
TxPR
Period Register
auto-load on underflow
UP Timer
This example:
TxPR = 3 (initially)
Prescale = 1
CPU writes a 2 to
period reg. buffer
anytime here
3
3
2
2
1
TxCNT Reg.
TxCON[6]
CPUCLK
0
TxPR=2 is auto-loaded
on underflow here
2
1
0
2
1
0
1
0
U/D Timer
This example:
TxPR = 3 (initially)
Prescale = 1
 Seamless up/down repetition
 Up/down count period is 2*TxPR
CPU writes a 2 to
period reg. buffer
anytime here
3
2
2
1
1
TxCNT Reg.
TxCON[6]
CPUCLK
0
TxPR=2 is auto-loaded
on underflow here
2
1
0
2
1
1
0
1
0
PWM Architecture
Reset
INT2, 3, 4
EV Control Registers / Logic
GP Timer 1 Compare
GP Timer 1
/
2
TMRCLK / TMRDIR
ADC Start
Waveform
Generator Output Logic
T1PWM/T1CMP
•
Full Compare 1
Full Compare 2
PWM Circuits Output Logic
PWM Circuits Output Logic
Full Compare 3
PWM Circuits Output Logic
Data Bus
GP Timer 2 Compare
GP Timer 2
MUX
Waveform
Generator Output Logic
CLK
DIR
T2PWM/T2CMP
QEP
Circuit
•
Capture Units
PWM1/CMP1
PWM2/CMP2
PWM3/CMP3
PWM4/CMP4
PWM5/CMP5
PWM6/CMP6
•
CAP1/QEP1
CAP2/QEP2
CAP3
TIMER
This example:
TxPR = 3
Prescale = 1
CPUCLK as source
Count holds at TxPR=3
since TMRDIR = hi
on rising clock edge
2 CPUCLK latency
2 CPUCLK latency
3
2
1
0
TxCNT Reg.
TMRDIR
TxCON[6]
CPUCLK
0
0
0
3
3
3
2
1
0
0
0
PWM Architecture
This example:
TxCON.3-2 = 00 (reload TxCMP on underflow)
TxPR = 3
TxCMP = 1 (initially)
CPU writes a 2 to
Prescale = 1
compare reg. buffer
TxCMP=2 is loaded here
anytime here
3
3
2
2
1
TxCNT Reg.
TxPWM/TxCMP
(active high)
TxCINT
CPUCLK
0
3
2
1
0
1
0
0
PWM Architecture
This example:
TxCON.3-2 = 01 (reload TxCMP when on underflow or period match)
TxPR = 3
TxCMP = 1 (initially)
Prescale = 1
TxCMP loads
with a 1
TxCMP loads
with a 2
3
2
1
TxCNT Reg.
TxPWM/TxCMP
(active high)
CPUCLK
0
TxCMP loads
with a 1
3
2
2
1
1
0
2
1
0
PWM Architecture
SV
T1CNT 16
(GP Timer 1)
Compare
Logic
MUX
Dead
Band
sym.
asym.
16
Output
Logic
Compare
Reg. Buffer
PWMy/
CMPy
CMPRx
compare register
auto-load on software selectable events
Space Vector
Space Vector
Only states of transistors 1, 3, & 5 need be determined since 2, 4, & 6
are their respective compliments
Switching State Notation: (Q5,Q3,Q1)
e.g. (0,0,1) means gate 1 is on, gates 3 & 5 are off
Vs
DTPH1
1
DTPH2
3
Va
DTPH1
2
DTPH3
5
Vb
DTPH2
4
Vc
DTPH3
GND
3-Phase Power Converter
6
Space Vector
(Q5,Q3,Q1) = (001)
 Va=Vs , Vb=Vc= GND
Vs /3
Vc
2Vs /3
i/2
i
60°
Va
Vs /3
y
x
Vs /3
60°
i/2
Vb
Y-Connected Motor Windings
Showing Current Flow
x - dir:
2Vs
V
+ 2  s cos( 60) = Vs
3
3
y - dir:
Vs
V
sin( 60) - s sin( 60) = 0
3
3
Voltage Drop Vectors
Space Vector
U120 (010)
U180 (110)
O(000)
O(111)
U240 (100)
U60 (011)
U0 (001)
U300 (101)
Basic Space Vectors w/ Switching Patterns
Space Vector
 Approximate desired voltage drop
vector as a linear combination of
the basic space vectors
 Coefficients are duration times
U60 (011)
Uout
T2
T1
U out
T1
T2
T0

Ux 
 U x  60 
 [O ( 000) or O (111)]
Tp
Tp
Tp
where T0  T p  T1  T2 and T p :  PWM carrier period
U0 (001)
Space Vector
T1PR match
Full compare #2
match
GP Timer 1 value
Full compare #1
match
DTPH1
DTPH2
DTPH3
T1/2
T2/2
Tp/2
U0
(001)
U60
(011)
O
(111)
O
(111)
U60
(011)
U0
(001)
PWM
supply rail
Gate Signals are
Complimentary PWM
to motor phase
 Transistor gates turn on faster than they shut off
 Short circuit if both gates are on at same time!
Asymmetric PWM Example
CPUCLK
(20 MHz)
Clock
prescaler
PHx
PHx
edge
detect
DT
ENA
reset
Counter
8-bit
Comparator
DTPHx
DT
DTPHx_
4-bit period
(DBTCON.11-8)
dead time
DTPHx
DTPHx_
2-Level FIFO
8/1
MUX
Sample
& Hold
10 bit A/D
Converter
2-Level FIFO
VREFHI
VREFLO
ADCSOC
5 volts
GND
VCCA
AGND
Event Manager
SOC Signal
Control
&
Reference
Circuitry
Internal Data Bus
Ch. 0-7
A/D Converter
Q&A
Thanks