Evaluation of a safety multi core
platform for the sensorless drive of a
PMSM
作者 :
Saarland University of Applied Sciences, School of
Engineering,
University of Applied Sciences, Sc
Saarland University, Laboratory of Actuation Technology,
University, Laboratory of Actu
學生 : 賴弘偉
教授 : 王明賢
Outline
Abstract
 Introduction
 Related work
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Sensorless drive application
Evaluation of cross-core interference
Conclusion and future work
Reference
Abstract
To reduce hardware requirements and costs recent applications apply
sensorless methods to drive electrical machines. However, such methods
have a high demand on CPU resources, reducing the possibility to integrate
further applications into the system. Multi-core architectures potentially
provide the necessary performance for joint integration of sensorless driving
methods and additional, typically outsourced, applications. However, such
parallel execution can induce cross-core interference which can corrupt the
time-critical execution of the drive controller and reduce the overall system
performance. In this paper we evaluate a speed control application for a
sensorless drive and quantify its sensitivity to cross-core interferences.
Introduction
Recent procedures to drive permanent magnet synchronous motors
(PMSM) in the field of electrical drive engineering are based on
sensorless analysis methods. Such methods observe parameters of
the electrical drive to continuously calculate the necessary pulse
patterns for its operation. Common cycle times for observation and
calculation are in a range of 25 microseconds (Thiemann (2011)).
The sensorless algorithms are fully implemented in software, so
safety requirements in particular must be met to maintain a correct
real-time behavior and to preserve data integrity.
Related work
For quantifying the interferences to the sensorless drive application,
a direct method will be used. This characterization is based on the
method for contention interference synthesis introduced in Mars
(2011). This model uses a periodic probing approach for the
intermittent synthesis of the contentions and hardware performance
monitoring (Mars (2009)). The synthesis is intended to aggressively
access memory causing as much cross-core interference as
possible.
Sensorless drive application
In this section we give a description of the application that is used
for the evaluation. The application encompasses the sensorless
drive method Direct Flux Control (DFC) and a field oriented speed
control (FOC). Further, a 24 VDC PMSM with 54 stator poles and 20
rotor pole pairs and an accessible machine star point is used. This
PMSM is typically applied as motor in small electric vehicles.
Sensorless Speed Control
Building upon Thiemann (2012), the following description of the
basic functionality of DFC and FOC is standard. To drive the PMSM,
three phase-shifted PWM patterns have to be calculated. This
calculation is done by DFC observing the linkage of the magnetic
flux of the PMSM. The observation is performed synchronously with
the frequency of the PWM fPWM. Typical values for fPWM are in the
range of 10-40 kHz. So the observer collects new data in each cycle
of the PWM and prepares it for further processing.
Timing of DFC and FOC
FOC does not necessarily provide new presets for each DFC
frame. The frequency with which FOC can be executed depends
on the performance of the system and is controlled by our
application architecture. Within the period of one FOC cycle, we
summarize the needed runtime to calculate the rotor position
and the presets. Hence, the frequency of FOC is given by
Application Architecture
The integration of DFC and FOC into a defined software
architecture aims at providing a reliable and uniform basis for
sensorless drive applications. This allows extending and
exchanging individual parts of the application for further
research, while maintaining the possibility to put the individual
results in relation to each other.
Evaluation of cross core interference
The evaluation aims to show and to quantify the cross core
interferences emerging due to the parallel execution of the DFC
algorithm and the tasks performing the FOC speed control. In
the following we describe the analysis approach used and the
results for the drive application. In order to simplify, we refer to
the intermediary and the FOC tasks as FOC application.
Analysis Methodology
To determine the interferences we measured the IPCs during
regular executions of the application taking samples for each
FOC cycle. To determine the dependency of the interference on
the PWM frequency, we collected the IPCs for different values of
fPWM. These values were compared to the IPC of a reference
frequency fPWM REF. With the IPCs for a test frequency fPWM i
and fPWM REF we calculated the Cross Core Interference
Sensitivity (CIS) score for fPWM i. The score is calculated as the
difference of fPWM i and fPWM REF normalized to fPWM REF:
Analysis Methodology
We determined the CIS score for an interval of different test frequencies.
The lower bound of the interval is the reference frequency. It is set to a
period that is long enough such that no parallel execution of DFC and
FOC can take place. The upper bound is the highest frequency that can
be used to drive the PMSM on the given multi core platform. For higher
frequencies, a reliable sensorless operation of the electrical drive would
not be possible due to TDFC > TPWM. For the given application we
chose fPWM i with 5 < i 40 kHz in 5 kHz steps.
Cross-Core Interferences to DFC
Figure 2 shows the CIS score emerging from the interferences
induced by FOC to the DFC interrupt for all test frequencies. The
figure shows the maximum of the average CIS score to be 4.2%
at 30 kHz. This means that the IPC of the DFC execution suffers
from an average slowdown of 4.2% at this PWM frequency. Also
the maximum interference of 6.8% is reached at this test
frequency.
Cross-Core Interferences to FOC
Cross core Interferences to FOC The interferences affecting FOC
execution is depicted in Figure3.Both the average and the
maximum CIS score reach their peak values at 40 kHz with 5.4%
and 6.5%, respectively.
Runtime Comparison
Figure 4 shows a comparison between the runtime FOC for a
genuine parallel execution on the multi-core system and a
concurrent execution on a single-core system. The space
between both graphs illustrates the extent of the runtime
extension between both systems, that is to say, the extension due
to preemptive scheduling as compared to the extension caused by
cross-core interference. Real parallel execution enables a
substantially shorter runtime for each frequency.
Band width of the FOC Control
The reduction of CPU cycles needed to run FOC on the multi-core
systems results in a lower number of passing DFC frames for each
FOC execution. As a result, more new presets from the FOC control
loop for the generation of the PWM signals can be provided to DFC
in a given time. Such a higher frequency of FOC contributes to a
more precise speed control of the PMSM. Figure 5 illustrates the
possible fFOC Cycle obtained for each PWM frequency without the
need to drop data due to over utilization.
Conclusion and future work
The implementation of sensorless methods to operate electrical
drives causes a high load on typically used embedded processing
units. This limits the possibilities to implement enhanced applications
on such systems. Embedded multi-core microprocessors are a
potential alternative for pro-viding the performance necessary to
raise the function density. However, cross-core interference might
impair the performance and reliability of such applications. To
quantify these effects, we have analysed the interference for an
application that implements basic functionalities for the sensorless
and speed controlled drive of a PMSM. This has been carried out on
a safety-critical multi-core platform with industrial components to
increase the validity of the results for practical use.
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