State and Finite State Machines
Hakim Weatherspoon
CS 3410, Spring 2013
Computer Science
Cornell University
See P&H Appendix C.7. C.8, C.10, C.11
Big Picture: Building a Processor
memory
+4
inst
register
file
+4
=?
PC
control
offset
new
pc
alu
cmp
target
imm
extend
A Single cycle processor
addr
din
dout
memory
Review: Efficiency and Generality
• We can generalize 1-bit Full Adders to 32 bits, 64 bits …
A3
B3
A2
B2
A1 B 1
A0
B0
C0
S3
S2
S1
S0
Review: Efficiency and Generality
• We can generalize 1-bit Full Adders to 32 bits, 64 bits …
• How long does it take to compute a result?
• Can we store the result?
B3
B2
B1
B0
mux
A3
A2
mux
A1
mux
A0
mux
0=add
1=sub
over
flow
S3
S2
S1
S0
Performance
Combinational
Logic
tcombinational
outputs
expected
inputs
arrive
Speed of a circuit is affected by the number of
gates in series (on the critical path or the
deepest level of logic)
4-bit Ripple Carry Adder
A 3 B3
A2 B2
C3
C4
S3
A1 B1
C2
S2
A0 B0
C1
S1
Carry ripples from lsb to msb
•
•
•
First full adder, 2 gate delay
Second full adder, 2 gate delay
…
C0
S0
Stateful Components
Until now is combinatorial logic
• Output is computed when inputs are present
• System has no internal state
• Nothing computed in the present can depend on
what happened in the past!
Inputs
N
Combinational
circuit
M
Need a way to record data
Need a way to build stateful circuits
Need a state-holding device
Finite State Machines
Outputs
Goals for Today
State
• How do we store one bit?
• Attempts at storing (and changing) one bit
–
–
–
–
Set-Reset Latch
D Latch
D Flip-Flops
Master-Slave Flip-Flops
• Register: storing more than one bit, N-bits
Basic Building Blocks
• Decoders and Encoders
Finite State Machines (FSM)
• How do we design logic circuits with state?
• Types of FSMs: Mealy and Moore Machines
• Examples: Serial Adder and a Digital Door Lock
Goal
How do we store store one bit?
First Attempt: Unstable Devices
B
C
A
First Attempt: Unstable Devices
B
0
1
10
A
Does not work!
• Unstable
• Oscillates wildly!
C
01
Second Attempt: Bistable Devices
• Stable and unstable equilibria?
A
A Simple Device
B
In stable state, A = B
0
A
1
1
B
A
How do we change the state?
0
B
Third Attempt: Set-Reset Latch
S
A
Q
Q
B
R
Third Attempt: Set-Reset Latch
S
R
0
0
0
1
1
0
1
1
Q Q
S
Q
Q
R
Set-Reset (S-R) Latch
Stores a value Q and its complement
Third Attempt: Set-Reset Latch
S
0
Q
A B OR
NOR
0 0 0
1
0 1 1
0
1 0 1
0
1 1 1
Set-Reset (S-R) Latch
Stores a value Q and its complement
0
1
0
Q will be 0 if R is 1
S
R
0
0
0
1
1
0
1
1
Q Q
0?
1?
Q
1
R
𝑸will be 1
Third Attempt: Set-Reset Latch
S
1
Q
A B OR
NOR
0 0 0
1
0 1 1
0
1 0 1
0
1 1 1
Set-Reset (S-R) Latch
Stores a value Q and its complement
0
0
1
Q will be 1
Q
S
R
0
0
0
1
0
1
1
0
1?
0?
1
1
0
Q Q
R
𝑸will be 0 if S is 1
What are the values for Q and Q?
a)
b)
c)
d)
0 and 0
0 and 1
1 and 0
1 and 1
Third Attempt: Set-Reset Latch
S
1 0
Q
A B OR
NOR
0 0 0
1
0 1 1
0
1 0 1
0
1 1 1
Set-Reset (S-R) Latch
Stores a value Q and its complement
0
0
1
If Q is 1, will stay 1
if Q is 0, will stay 0
S
R
Q Q
0
0
Q? Q?
0
1
0
1
1
0
1
0
1
1
Q
0
R
If 𝑸 is 0 will stay 0
If 𝑸 is 1 will stay 1
Third Attempt: Set-Reset Latch
S
1
Q
A B OR
NOR
0 0 0
1
0 1 1
0
1 0 1
0
1 1 1
Set-Reset (S-R) Latch
Stores a value Q and its complement
0
0
0
Q will be 0 since R is 1
Q
S
R
Q Q
0
0
Q Q
0
1
0
1
1
0
1
0
1
1
?
?
1
R
𝑸 will be 0 since S is 1
What happens when S,R changes from 1,1 to 0,0?
Third Attempt: Set-Reset Latch
S
10
A B OR
NOR
0 0 0
1
0 1 1
0
1 0 1
0
1 1 1
Set-Reset (S-R) Latch
Stores a value Q and its complement
0
01
0 1
0
Q
Q
0 1 0 1
R
1 0
S
R
Q Q
0
0
Q Q
0
1
0
1
What happens when S,R changes from 1,1 to 0,0?
1
0
1
0
1
1
Q and Q become unstable and will oscillate wildly
between values 0,0 to 1,1 to 0,0 to 1,1 …
forbidden
? ?
Third Attempt: Set-Reset Latch
S
Q
Q
R
S
R
Q Q
0
0
Q Q
0
1
0
1
reset
1
0
1
0
set
1
1
forbidden
hold
S
Q
R
Q
Set-Reset (S-R) Latch
Stores a value Q and its complement
Takeaway
Set-Reset (SR) Latch can store one bit and we can
change the value of the stored bit. But, SR Latch
has a forbidden state.
Next Goal
How do we avoid the forbidden state of S-R Latch?
Fourth Attempt: (Unclocked) D Latch
D
D
S
Q
Fill in the truth table?
Q
R
S
Q
R
Q
D Q Q
0
1
A B OR
NOR
0 0 0
1
0 1 1
0
1 0 1
0
1 1 1
0
Fourth Attempt: (Unclocked) D Latch
D
D
S
Q
Q
R
S
Q
R
Q
D Q Q
Fill in the truth table?
0
0
1
Data (D) Latch
1
1
0
• Easier to use than an SR latch
• No possibility of entering an undefined state
When D changes, Q changes
– … immediately (…after a delay of 2 Ors and 2 NOTs)
Need to control when the output changes
A B OR
NOR
0 0 0
1
0 1 1
0
1 0 1
0
1 1 1
0
Takeaway
Set-Reset (SR) Latch can store one bit and we can
change the value of the stored bit. But, SR Latch
has a forbidden state.
(Unclocked) D Latch can store and change a bit like
an SR Latch while avoiding the forbidden state.
Next Goal
How do we coordinate state changes to a D Latch?
Clocks
Clock helps coordinate state changes
• Usually generated by an oscillating crystal
• Fixed period; frequency = 1/period
clock
high
falling
edge
1
0
clock
period
clock
low
rising
edge
Clock Disciplines
Level sensitive
• State changes when clock is high (or low)
Edge triggered
• State changes at clock edge
positive edge-triggered
negative edge-triggered
Clock Methodology
Clock Methodology
•Negative edge, synchronous
clk
tcombinational
compute
tsetup thold
save
compute
save compute
– Edge-Triggered: Signals must be stable near falling clock edge
•Positive edge synchronous
Fifth Attempt: D Latch with Clock
D
S
Q
R Q
Fifth Attempt: D Latch with Clock
D
clk
S
Q
R Q
Fill in the truth table
clk D
0
0
0
1
1
0
1
1
Q
Q
Fifth Attempt: D Latch with Clock
D
S
Q
R Q
clk
Fill in the truth table
Q
Q
0
Q
Q
0
1
Q
Q
1
0
0
1
1
1
1
0
clk D
S R Q
Q
0 0 Q
Q
hold
0
0 1 0
1
reset
1 0 1
0
set
1 1
forbidden
Fifth Attempt: D Latch with Clock
D
clk
clk
D
Q
S
Level Sensitive D Latch
Clock high:
set/reset (according to D)
Clock low:
keep state (ignore D)
Q
R Q
clk D
Q
Q
0
0
Q
Q
0
1
Q
Q
1
0
0
1
1
1
1
0
Sixth Attempt: Edge-Triggered D Flip-Flop
D
clk
clk
D
X
Q
1
D
Q
0
X D Q
1
Q
cL
0
D Flip-Flop
Q •Edge-Triggered
•Data captured when clock
Q is high
c
•Output changes only on
falling edges
Activity#1: Fill in timing graph and values for X and Q
0
L
Q
Sixth Attempt: Edge-Triggered D Flip-Flop
D
clk
10
01
D
Q
L
Q
01
X D Q
01
Q
cL
c
clk
D
X
Q
01
D Flip-Flop
Q •Edge-Triggered
•Data captured when clock
Q is high
•Output changes only on
falling edges
Takeaway
Set-Reset (SR) Latch can store one bit and we can
change the value of the stored bit. But, SR Latch has a
forbidden state.
(Unclocked) D Latch can store and change a bit like an
SR Latch while avoiding a forbidden state.
An Edge-Triggered D Flip-Flip (aka Master-Slave D FlipFlip) stores one bit. The bit can be changed in a
synchronized fashion on the edge of a clock signal.
Next Goal
How do we store more than one bit, N bits?
Registers
D0
D1
D2
Register
•D flip-flops in parallel
•shared clock
•extra clocked inputs:
write_enable, reset, …
D3
4
clk
4-bit
reg 4
clk
Takeaway
Set-Reset (SR) Latch can store one bit and we can
change the value of the stored bit. But, SR Latch has a
forbidden state.
(Unclocked) D Latch can store and change a bit like an
SR Latch while avoiding a forbidden state.
An Edge-Triggered D Flip-Flip (aka Master-Slave D FlipFlip) stores one bit. The bit can be changed in a
synchronized fashion on the edge of a clock signal.
An N-bit register stores N-bits. It is be created with N
D-Flip-Flops in parallel along with a shared clock.
An Example: What will this circuit do?
4
16
Decoder
4
4-bit
reg
Clk
4
+1
4
An Example: What will this circuit do?
Reset
Run
4
WE R
4
4-bit
reg
16
Decoder
A[4] 1 = 0001 =B[4]
4
Cout
+1
S[4]
Clk
4
Decoder Example: 7-Segment LED
7-Segment LED
d7 d6
d5 d4
d3 d2
d1 d0
• photons emitted when
electrons fall into
holes
Decoder Example: 7-Segment LED
7-Segment LED
d7 d6
d5 d4
d3 d2
d1 d0
• photons emitted when
electrons fall into
holes
7LED decode
Decoder Example: 7-Segment LED Decoder
3 inputs
• encode 0 – 7 in
binary
7 outputs
• one for each LED
7 Segment LED Decoder Implementation
b2 b1 b0 d6 d5 d4 d3 d2 d1 d0
0 0 0
0 0 1
d2
0 1 0
d0
d3
0 1 1
d4
1 0 0
d6
d5
1 0 1
1 1 0
1 1 1
d1
1
0
0
0
0
1
1
7 Segment LED Decoder Implementation
b2 b1 b0 d6 d5 d4 d3 d2 d1 d0
0 0 0
1
1
1
0
1
1
1
0 0 1
1
0
0
0
0
0
1
0 1 0
0
1
1
1
0
1
1
0 1 1
1
1
0
1
0
1
1
1 0 0
1
0
0
1
1
0
1
1 0 1
1
1
0
1
1
1
0
1 1 0
1
1
1
1
1
1
0
1 1 1
1
0
0
0
0
1
1
d2
d1
d0
d3
d4
d6
d5
Basic Building Blocks We have Seen
2N
N
N
N
binary
decoder
...
binary
encoder
N
2N
N
0
1
2
Multiplexor
N
2M-1
M
N
Encoders
0
1
3
4
5
6
7
...
N
...
N Input wires
encoder
2
Log2(N) outputs wires
e.g. Voting:
Can only vote for one out of N
candidates, so N inputs.
But can encode vote efficiently
with binary encoding.
Example Encoder Truth Table
a
b
1
o0
2
o1
c
3
d
4
o2
A 3-bit
encoder
with 4 inputs
for simplicity
a
b
c
d
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
Example Encoder Truth Table
a
b
1
o0
2
o1
c
3
d
4
a
b
c
d
o2
o1
o0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
1
1
0
0
o2
A 3-bit
encoder
with 4 inputs
for simplicity
• o2 = abcd
• o1 = abcd + abcd
• o0 = abcd + abcd
detect
Basic Building Blocks Example: Voting
8
enc
3
7LED
decode
Ballots
The 3410 optical scan
vote reader
machine
7
Recap
We can now build interesting devices with sensors
• Using combinatorial logic
We can also store data values (aka Sequential Logic)
• In state-holding elements
• Coupled with clocks
Administrivia
Make sure to go to your Lab Section this week
Design Doc for Lab1 due Monday, Feb 4th
Completed Lab1 due in two weeks, Monday, Feb 11th
Work alone
Homework1 is out
Due in one week, next Wednesday, start early
Homework Help Session: Thursday and Monday, B14 HLN, 6-8pm
Work alone
BUT, use your resources
• Lab Section, Piazza.com, Office Hours, Homework Help Session,
• Class notes, book, Sections, CSUGLab
Administrivia
Check online syllabus/schedule
• http://www.cs.cornell.edu/Courses/CS3410/2013sp/schedule.html
Slides and Reading for lectures
Office Hours
Homework and Programming Assignments
Prelims (in evenings):
• Tuesday, February 26th
• Thursday, March 28th
• Thursday, April 25th
Schedule is subject to change
Goals for Today
State
• How do we store one bit?
• Attempts at storing (and changing) one bit
–
–
–
–
Set-Reset Latch
D Latch
D Flip-Flops
Master-Slave Flip-Flops
• Register: storing more than one bit, N-bits
Basic Building Blocks
• Decoders and Encoders
Finite State Machines (FSM)
• How do we design logic circuits with state?
• Types of FSMs: Mealy and Moore Machines
• Examples: Serial Adder and a Digital Door Lock
Finite State Machines
Next Goal
How do we design logic circuits with state?
Finite State Machines
An electronic machine which has
• external inputs
• externally visible outputs
• internal state
Output and next state depend on
• inputs
• current state
Abstract Model of FSM
Machine is
M = ( S, I, O,  )
S:
Finite set of states
I:
Finite set of inputs
O: Finite set of outputs
:
State transition function
Next state depends on present input and
present state
Automata Model
Registers
Finite State Machine
•
•
•
•
Current
State
Input
inputs from external world
outputs to external world
internal state
combinational logic
Comb.
Logic
Output
Next State
FSM Example
down/on
input/output
state
down/on
up/off
B
A
start
state
up/off
Legend
down/off
up/off
C
Input: up or down
Output: on or off
States: A, B, C, or D
D
up/off
up/off
FSM Example
down/on
input/output
state
down/on
up/off
B
A
start
state
up/off
Legend
down/off
up/off
C
Input: = up or = down
Output: = on or = off
States: = A, = B, = C, or = D
D
up/off
up/off
FSM Example
1/1
i0i1i2…/o0o1o2…
01
00
S1S0
1/1
0/0
S1S0
Legend
0/0
0/0
10
Input: 0=up or 1=down
1/0
Output: 1=on or 1=off
States: 00=A, 01=B, 10=C, or 11=D
0/0
11
1/0
Mealy Machine
Registers
General Case: Mealy Machine
Current
State
Input
Comb.
Logic
Output
Next State
Outputs and next state depend on both
current state and input
Moore Machine
Registers
Special Case: Moore Machine
Current
State
Comb.
Logic
Output
Input
Comb.
Logic
Next State
Outputs depend only on current state
Moore Machine FSM Example
down
input
state
out
up
B
A
on
off
start
out
up
Legend
up
C
down
D
off
Input: up or down
Output: on or off
States: A, B, C, or D
down
off
up
up
Mealy Machine FSM Example
down/on
input/output
state
down/on
up/off
B
A
start
state
up/off
Legend
down/off
up/off
C
Input: up or down
Output: on or off
States: A, B, C, or D
D
up/off
up/off
Activity#2: Create a Logic Circuit for a Serial Adder
Add two infinite input bit streams
• streams are sent with least-significant-bit (lsb) first
• How many states are needed to represent FSM?
• Draw and Fill in FSM diagram
…10110
…00101
…01111
Strategy:
(1) Draw a state diagram (e.g. Mealy Machine)
(2) Write output and next-state tables
(3) Encode states, inputs, and outputs as bits
(4) Determine logic equations for next state and outputs
FSM: State Diagram
a …10110
b …01111
…00101 z
Two states: S0 (no carry in), S1 (carry in)
Inputs: a and b
Output: z
• z is the sum of inputs a, b, and carry-in (one bit at a time)
• A carry-out is the next carry-in state.
• .
FSM: State Diagram
__/_
__/_
S0
__/_
__/_
__/_
__/_
S1
__/_
__/_
a …10110
b …01111
…00101 z
Two states: S0 (no carry in), S1 (carry in)
Inputs: a and b
Output: z
• z is the sum of inputs a, b, and carry-in (one bit at a time)
• A carry-out is the next carry-in state.
• Arcs labeled with input bits a and b, and output z
FSM: State Diagram
11/0
00/0
S0
10/1
00/1
01/1
11/1
S1
10/0
01/0
a …10110
b …01111
…00101 z
Two states: S0 (no carry in), S1 (carry in)
Inputs: a and b
Output: z
• z is the sum of inputs a, b, and carry-in (one bit at a time)
• A carry-out is the next carry-in state.
• Arcs labeled with input bits a and b, and output z (Mealy Machine)
Serial Adder: State Table
11/0
00/0
S0
10/1
a
b
Current
state
z
00/1
01/1
S1
10/0
11/1
01/0
Next
state
(2) Write down all input and
state combinations
Serial Adder: State Table
11/0
00/0
S0
10/1
a
b
Current
state
z
0
0
S0
0
S0
0
1
S0
1
S0
1
0
S0
1
S0
1
1
S0
0
S1
0
0
S1
1
S0
0
1
S1
0
S1
1
0
S1
0
S1
1
1
S1
1
S1
00/1
01/1
S1
10/0
11/1
01/0
Next
state
(2) Write down all input and
state combinations
Serial Adder: State Assignment
11/0
00/0
0
10/1
a
b
s
z
s'
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
1
1
1
1
00/1
01/1
10/0
1
11/1
01/0
(3) Encode states, inputs, and
outputs as bits
Two states, so 1-bit is sufficient
• A single flip-flop will encode the
state
Serial Adder: Circuit
Next
State
s'
D
Q
Current
State
s
a
b
Input
a
b
s
z
s'
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
1
1
1
1
Comb.
Logic
Output
z
Next State
s'
(4) Determine logic equations
for next state and outputs
Combinational Logic Equations
z = abs + abs + abs + abs
s’ = abs + abs + abs + abs
Sequential Logic Circuits
Next
State
s'
D
Q
Current
State
s
a
b
Input
Comb.
Logic
Output
z
Next State
s'
z = abs + abs + abs + abs
s’ = abs + abs + abs + abs
Strategy:
.
(1) Draw a state diagram (e.g.
. Mealy Machine)
(2) Write output and next-state
tables
.
(3) Encode states, inputs, and outputs as bits
(4) Determine logic equations for next state and outputs
Example #2: Digital Door Lock
Digital Door Lock
Inputs:
• keycodes from keypad
• clock
Outputs:
• “unlock” signal
• display how many keys pressed so far
Door Lock: Inputs
Assumptions:
• signals are synchronized to clock
• Password is B-A-B
K
A
B
K A B Meaning
0 0 0 Ø (no key)
1 1 0 ‘A’ pressed
1 0 1 ‘B’ pressed
Door Lock: Outputs
Assumptions:
• High pulse on U unlocks door
D3D2D1D0
4 LED 8
dec
U
Strategy:
(1) Draw a state diagram (e.g. Moore Machine)
(2) Write output and next-state tables
(3) Encode states, inputs, and outputs as bits
(4) Determine logic equations for next state and outputs
Door Lock: Simplified State Diagram
Ø
Ø
G1
”1”
“A”
“B”
G2
”2”
else
“B”
else
G3
”3”, U
any
Idle
”0”
Ø
else
any
B1
”1”
else B2
”2”
Ø
else
B3
”3”
Ø
(1) Draw a state diagram (e.g. Moore Machine)
Door Lock: Simplified State Diagram
Ø
Ø
G1
”1”
“A”
else
“B”
G2
”2”
else
“B”
G3
”3”, U
any
Idle
”0”
Ø
else
else
B1
”1”
else B2
”2”
Ø
Ø
(1) Draw a state diagram (e.g. Moore Machine)
Door Lock: Simplified State Diagram
Ø
Ø
G1
”1”
“A”
else
“B”
G2
”2”
else
“B”
Cur.
State
Idle
”0”
Ø
else
else
B1
”1”
else B2
”2”
Ø
Ø
(2) Write output and next-state tables
G3
”3”, U
any
Output
Door Lock: Simplified State Diagram
Ø
Ø
G1
”1”
“A”
else
“B”
G2
”2”
else
Idle
”0”
Ø
else
else
B1
”1”
else B2
”2”
Ø
Ø
“B”
Cur.
State
Idle
G1
G2
G3
B1
B2
(2) Write output and next-state tables
G3
”3”, U
any
Output
“0”
“1”
“2”
“3”, U
“1”
“2”
Door Lock: Simplified State Diagram
Ø
Cur. State
Ø
G1
”1”
“A”
else
“B”
G2
”2”
“B”
else
Idle
”0”
Ø
else
else
B1
”1”
else B2
”2”
Ø
Ø
(2) Write output and next-state tables
Input
Next State
G3
”3”, U
any
Door Lock: Simplified State Diagram
Ø
G1
”1”
“A”
else
“B”
Idle
”0”
Ø
else
else
B1
”1”
else
Cur. State
Ø
Idle
G2 Idle “B”
”2”Idle
elseG1
G1
G1
G2
G2
G2
G3
B2 B1
”2” B1
B2
Ø
B2
Ø
(2) Write output and next-state tables
Input
Next State
Ø
Idle
“B”G3
G1
”3”, U
“A”
B1
Ø
any G1
“A”
G2
“B”
B2
Ø
B2
“B”
G3
“A”
Idle
any
Idle
Ø
B1
K
B2
Ø
B2
K
Idle
State Table Encoding
SCur.
SState
S0
2
1
0 Idle
0 0
0 G1
0 1
0 G2
1 0
0 G3
1 1
1 B1
0 0
1 B2
0 1
D3
0
0
0
0
0
0
DOutput
2 D1 D0
0 “0”
0 0
0 “1”
0 1
0 “2”
1 0
0“3”,
1 U1
0 “1”
0 1
0 “2”
1 0
U
0
0
0
1
0
0
Cur.
S2 SState
1 S0
0 Idle
0 0
0 Idle
0 0
0 Idle
0 0
0 G1
0 1
0 G1
0 1
0 G1
0 1
0 G2
1 0
0 G2
1 0
0 G2
1 0
0 G3
1 1
1 B1
0 0
1 B1
0 0
1 B2
0 1
1 B2
0 1
K Input
A
B
0
Ø
0
0
1 “B”
0
1
1 “A”
1
0
0
Ø
0
0
1 “A”
1
0
1 “B”
0
1
0
Ø
0
0
1 “B”
0
1
1 “A”
1
0
x any
x
x
0
Ø
0
0
1
K
x
x
0
Ø
0
0
1
K
x
x
State
S2 S 1 8 S0
4 Meaning
K
A
B
D3D2D1D0
dec 0 0
Idle
0
0 0 0 Ø (no key)
U 0 0 1
G1
1 1 0 ‘A’ pressed
K 0
G2
0
1
1 0 1 ‘B’ pressed
A
G3
0 1 1
B
B1
1 0 0
(3) Encode
states,
and outputs as bits
B2
1 0 inputs,
1
S’
Next
2 S’State
1 S’0
0 Idle
0 0
0 G1
0 1
1 B1
0 0
0 G1
0 1
0 G2
1 0
1 B2
0 1
0 B2
1 0
0 G3
1 1
0 Idle
0 0
0 Idle
0 0
1 B1
0 0
1 B2
0 1
1 B2
0 1
0 Idle
0 0
3bit
Reg
S2-0
D3-0
4
dec
Door Lock: Implementation
U
clk
S2-0
K
A
S’2-0
B
U = S2S1S0
D0 = S2S1S0 + S2S1S0 + S2 S1S0
D1 = S2S1S0 + S2S1S0 + S2S1S0
S2
0
0
0
0
1
1
S1
0
0
1
1
0
0
S0
0
1
0
1
0
1
D3
0
0
0
0
0
0
D2
0
0
0
0
0
0
D1
0
0
1
1
0
1
D0
0
1
0
1
1
0
(4) Determine logic equations for next state and outputs
U
0
0
0
1
0
0
Door Lock: Implementation
3bit
Reg
clk
S2-0
K
A
B
K
0
1
1
0
1
1
0
1
1
x
0
1
0
1
dec
S2-0
S2 S1 S0
4
D03-00 0
0 0 0
U
0 0 0
0 0 1
0 0 1
0 0 1
0S’2-0
1 0
0 1 0
0 1 0
0 1 1
1 0 0
1 0 0
1 0 1
1 0 1
A
0
0
1
0
1
0
0
0
1
x
0
x
0
x
B
0
1
0
0
0
1
0
1
0
x
0
x
0
x
S’2 S’1 S’0
0 0 0
0 0 1
1 0 0
0 0 1
0 1 0
1 0 1
0 1 0
0 1 1
0 0 0
0 0 0
1 0 0
1 0 1
1 0 1
0 0 0
S2’ = S2S1S0KAB + S2S1S0KAB + S2S1S2KAB + S2S1S0K + S2 S1S0 KAB
3bit
Reg
S2-0
D3-0
4
dec
Door Lock: Implementation
U
clk
S2-0
K
A
S’2-0
B
Strategy:
(1) Draw a state diagram (e.g. Moore Machine)
(2) Write output and next-state tables
(3) Encode states, inputs, and outputs as bits
(4) Determine logic equations for next state and outputs
Summary
We can now build interesting devices with sensors
• Using combinational logic
We can also store data values
• Stateful circuit elements (D Flip Flops, Registers, …)
• Clock to synchronize state changes
• State Machines or Ad-Hoc Circuits