Electronics for large LAr TPC’s
F. Pietropaolo (ICARUS Collaboration)
CRYODET Workshop
LNGS, 13-14 March 2006
Outline
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The ICARUS front-end electronics
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Alternatives solutions
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Layout in T600 module (analogue + digital)
Performance and limitations
Possible upgrades for multi-kton detectors
Front-end inside vs outside LAr
Analog-to-digital serial converter
Summary
13-14 March 2006
CryoDet workshop, LNGS
2
The ICARUS T600 experience
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The T600 DAQ system (5·104 channels), designed in
Padova, engineered and built by CAEN, has proven to
perform satisfactory during the 2001 test run in Pavia.
It consists of an analogue front-end followed by a
multiplexed AD converter (10 bit) and by a digital VME
module performing local storage, hit finding and data
compression.
From the experience gained with the T600 operation,
an R&D phase is underway in view of an upgrade for a
multi-kton detector with ~ n·105 channels (better S/N,
larger integration, lower cost).
13-14 March 2006
CryoDet workshop, LNGS
3
The ICARUS read-out principle
m.i.p. ionization
~ 6000 e-/mm
Time
Edrift ~ 500 V/cm
Drift direction
Hit
finder
Mux
8:1
Low-noise
amplifiers
Front-end
13-14 March 2006
FADC
Memory
400ns
n x 4kB
multi-event
circular buffer
Continuous
waveform
recording
Daedalus
CryoDet workshop, LNGS
To storage
4
The induction signals
Electrons
path
Ionizing track
Induced current
Edrift
Induced charge
T=0
Drift
u-t view
E1
Induction 1
v-t view
d
E2
Induction 2
w-t view
Charge
= area
d
Collection
Charge
= ampl.
p
Drift time
Drift time
• ICARUS T600: three wire planes (pitch 3mm, separation 3mm)
13-14 March 2006
Edrift = 500 V/cm
Mip signal ~ 12000 e- (inc. recombinantion)
Electron drift velocity ~ 1.5 mm/s
Typical grid transit time ~ 2-3 s
CryoDet workshop, LNGS
5
Requirements for the preamplifier
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Need of very low noise amplifier:
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No amplification around sense wires
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Induced charge ~ 104 electrons
Large input capacitance (CD)
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Wires (20 pF/m) + cables (50 pF/m)
In T600 CD ~ 300-400pF
Serial noise (proportional to CD)
dominates over parallel noise
(proportional only to signal
bandwidth)
esn 
2
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High trans-conductance (gm) input
device required to ensure acceptable
Signal-to Noise level (S/N ~ 10)
S /N 

13-14 March 2006
CryoDet workshop, LNGS
1
gm
q
CF
q


CF esn  CD esn  CD
6
Choice of the active input device
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Bipolar transistors
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VLSI-CMOS
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gm ≈ 400mS @ Ic ≈ 10 mA (Amplification merit factor gm·Zout ≈ 3-4·105)
BUT: parallel noise density ≈ 2 pA / √Hz too high (with a typical LAr signal
bandwidth of ~ 1 MHz gives unacceptable noise contribution)
Extremely low gm
jFET
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Good gm ≈ 40mS @ Ids ≈ 10 mA (Amplification merit factor gm·Zout ≈ 3-4·104)
negligible parallel noise density ≈ 0.001 pA / √Hz
ICARUS choice since 1986:
charge sensitive preamplifier with high gm jFET input stage
13-14 March 2006
CryoDet workshop, LNGS
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The ICARUS T600 preamplifier
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Custom IC in BiCMOS technology
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Classical Radeka integrator
External input stage jFET’s
 Two IF4500 (Interfet) or
BF861/2/3 (Philips) in parallel
Two versions:
“quasi-current” mode: RfCf ≈ 1.6s (collection +
first induction)
“quasi-charge” mode: RfCf ≈ 30s (mid induction)
Cz
R2
R1
to increase gm (50-60 mS)
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External feed-back network
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External baseline restorer circuit
Identical symmetrical layout
guarantees identical electrical
behavior
13-14 March 2006
R3
Cu
Allow sensitivity and decay time
optimization
High value f.b. resistor (100M)
reduce parallel noise
Two channels per IC
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R4
Cs
Rf
Ra
Cf
AGND
Rp
Sensitivity ≈ 6 mV/fC
Dynamic range > 200 fC
Linearity < 0.5% @ full scale
Gain uniformity < 3%
E.N.C. ≈ (350 + 2.5 x CD) el ≈ 1200 el. @ 350pF
Power consumption ≈ 40 mW
CryoDet workshop, LNGS
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Layout of front-end electronics
UHV
Feed-through
(18x32ch.)
Liquid argon
H.V. (<±500 V)
VME board (18/crate)
Gas
Sense wires
(4-9m, 20pF/m)
4 Multiplexers
(400ns x 8ch.)
Twisted pair cables
(~5m, 50pF/m)
Decoupling
Boards
(32 ch.)
Front-end
amplifiers
(32/board)
F
A
D
C
10bit FADC
400ns sampling
1mV/ADC
ICARUS T600: ~ 54000 channels — 1720 boards — 96 crates
Cost of the full electronic chain: ~ 80 € / channel
13-14 March 2006
CryoDet workshop, LNGS
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The ICARUS T600 read-out chain
CAEN-V789 board: 2 Daedalus VLSI * 16 input channels
(local self-trigger & zero suppression) + memory buffers +
data out on VME bus
Signal UHV feed-through:
576 channels (18 connectors x 32)
+ HV wire biasing
CAEN-V791 board: 32 pre-amplifiers +
4 multiplexers (8:1) + 4 FADC’s (10 bits - 20 MHz)
13-14 March 2006
CryoDet workshop, LNGS
Decoupling board:
HV distribution and
signal input
10
The T600 electronic racks
13-14 March 2006
CryoDet workshop, LNGS
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The analogue board V791
FADC’s
Multiplexers
Digital link
Preamplifiers
QuickTime™ and a
TIFF (Uncompressed) decompressor
are needed to see this picture.
BiCMOS
IC layout
Input signal
connector
Output of
analogue sum
Shielding of
front-end
13-14 March 2006
CryoDet workshop, LNGS
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Performance of the V791 boards
V791C
V791Q
Collection
Mid. Induction
1st Induction
1st Induction
13-14 March 2006
CryoDet workshop, LNGS
128 wires/view
1024 samples
400 ns/sample
13
Performance of the V791C board
Single wire waveforms (horiz. axis unit = 400 ns)
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60
44
42
40
38
36
34
32
30
28
26
m.i.p. ≈ 12 ADC counts
(3 mm) FWHM ≈ 5 µs
Collection
50
45
40
35
30
0
50
100
150
200
250
40
1st Induction
35
30
25
20
15
20
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Test pulse
(6 mm m.i.p)
24 ADC counts
FWHM ≈ 5 µs
55
70
120
170
220
25
300
38
37
36
35
34
33
32
31
30
29
28
120
350
Noise
400
450
RMS ≈ 1.3 ADC counts
Coherent noise due to layout not negligible!
170
220
270
320
370
RMS noise on T600 = 1.3 - 1.7 ADC counts (due to difficult environment in Pavia)
13-14 March 2006
CryoDet workshop, LNGS
14
Performance of the V791Q board
Single wire waveforms (horiz. axis unit = 400 ns)
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60
44
42
40
38
36
34
32
30
28
26
Mid. Induction
55
50
45
40
m.i.p. ≈ 10 ADC counts
(3 mm) FWHM ≈ 5 µs
0
50
100
150
200
250
35
30
25
20
200
38
36
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Pulse height & shape from mid. plane wires very
similar to those from collection plane wires.
High frequency S/N also comparable.
Low frequency minimized by baseline restorer.
Test pulse
(6 mm m.i.p.)
24 ADC counts
RC ≈ 30 µs
34
250
Noise
300
350
400
450
500
RMS (h.f.) ≈ 1.2 ADC counts
32
30
28
26
24
22
150
200
250
300
350
400
450
500
Low frequency noise visible but not dangerous!
13-14 March 2006
CryoDet workshop, LNGS
15
Drift time (1.5m)
Events from T300 semi module
Collection view
Drift time (1.5m)
Wire numbering (4.5m)
Induction2 view
Wire numbering (4.5m)
13-14 March 2006
CryoDet workshop, LNGS
16
Possible upgrades
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In a multi-kton LAr-TPC with the ICARUS read-out principle we
can foresee
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S/N close to T600
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Larger number of channels (~ n•105)
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Longer electrodes (larger input capacitance, more electronic noise)
But probably larger electrode pitch (more input charge)
Require integration, cost reduction
Present overall architecture fully satisfactory
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Improvement will focus on
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Input stage jFET
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Review IC design - Integrate more channels
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BiCMOS technology evolved since last IC design
Careful study of layout topology
Development of new hybrid sub module
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13-14 March 2006
Technology still state of the art
Optimization of number of input jFET to larger input capacitance
Hosting more amplification channels (e.g. 4 - 8)
And, possibly, the analogue-to-digital converter stage
CryoDet workshop, LNGS
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Electronics in LAr
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Deeply investigated within ICARUS collaboration (since 1988)
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Limited choice of active devices
working at LAr temperature
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U310 jFET
GAs-jFET (High Electron
Mobility Transistor technology)
Silicon jFET (High Resistive
Substrate technology)
Expected characteristics:
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Better S/N due to improved gm
at cryogenic temperature
Reliability at LAr temperature
Availability on the market
13-14 March 2006
CryoDet workshop, LNGS
Carrier
mobility
decrease
Pinch-off
increase
18
Pro & Contra
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Advantages
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Reduction of input capacitance due to cable absence
Reduction of micro-phonic noise (detector = Faraday cage)
Intrinsic improvement of S/N due to larger jFET gm at
cryogenic temperature
Disadvantages
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Inaccessibility during detector operation
Need of careful selection of components, extensive burn-in
and temperature cycles before installation to minimize
components failure
Design architecture and technology restricted by limited
choice of active components
Limit on power dissipation (< 100 mW/mm2 to avoid LAr
boil-off)
13-14 March 2006
CryoDet workshop, LNGS
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The TOTEM architecture
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Charge Integrator made on Thick Film
Hybrid technology with discrete jFET only (IF1330)
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Minimum active and passive components
Ability to drive long transmission line
Reduced power consumption
Minimum cable connections
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V0 
R0 qin

RL CF

Current signal from Positive Power Supply
Common Negative polarization
Characteristics
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Optimized for low detector capacitance
Sensitivity ≈ 0.45 mV/fC (0.9 A/fC)
Dynamic range ±1.5 pC
Linearity < 0.5% @ full scale
Input impedance ≈ 420 
Input capacitance ≈ 20 pF
E.N.C. ≈ (390 + 7 x CD) el
Power consumption ≈ 11 mW
13-14 March 2006
CryoDet workshop, LNGS
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Events with electronics in LAr
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Extensively used on the 50 liter LAr-TPC
Wire capacitance: ~ 15 pF
(horiz. axis unit = 400 ns)
74
Collection
72
70
68
66
mip ≈ 10 ADC
counts (2.54 mm)
FWHM ≈ 6 µs
Collection
64
62
60
58
200
66
Induction
65
250
300
350
400
450
RMS ≈ 0.7 ADC counts
Noise
64
63
62
61
60
59
180
260
340
420
500
Negligible low frequency noise !
13-14 March 2006
CryoDet workshop, LNGS
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The ICARUS experience
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Electronics in LAr studied for
sake of completeness
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Not a viable solution for large scale
detectors
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Inaccessibility, poor integration, cost
However
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TOTEM design could be improved
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HEMT replacing silicon jFET
jFET matrix on single chip
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13-14 March 2006
Technology commercially available
for low temperature application
E.g. INTERFET IPA300 amplifier
(serial noise density = 0.6 nV / √Hz,
80 mW dissipation)
CryoDet workshop, LNGS
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Analog-to-digital conversion
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Present architecture
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Serves sets of 16 channels
through analogue
multiplexers and 10 bit
FADC’s
Trade-off between sampling
speed and price
Two sets per V789 board (32 ch.)
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Total bandwidth = 800 Mbit/s
FADC sampling rate 20MHz
interleaved
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400 ns sampling time /
channel
40MHz digital output
Dissipated power ~ 500 mW
Components cost ~40 € / 16
channels
13-14 March 2006
CryoDet workshop, LNGS
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Compact serial AD converter
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New architecture based on 1-bit
serial converter
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Interesting characteristics
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Basic structure
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No need for multiplexing
Very low number of components
Resolution better than 10 bit
Commercially available chip
Low price (< 1 € / channel)
Four QUAD FLATPACK 4x4 mm2
components plus few glue logic
Sampling rate = 16 MHz
Dissipated power = 400mW
Data reconstruction
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Simple FIR filters could be
implemented
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In pipeline on FPGA / DSP
Off line after data storage
Test underway of 16 channel
prototype boards fully compatible
with present ICARUS data link
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Total bandwidth = 256 Mbit/s
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Serving multiples of 16 channels
13-14 March 2006
CryoDet workshop, LNGS
Upgradable to 800 Mbit/s if sampling
rate increased to 25 MHz and 32
channels
24
Serial ADC frequency response
16 sample FIR comb filter
equivalent to 10 bit resolution
8 sample FIR comb filter
equivalent to 8 bit resolution
25 MHz
16 MHz
Typical ICARUS signal bandwidth (~ 1 MHz)
better matched in 25 MHz case.
Marginal in the 16 MHZ case
13-14 March 2006
CryoDet workshop, LNGS
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Simulations
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Typical ICARUS signal waveform (~3 s width) digitized with Serial AD converter
FIR comb filter applied to recover signal shape (16 sample width)
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10 bit equivalent resolution
1 bit quantization noise
Continuous reconstruction (useful feature for signal analysis)
Input waveform
16 MHz
Continuous reconstruction
25 MHz
400ns sampled (cfr. FADC)
Slight pulse height reduction but area (= charge) unchanged
13-14 March 2006
CryoDet workshop, LNGS
26
Signals from LAr
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LAr signal waveforms (from oscilloscope) digitized with Serial AD
converter simulator
FIR comb filter applied to recover signal shape (16 sample width)
Quantization noise well within analogue noise level
Input waveform
16 MHz
Continuous reconstruction
25 MHz
400ns sampling
13-14 March 2006
CryoDet workshop, LNGS
27
Prototype board
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16 channels
16 MHz sampling rate
Data link compatible
with ICARUS DAQ
Effective throughput
256 Mbit/s
Charge
sensitive
preamplifiers
Digital link
13-14 March 2006
4 x 4 channel serial
AD converters
CryoDet workshop, LNGS
28
First signals from prototype
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Test pulse injected on on-board preamplifiers
Digitized signal recorded with ICARUS DAQ
Off-line signal reconstruction with FIR comb filter (16 sample width)
Input waveform
16 MHz
Continuous reconstruction
Zoom of gray
shaded area
400ns sampling
High preamp. noise due to present board layout (analogue/digital interference)
13-14 March 2006
CryoDet workshop, LNGS
29
Summary
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The ICARUS R&D on electronics for large LAr-TPC’s

Upgrade of the analogue front-end

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Possible alternative solution

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Development of a completely new cold amplifier (hybrid based on TOTEM
structure with jFET matrix or HEMT) for better S/N
Major drawback: inaccessibility, component reliability, cost
Upgrade of Analogue-to-digital conversion
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VLSI-CMOS technology for high channel integration excluded by simple S/N
requirements
Review of amplifier IC design could allow integrating more than two channel
per chip
Use of HEMT at input could help improving S/N
Serial-converter: promising alternative to Multiplexer + Flash ACD
Intrinsically simpler,more compact, cheaper
Comparable bandwidth and signal resolution
Review of the data link with digital buffers
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13-14 March 2006
Study the recent optical link development at LHC experiments to help defining
a suitable solution for the LAr-TPC environment
CryoDet workshop, LNGS
30