First Fab Report
Comments on various slides I have received on first reports
John Hudak
11-11-2014
First fab report is a learning assignment
• Only counts as 10% of grade – so the difference in a grade of 90 vs a grade
of 70 is only 2 points on your final grade.
• I expect you to use these comments to revise and improve your slides for
the final report. The final report counts more towards the final grade
• Slides are presented to learn from, not to embarrass anyone
• Many of my comments are common to many reports
• Everyone can create a PowerPoint presentation effortlessly
• Now it is time to focus on how the content is presented.
• Content should be enough for someone unfamiliar with your work to
understand what you did.
My comments are in the white
text box.
I expect the second report to
not have these issues
Slide background should be muted and not overwhelm the information
presented. Harsh colors for background on slides should be avoided.
Solar Cell
st
1
Fabrication
B Y T HO MA S DOA N
T H I S R E P O R T WA S S U B M I TT ED I N CO M P L I A NCE W I T H U N CC
P O L I C Y S TAT E M E NT # 10 5 T H E CO D E O F S T U D ENT AC A D E M I C
I N T E GR I TY, R EV I SED A U GU S T 24, 20 0 8
(HT T P :/ /WWW. LEGAL.UNCC .EDU/P OL IC IES/P S -105.HTML )
_ _ _ TD____. (S T U D ENT ’S I N I T I A L S)
Objective:
 Solar cell is : a semiconductor device that converts
the energy of sunlight into electric energy.
 The goal of this project was to fabricate a basic silicon solar cell
while working in a clean room environment.
 There are many clean room protocols that student should know
before starting the project such as hazardous materials
handling, and microelectronic fabrication processes.
This style format for the slides does not make maximum use of the area of the slide
for information.
ECGR 3090 Solar Cell First
Fabrication
http://i01.i.aliimg.com/photo/v1/493663835Round_Solar_Panel_15W_with_12V.jpg
Show your cell, not a commercial
cell
November 7, 2014
Deep Panara
This report was submitted in compliance with the UNCC Code of Student Academic Integrity (2013-2014 UNCC Catalog)
Diagram of Basic Silicon Solar Cell
Anti - Reflective Coating SiO2
Top Side
Conductor
Grid
Top Side
Conductor
Grid
Top Side
Conductor
Grid
Top Side
Conductor
Grid
Top Side
Conductor
Grid
N – Region Phosphorus Doped – Spin on Dopant
Silicon
P-Type (100) Prime Boron Doped
Needs aluminum as the top
and back conductor, eliminate
probes and conductive back
plate, not part of schematic
Conductive Base Plate
Back Side Conductor Metal
Top Side
Conductor
Grid
Avoid black
background
SOLAR CELL SCHEMATIC

Boron doped P-type silicon wafer

Spin on N-type Phosphorous Dopant

Top side conductor metal deposited
and grid photolithographed on

Backside conductor metal deposited

Anti-Reflective Si02 deposited
Avoid free hand sketches if possible
The main objective of this course was to use the process
described in the traveler to fabricate a working
photovoltaic cell in the clean room. The schematic for
this cell can be seen below.
Schematic OK, image
could be larger and
centered
9
Fabrication Photos
Piranha clean
Resistivity Testing
Number fabrication steps, larger
photos where possible. More detailed
descriptions, PECVD entire tool should
be shown instead of just the chamber
plate
Backside SI02 using PECVD

Four Point Probe


Wafer cleaning


Utilizing chemicals to
clean wafers
PECVD Backside SiO2
deposition


Measured resistivity
Deposited a SiO2 barrier
on the back of the wafer
P509 Spin on Dopant

N-type Dopant
application
Number steps – match steps to photos, captions for photos.
Photo is not for spin on dopant but PR spinning

N-Region Diffusion in furnace


Top side Aluminum sputtering


60 min @ 950C with oxygen
flow
Applied the top side
Aluminum layer to the wafer
via sputtering
UV Photolithography

Photoresist applied then
removed using UV light on a
pre drawn solar cell design
Number steps, match photos to steps, captions for photos,
photos should show entire tool, not just a small portion
Fabrication Continued
4.
5.
6.
BOE (Buffered Oxide Etch)
N Diffusion
Time and temp for N diffusion missing, wrong
photo for BOE, showing aluminum etch
Front Side Contact Aluminum
The expiration of the spin on
dopant was checked and
verified to be November 2014.
It was then spun on using the
P509 machine at 3K rpm for 10
seconds.
Once the dopant was on it was
cured at 120 degrees Celsius
and diffused using the furnace
seen to the right
14
Number steps, match photos to steps, need time and
temperature for furnace, photo poorly sized
Equipment Used in the Fabrication Process
Wafer Dryer
Sputtering Tool
Avoid black background,
list process steps, not
equipment
Trion PECVD
Fabrication Steps Continued

Next the students did N diffusion in the furnace at
950 C for 60 minutes

Next the students used Buffered Oxide Etch(BOE)
on the wafer for 5 minutes to remove the leftover
dopant

Again the students rinsed and dried the wafers

Next the students sputtered front side aluminum

With the aluminum on the students created a cell
mask and developed it on to the wafer
Reading Lab Manual

Using positive photoresist, a soft bake, exposure to
UV light, and developer the mask was transferred
to the wafer

Next the students hard baked the wafer at 90 C for
20 minutes
Number process steps, match steps to photos, replace “students”
with first person
Photoresist
Spinner
FABRICATION PROCESS PHOTOS
Dress up
4 point probe
Chemical Cleaning
Use whole slide for info, enlarge photos, better descriptions
Procedure of fabrication
5. N-region Deposition
6. N-region Diffusion
Need more info – spin on n type dopant, time and temperature for diffusion
SOLAR CELL MASK
Cell Size: 6.997 * 6.382cm = 45.355cm2
3mm width bus bars
1.25mm width fingers
Why all the wasted space? Use all available space.
Avoid black background on mask?
Top Conductor Mask Design
Avoid black background on mask,
very hard to see
Mask
Very hard to see. Needs
white background for mask
Review slides and
spelling before
submission
Taster Condition

 AM 1.5G
 Temperature = 25C
 irradiance of 1000 W/m2
Be sure photos are correct,
photos need captions
Testing on Solar Simulator
 The final step was for the students
to test the wafer
 Using the solar light simulator the
students test the response of the
wafer
Keithley 4200 Solar Light Simulator
 The wafer was tested first without
light and then with light
 Through testing the wafer two I/V
plots were created, shown on the
next slide
Make notes on photos larger and easier to see,
Solar light simulator is not Keithley, I/V plots are created by
Keithley source meter, solar light simulator is made by Scientech
First Fab I/V plot
STA NDA R D I / V P LOT
E X PA ND ED I / V P LOT
This area is too
small to read
Expanded plot needs to be
centered on area of interest
and expanded so it is easier to
Imax Photo=750mA, Isc=60mA, Imp=25mA, Voc=.2V, Vmp=.1V
see
Regular curve
VOC = 0.4V
ISC= 4mA
Vmp= 0.29V
I-V curves

Expand Curve
Imp= 2mA
Max Photocurrent= 9mA
Do not use photos of paper images,
scan for proper quality
STANDARD VIEW
EXPANDED VIEW
PARAMETERS:
Isc= 180
mA
Imp= 90 mA
Imax= 700 mA
.5 V
Vmp= .25 V
Size= 33.64 cm^2
Voc=
Looks like free hand drawn lines,
plots can be larger, plenty of space
I/V Plot Expanded
Poor quality image
I/V Plot
Expand area of interest on I/V plot so it is easier to read, no free hand drawn lines
I/V Plot and Parameters
•
•
•
•
•
Cell Size = 61mm x 74mm
Voc = 0.6V
Make sure of all your data,
Isc = 215mA
reverse leakage current is
Vmp = 0.25V
not correct
Imp = 100mA
•
•
•
•
•
Imax photocurrent = 880mA
Jsc = 47.63 mA/cm^2
Fill factor = 0.19
Efficiency = 6.25%
Reverse leakage current at -2v = 815mA
Conclusion
• During the diffusion process, there was a fire drill and both wafers were
in the furnace for an extra 30 minutes.
• One couldn’t etch everything off even when etched for an additional 20
minutes.
• One worked okay and displayed satisfactory results once tested.
• Also was told to skip the anneal step as well.
Make sure all photos have captions, unknown
meaning of attached photo