Self-timed and asynchronous design
Functions of clock in synchronous design
1) Acts as completion signal
2) Ensures the correct ordering of events
Truly asynchronous design
1) Completion is ensured by careful timing analysis
2) Ordering of events is implicit in logic
Self-timed design
1) Completion ensured completion signal
2) Ordering imposed by handshaking protocol
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Self-timed pipelined datapath
Req
Req
HS
Ack
In
HS
Ack
Start
R1
Req
Done
F1
Start
R2
tpF1
Digital Integrated Circuits
HS
Ack
Done
F2
tpF2
Timing
Req
ACK
Start
R3
Done
F3
Out
tpF3
© Prentice Hall 1995
Completion Signal Generation
LOGIC
In
Out
NETWORK
Start
DELAY MODULE
Done
Using Delay Element (e.g. in memories)
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Completion Signal Generation
Using Redundant Signal Encoding
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Completion Signal in DCVSL
VDD
VDD
B0
Start
Done
B1
B0
B1
In1
In1
In2
In2
PDN
PDN
Start
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Self-timed Adder
VDD
VDD
Start
C0
C0
P0
C1
G0
P1
C2
G1
P2
C3
G2
P3
Start
C4
C4
G3
Start
VDD
C4
C4
C3
C3
C2
C2
C1
C1
Start
Start
C0
C0
Done
P0
K0
C1
P1
K1
C2
P2
K2
C3
P3
C4
C4
(b) Completion signal
K3
Start
(a) Differential carry generation
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Hand-shaking Protocol
(b) Timing diagram
Req
¡
Ack
SENDER
Data
Req
RECEIVER
¬
Ack
(a) Sender-receiver configuration
Data
¿
cycle 1
¿
cycle 2
Senders action
Receivers action
Two-Phase Handshake
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Event Logic —
The Muller C-element
A
F
C
B
(a) Schematic
A
B
Fn+1
0
0
1
0
1
0
1
1
0
Fn
Fn
1
(b) Truth table
VDD
A
S
B
Q
F
A
F
R
B
Static
Dynamic
Digital Integrated Circuits
Timing
© Prentice Hall 1995
2-phase Handshake Protocol
Data
Sender
Receiver
logic
logic
Data Ready
Data Accepted
Req
C
Ack
Handshake logic
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Example: Self-timed FIFO
Out
In
R1
En
R2
R3
Done
Reqi
Req0
C
C
Acko
Acki
Digital Integrated Circuits
C
Timing
© Prentice Hall 1995
4-phase Handshake Protocol (or
RTZ)
Req
Sender’s Action
Receiver’s Action
Ð
¡
Ack
¬
Data
ƒ
¿
¿
cycle 1
cycle 2
Digital Integrated Circuits
Timing
© Prentice Hall 1995
4-phase Handshake Protocol Implementation
Data
Sender
Receiver
logic
logic
Data Accepted
Data Ready
S
C
Req
C
Ack
Handshake logic
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Asynchronous-Synchronous
Interface
fin
Asynchronous
Synchronous System
System
f
Synchronization
Digital Integrated Circuits
Timing
© Prentice Hall 1995
A Simple Synchronizer
Vin
Vout

• Data sampled on Falling Edge of Clock
• Latch will eventually Resolve Signal Value,
but ... this might take infinite time!
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Synchronizer: Output Trajectories
Vin
1
VIH
Undefined
VMS
VIL
0
t

Single Pole Model for Flip-Flop
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Simulated Trajectory versus
One Pole Model
Simulated
Estimated
V (Volt)
2.8
2.6
2.4
2.20
0.2
0.4
0.6
0.8
time (nsec)
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Mean Time to Failure
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Example
Tf = 10 nsec = T
Tsignal = 50 nsec
tr = 1 nsec
t = 310 psec
VIH - VIL = 1 V (VDD = 5 V)
N(T) = 3.9 10-9 errors/sec
MTF (T) = 2.6 108 sec = 8.3 years
MTF (0) = 2.5 sec
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Cascaded Synchronizers Reduce MTF
In
O1
Sync
O2
Sync
Out
Sync

Digital Integrated Circuits
Timing
© Prentice Hall 1995
Arbiters
Req1
Req2
Ack1
Arbiter
Req1
A
Ack2
B
Ack2
Ack1
(a) Schematic symbol
Req2
Req1
(b) Implementation
Req2
A
B
metastable
Ack1
Digital Integrated Circuits
VT gap
(c) Timing diagram
t
Timing
© Prentice Hall 1995
Synchronization at System Level
Chip 1
Chip 2
 1’
 2’
1 “
Logic
Logic
2 “
Clock
Generator
Clock
Generator
I/O Data
Reference clock 
Crystal-based
clock-generator
Digital Integrated Circuits
PC board
Timing
© Prentice Hall 1995
Skew of Local Clocks vs Reference


 ’
 ’
"
"
(a) Skew of local clock signals
with respect of reference clock.
Digital Integrated Circuits
(b) Local clock signals as produced
by PLL based clock generator.
Timing
© Prentice Hall 1995
Phase-Locked Loop Based Clock Generator
Up
Down
Reference
clock
Vcontr
Up
Local
clock
Loop
filter
Charge
pump
Phase
detector
VCO
Down
Clock decode
&
buffer
Divide by
N
 1  2 ...
Acts also as Clock Multiplier
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Ring Oscillator
0
1
2
N-1
(a) VCO
VDD
VDD
M6
M4
M2
In
M1
I ref
Vcontr
M5
I ref
M3
(b) Current starved inverter
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Example of PLL-generated clock
Digital Integrated Circuits
Timing
© Prentice Hall 1995